SC 47D - Semiconductor devices packaging

IEC 63378-2-1:2024 specifies three-dimensional (3D) thermal models of discrete semiconductor packages (TO-243, TO-252 and TO-263), utilized in the steady-state thermal analysis of electronic devices to estimate junction temperatures accurately.
This model is assumed to be made by semiconductor suppliers and to be used by assembly makers of electronic devices.

IEC TR 63378-1:2021(E) specifies the terms and definitions that are commonly used for thermal characteristics of BGA and QFP type semiconductor packages, and guidelines to use these thermal characteristics.

Specifies a small-scale laboratory screening procedure for comparing the relative burning behaviour of vertically or horizontally oriented specimens made from plastic and other non-metallic materials, exposed to a small-flame ignition source of 50 W nominal power.  These test methods determine the linear burning rate and the afterflame/afterglow times, as well as the damaged length of specimens.  Applicable to solid and cellular materials that have an apparent density of not less than 250 kg/m3, determined in accordance with ISO 845.  They do not apply to materials that shrink away from applied flame without igniting;  ISO 9773 should be used for thin flexible materials.  The test methods described provide classification systems which may be used for quality assurance, or the pre-selection of component materials of products.  May be used for the pre-selection of a material, providing positive results are obtained at a thickness equal to the smallest thickness used in the application.  Has the status of a basic safety publication in accordance with Guide 104.

IEC 60191-1:2018 gives guidelines on the preparation of outline drawings of discrete devices, including discrete surface-mounted semiconductor devices with lead count less than 8.
This edition includes the following significant technical changes with respect to the previous edition:
a) the Scope has been extended to include surface-mounted semiconductor devices with a lead count less than 8;
b) a definition of the term "stand-off" has been added;
c) the methods for locating the datum have been extended to be suitable for SMD-packages;
d) the visual identification of terminal position one for automatic handling has been clarified;
e) the rules for the drawing of terminals have been clarified;
f) Table A.1 has been completed with symbols specifically for SMD-packages;
g) Annex B "Standardization philosophy" has been deleted;
h) a normative Annex with special rules for SMD-packages has been added;
i) the examples of semiconductor device drawings have been aligned to state-of-the-art packages including SMD-packages.

IEC 60191-6-13:2016 specifies a design guideline of open-top-type semiconductor sockets for Fine-pitch Ball Grid Array (FBGA) and Fine-pitch Land Grid Array (FLGA). In particular, this part of IEC 60191 establishes the outline drawings and dimensions of the open-top-type test and burn-in sockets applied to FBGA and FLGA. This edition includes the following significant technical changes with respect to the previous edition:
a) BGA package nominal length and width have been newly expanded to 43 mm and 43 mm, respectively. Accordingly, six socket sizes have been added to the socket group numbers 1, 2 and 3, and twenty-two socket sizes have been added to the socket group number 4.

IEC 60191-4:2013 specifies a method for the designation of package outlines and for the classification of forms of package outlines for semiconductor devices and a systematic method for generating universal descriptive designators for semiconductor device packages. The descriptive designator provides a useful communication tool but has no implied control for assuring package interchangeability. This edition includes the following significant technical changes with respect to the previous edition:
a) Material code "S" is added to indicate a silicon based package.
b) Description of "WL" is added to be used for general use.

IEC 60191-6-22:2012 provides the outline drawings and dimensions common to silicon-based package structures and materials of ball grid array packages (BGA) and land grid array packages (LGA).

IEC 60191-6-12:2011 provides standard outline drawings, dimensions, and recommended variations for all fine-pitch land grid array packages (FLGA) with terminal pitch of 0,8 mm or less. This edition includes the following significant changes with respect to the previous edition:
- scope is expanded so that this standard include the square type FLGA. The title of this standard has been changed accordingly: "Rectangular type" has been deleted from the title;
- ball pitch of 0,3 mm has been added;
- datum is changed from the body datum to the ball datum;
- combination lists of D, E, MD, and ME have been revised.

IEC 60191-6-17:2011 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.

IEC 60191-6-20:2010 specifies methods to measure package dimensions of small outline J-lead-packages (SOJ), package outline form E in accordance with IEC 60191-4.

IEC 60191-6-21:2010 specifies methods to measure package dimensions of small outline packages (SOP), package outline form E in accordance to IEC 60191-4.

Defines the measurement of physical performance characteristics of air-conduction hearing aids based on a free-field technique and measured with an ear simulator. Describes methods of measurement for evaluation of the electroacoustical characteristics of hearing aids.

IEC 60191-6-19:2010 specifies measurement methods of the package warpage at elevated temperature and the maximum permissible warpages for Ball Grid Array(BGA), Fine-pitch Ball Grid Array (FBGA), and Fine-pitch Land Grid Array (FLGA). This standard cancels and replaces IEC/PAS 60191-6-19 published in 2008. This first edition constitutes a technical revision.

IEC 60191-6-18:2010 provides standard outline drawings, dimensions, and recommended variations for all square ball grid array packages (BGA), whose terminal pitch is 1 mm or larger. This standard cancels and replaces IEC/PAS 60191-6-18 published in 2008. This first edition constitutes a technical revision. The contents of the corrigenda of May 2010 and July 2010 have been included in this copy.

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition:
a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;
b) editorial modifications on several pages; and
c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.

IEC 60191-6-13:2007 gives a design guideline of open-top-type semiconductor sockets for Fine-pitch Ball Grid Array ("FBGA" hereafter) and Fine-pitch Land Grid Array ("FLGA" hereafter). This standard is intended to establish the outline drawings and dimensions of the open-top-type socket out of the test and burn-in sockets applied to FBGA and FLGA.

IEC 60191-6-16:2007 gives a glossary of semiconductor sockets for BGA, LGA, FBGA and FLGA. This standard intends to establish definitions and unification of terminology relating to tests and burn-in sockets for BGA, LGA, FBGA and FLGA.

IEC 60191-1:2007 gives guidelines on the preparation of outline drawings of discrete devices. For preparation of outline drawings of surface mounted discrete devices, IEC 60191-6 should be referred to as well. The main changes from the previous edition are as follows:
- requirement added for SI-dimensions for new drawings to be published;
- former rules concerning inch-dimensions are given in an informative annex;
- former rules for coding are given in an informative annex; incorporation of the supplements;
- updating of references and
- restructuring and renumbering.

Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.

IEC 60191-6-10:2003 provides the common outline drawings and dimensions for all types of structures and composed materials of plastic very thin small outline non-lead package (hereinafter called P-VSON).

IEC 60191-6-4:2003 covers the requirements for the measuring methods of ball grid array (BGA) dimensions.

Describes a method for the designation and the classification into forms of package outlines for semiconductor devices. Provides a systematic method for generating universal descriptive designators for semiconductor packages.

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is rectangular.

IEC 60191-6-2:2001 covers the requirements for the preparation of drawings of integrated circuit outlines for the various ball terminal packages, e.g. ceramic ball grid array (C-BGA), plastic ball grid array (P-BGA), tape ball grid array (T-BGA) and others as well as column terminal packages, e.g. ceramic column grid array (C-CGA).

Covers the requirements for the design rule of terminal shape plastic packages with gull-wing leads (e.g. QFP, SOP, SSOP, TSOP, etc.)

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array the terminal pitch of which is less than or equal to 0,80 mm.

IEC 60191-6-8:2001 provides the common outline drawings and dimensions for all types of structures and composed materials of glass sealed ceramic quad flatpack (hereinafter called G-QFP). The object of this design guide is to standardize outlines and obtain interchangeability of G-QFP.