IEC 60191-6-17:2011

IEC 60191-6-17 ®
Edition 1.0 2011-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-17: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
pour les boîtiers empilés – Boîtiers matriciels à billes et à pas fins et boîtiers
matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

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IEC 60191-6-17 ®
Edition 1.0 2011-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-17: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
pour les boîtiers empilés – Boîtiers matriciels à billes et à pas fins et boîtiers
matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX U
ICS 31.080.01 ISBN 978-2-88912-331-5

– 2 – 60191-6-17  IEC:2011
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Definitions . 6
4 Terminal position numbering . 7
5 Drawings . 8
6 Dimensions . 16
6.1 Group 1 . 16
6.2 Group 2 . 21
7 Dimension table . 27

Figure 1 – Individual stackable package, P-FBGA (cavity-up) . 8
Figure 2 – Individual stackable package, P-FBGA (cavity-down) . 9
Figure 3 – Individual stackable package, P-FLGA (cavity-up) . 10
Figure 4 – Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) . 11
Figure 5 – Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down
BGA) . 12
Figure 6 – Stacked package outline, P-PFBGA (cavity-down BGA + cavity-up LGA） . 13
Figure 7 – Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) . 14
Figure 8 – Functional gauge . 15
Figure 9 – Pattern of terminal position area . 15

Table 1 – Dimensions, Group 1 . 16
Table 2 – Dimensions Group 2 . 21
Table 3 – Combination of D, E, M , and M , e = 0.80mm pitch FBGA and FLGA . 22
D E
Table 4 – Combination of D, E, M , and M , e = 0,65mm pitch FBGA and FLGA . 23
D E
Table 5 – Combination of D, E, M , and M , e = 0,50mm pitch FBGA and FLGA . 24
D E
Table 6 – Combination of D, E, M , and M , e = 0,40mm pitch FBGA an FLGA . 25
D E
Table 7 – Combination of D, E, M , and M , e = 0,30mm pitch FLGA. 26
D E
Table 8 – Dimension table . 27

60191-6-17  IEC:2011 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-17: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array
(P-PFBGA and P-PFLGA)
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization
comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
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9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-17 has been prepared by subcommittee 47D: Mechanical
standardization for semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/785/FDIS 47D/793/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

– 4 – 60191-6-17  IEC:2011
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 60191 series, under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
60191-6-17  IEC:2011 – 5 –
INTRODUCTION
The trend toward downsizing and higher density of portable electronic devices has driven LSI
packages into smaller and higher density configurations. The market demand
...