Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

IEC 60191-6-17:2011 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.

Normalisation mécanique des dispositifs à semiconducteurs - Partie 6-17: Règles générales pour la préparation des dessins d'encombrement des dispositifs à semiconducteurs à montage en surface - Guide de conception pour les boîtiers empilés - Boîtiers matriciels à billes et à pas fins et boîtiers matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

La CEI 60191-6-17:2011 fournit les dessins d'encombrement et les dimensions pour les boîtiers empilés et les boîtiers empilables individuels sous forme de FBGA ou FLGA.

General Information

Status
Published
Publication Date
26-Jan-2011
Current Stage
PPUB - Publication issued
Start Date
28-Feb-2011
Completion Date
27-Jan-2011
Ref Project
Standard
IEC 60191-6-17:2011 - Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
English and French language
53 pages
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IEC 60191-6-17 ®
Edition 1.0 2011-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-17: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
pour les boîtiers empilés – Boîtiers matriciels à billes et à pas fins et boîtiers
matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

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IEC 60191-6-17 ®
Edition 1.0 2011-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-17: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-17: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
pour les boîtiers empilés – Boîtiers matriciels à billes et à pas fins et boîtiers
matriciels à zone de contact plate et à pas fins (P-PFBGA et P-PFLGA)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX U
ICS 31.080.01 ISBN 978-2-88912-331-5

– 2 – 60191-6-17  IEC:2011
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Definitions . 6
4 Terminal position numbering . 7
5 Drawings . 8
6 Dimensions . 16
6.1 Group 1 . 16
6.2 Group 2 . 21
7 Dimension table . 27

Figure 1 – Individual stackable package, P-FBGA (cavity-up) . 8
Figure 2 – Individual stackable package, P-FBGA (cavity-down) . 9
Figure 3 – Individual stackable package, P-FLGA (cavity-up) . 10
Figure 4 – Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) . 11
Figure 5 – Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down
BGA) . 12
Figure 6 – Stacked package outline, P-PFBGA (cavity-down BGA + cavity-up LGA) . 13
Figure 7 – Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) . 14
Figure 8 – Functional gauge . 15
Figure 9 – Pattern of terminal position area . 15

Table 1 – Dimensions, Group 1 . 16
Table 2 – Dimensions Group 2 . 21
Table 3 – Combination of D, E, M , and M , e = 0.80mm pitch FBGA and FLGA . 22
D E
Table 4 – Combination of D, E, M , and M , e = 0,65mm pitch FBGA and FLGA . 23
D E
Table 5 – Combination of D, E, M , and M , e = 0,50mm pitch FBGA and FLGA . 24
D E
Table 6 – Combination of D, E, M , and M , e = 0,40mm pitch FBGA an FLGA . 25
D E
Table 7 – Combination of D, E, M , and M , e = 0,30mm pitch FLGA. 26
D E
Table 8 – Dimension table . 27

60191-6-17  IEC:2011 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-17: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array
(P-PFBGA and P-PFLGA)
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization
comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and
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closely with the International Organization for Standardization (ISO) in accordance with conditions determined
by agreement between the two organizations.
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consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated
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services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
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Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-17 has been prepared by subcommittee 47D: Mechanical
standardization for semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/785/FDIS 47D/793/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

– 4 – 60191-6-17  IEC:2011
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 60191 series, under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
60191-6-17  IEC:2011 – 5 –
INTRODUCTION
The trend toward downsizing and higher density of portable electronic devices has driven LSI
packages into smaller and higher density configurations. The market demand of higher
density has led to the development of the package stacking technology that enabled
miniaturization and higher functionality. The objective of this design guide is to standardize
outlines and to get interchangeability of individual stackable packages.

– 6 – 60191-6-17  IEC:2011
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-17: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for stacked packages –
Fine-pitch ball grid array and fine-pitch land grid array
(P-PFBGA and P-PFLGA)
1 Scope
This part of IEC 60191 provides outline drawings and dimensions for stacked packages and
individual stackable packages in the form of FBGA or FLGA.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document applies.
IEC 60191-6, Mechanical standardization of semiconductor devices – Part 6: General rules
for the preparation of outline drawings of surface mounted semiconductor device package
IEC 60191-6-5, Mechanical standardization of semiconductor devices – Part 6-5: General
rules for the preparation of outline drawings of surface mounted semiconductor device
packages - Design guide for fine-pitch ball grid array (FBGA)
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60191-6 and the
following apply.
3.1
individual stackable package
package with an array of metallic balls or lands on the underside of the package for the
purpose of surface-mount on a printed circuit board and an array of footprints (lands) on the
upper side of the package for stacking packages
NOTE The individual stackable cavity-up FLGA package is a part of this specification on the premise of stacking
a cavity-down FBGA with cavity-up FLGA.
3.2
stacked package
assembly of multiple individual stackable packages in a stacked configuration
NOTE The top package can be a standard FBGA specified in IEC 60191-6-5 without any footprints on the upper
side of the package. The stand-off height of this standard package, however, shall follow this design guide.
3.3
mould cap height (A )
height of the mould cap which contains wire-bonded die or of the exposed flip chip-bonded die
with respect to the upper substrate surface of the package

60191-6-17  IEC:2011 – 7 –
3.4
distance between the mould cap edge and innermost balls (F)
distance between the mould cap edge of the lower package and the innermost terminals of the
upper package of the stacked package
3.5
upper side land grid pitch (e )
grid pitch of the footprints (lands) on the upper side of the individual stackable package. They
will be interconnected with the terminals of a mating upper package
3.6
parallelism tolerance of the mould cap surface (y )
parallelism tolerance of the top mould-cap surface of the stacked package or the individual
stackable package with respect to the seating plane (datum S), which is established by
contact of the crowns of the balls
NOTE For the stacked package, “y ” is defined as the parallelism tolerance of the top-component surface with
regard to the seating plane of the lowest component.
3.7
coplanarity (y)
flatness tolerance controlling the lowest points of the terminals of the individual stackable
package or the stacked package
3.8
diameter of the upper side lands (b )
diameter of the upper side lands, which will be bonded to the terminals of the mating upper
package
4 Terminal position numbering
When a package is viewed from the terminal side with the index corner in the bottom left
corner position, terminal rows are lettered from bottom to top starting with A, then B, C,,,, AA,
AB, etc., while terminal columns are numbered from left to right starting with 1. Terminal
positions are designated by a row-column grid system and shown as alphanumeric
identification, e.g., A1, B1, or AC34.
The letters I, O, Q, S, X and Z are not used for naming the terminal rows.

– 8 – 60191-6-17  IEC:2011
5 Drawings
Outline drawings are shown in Figure 1, 2, 3, 4, 5, 6 and 7.

E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
2 M
Top view
(1)
y
1 S
S
y CZ
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
M
Bottom view
IEC  164/11
Figure 1 – Individual stackable package, P-FBGA (cavity-up)
e
e
A
A
D
A
A
60191-6-17  IEC:2011 – 9 –
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b
x
2 M M M
1 S A B
(3)
(4)
x S
2 M
Top view
(1)
y
S
S
y CZ
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
M
Bottom view
IEC  165/11
Figure 2 – Individual stackable package, P-FBGA (cavity-down)
A
e
e 1
A
A
D
A
– 10 – 60191-6-17  IEC:2011
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b x
1 M S A M B M
(3)
(4) x S
M
Top view
(1)
y
S
S
Y
y CZ
Y
Section Y-Y
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
1 x
M S A M B M
(3)
(4) x S
M
Bottom view
IEC  166/11
Figure 3 – Individual stackable package, P-FLGA (cavity-up)
e
e
A
A
D
A A
60191-6-17  IEC:2011 – 11 –
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
M
Top view
y S
(1)
F
S
y CZ
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
x
1 M S A M B M
(3)
x S
M
(4) 2
Bottom view
IEC  167/11
Figure 4 – Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA)
A
e
e
A
A
D
A
– 12 – 60191-6-17  IEC:2011
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b
x
M S A M B M
(3)
(4)
x S
M
Top view
y S
(1)
S
y CZ
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
M
Bottom view
IEC  168/11
Figure 5 – Stacked package outline, P-PFBGA
(cavity-down BGA and cavity-down BGA)
A
e
e
A
A
D
A
60191-6-17  IEC:2011 – 13 –
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b
x
1 M S A M B M
(3)
(4) x S
M
Top view
y
S
(1)
S
y CZ
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
x
1 M S A M B M
(3)
(4)
x S
M
Bottom view
IEC  169/11
Figure 6 – Stacked package outline, P-PFBGA
(cavity-down BGA + cavity-up LGA)
A
e
e
A
A
D
A
– 14 – 60191-6-17  IEC:2011
E
B
e
1 2 3 4
A
B
C
D
(2)
n × ∅b x
2 1 M S A M B M
(3)
(4)
x S
M
Top view
y
1 S
(1) F
S
Y
y CZ
Y
Section Y-Y
Side view
e
D
C
B
A
1 2 3 4
n × ∅b
1 x
1 M S A M B M
(3)
x S
M
(4) 2
Bottom view
IEC  170/11
Figure 7 – Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA)
e
e
A
A
A
D
A
60191-6-17  IEC:2011 – 15 –
Common notes for Figure 1 to Figure 7.
(1) The datum S is defined as the seating plane on which a package free stands by contact of the balls.
(2) The hatched zone indicates the index-marking area where A1 terminal locates. The index-marking area is
basically 1/16 of the package body area in compliance with IEC standard. Even if the index mark extends more than
this area, it shall not extend more than 1/4 of the package body area.
(3) The terminal true position tolerances x and x are applied to all terminals.
1 2
(4) The terminal diameter b, b , and b are the largest diameters as measured in a plane parallel to the seating
1 2
plane.
The functional gauge drawing indicates the pattern of the circles, in which terminals locate,
with respect to the datum S, A, and B.
The pattern of terminal position area is composed of the circles, in which terminals locate,
with respect to the datum S.
E
max
e e
∅b
∅b
(5) (6)
IEC  171/11 IEC  172/11
Figure 8 – Functional gauge Figure 9 – Pattern of terminal position area
e
D
max
e
– 16 – 60191-6-17  IEC:2011
6 Dimensions
6.1 Group 1
Dimensions of group 1 are shown in Table 1.
Table 1 – Dimensions, Group 1
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
Package A package nominal dimension is defined as
nominal - -
E × D “package width E × length D”, which is expressed
dimension in the tenths place in millimetre.
For rectangular bodies, the package length D
ranges from 4,0 to 21,0 in increments of 0,5.
Rectangular
For square bodies, the package length D ranges
outlines are
Package from 4,0 to 14,5 in increments of 0,5, and from
D - allowed.
length 15,0 to 21,0 in increments of 1,0.
D includes
Tolerances of D are ± 0,1 for the individual
burr
stackable packages and ± 0,15 for the stacked
packages.
For rectangular bodies, the package width E
ranges from 4,0 to 21,0 in increments of 0,5.
Rectangular
For square bodies, the package width E ranges
outlines are
Package from 4,0 to 14,5 in increments of 0,5, and from
E - allowed.
width 15,0 to 21,0 in increments of 1,0.
E includes
Tolerances of E are ±0,1 for the individual
burr
stackable packages and ±0,15 for the stacked
packages.
The maximum profile height A is categorized as: A includes
Maximum
0,30, 0,40, 0,50, 0,65, 0,80, 1,00, 1,20, 1,40, package
profile A 1,60, 1,80, 2,00, 2,20, or 2,50. - warpage
height and tilt
errors
60191-6-17  IEC:2011 – 17 –
Table 1 – Dimensions, Group 1 (continued overleaf)
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
True (1) For the individual stackable packages:
position
e x
tolerance
0,80 0,15
of
0,65 0,15
terminals
0,50 0,15
with Positional
0,40 0,12
respect to tolerances
0,30 0,12
the body reflect the
x -
datum (2) For the stacked packages: current
process
e x
capabilities
0,80 0,20
0,65 0,20
0,50 0,20
0,40 0,15
0,30 0,15
(1) For the individual stackable packages:

e x
Positional
tolerances
0,80 0,08
reflect the
0,65 0,08
current
0,50 0,05
process
0,40 0,05
Terminal- capabilities.
0,30 0,03
to-terminal e=0,30 is
x (2) For the stacked packages: -
positional applied to the
tolerance e x cavity-up
FLGA.
0,80 0,08
e =0,30 is
0,65 0,08 1
applied to the
0,50 0,05
cavity-down
0,40 0,05
packages
0,30 0,03
– 18 – 60191-6-17  IEC:2011
Table 1 – Dimensions, Group 1 (continued overleaf)
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
(1) For FBGA:
For the
e b MIN NOM MAX
lowest
0,80 0,50 0,36 0,40 0,44
package,
0,45 0,30 0,34 0,38
the stand-off
0,40 0,24 0,28 0,32
height shall
0,65 0,45 0,32 0,36 0,40
Stand-off follow either
A -
1 0,40 0,26 0,30 0,34
height these
0,35 0,20 0,24 0,28
criteria or
0,50 0,35 0,26 0,30 0,34
ones
0,30 0,19 0,23 0,27
specified in
0,40 0,25 0,17 0,20 0,23
IEC 60191-6
-5
(2) For FLGA: A ≤0,10
(1) For FBGA:
e b A (MAX)
0,80 0,50 0,28
0,80 0,45 0,22
0,80 0,40 0,16
0,65 0,45 0,26
0,65 0,40 0,20
0,65 0,35 0,14
0,50 0,35 0,22
0,50 0,30 0,15
A shall be
0,40 0,25 0,14
Maximum taken into
mould cap A - account in
(2) For FLGA:
height specifying
e b A (MAX)
A
0,80 0,50 0,28
0,80 0,45 0,22
0,80 0,40 0,16
0,65 0,45 0,26
0,65 0,40 0,20
0,65 0,35 0,14
0,50 0,35 0,22
0,50 0,30 0,15
0,40 0,25 0,14
60191-6-17  IEC:2011 – 19 –
Table 1 – Dimensions, Group 1 (continued overleaf)
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
Distance
between the
mould cap edge F - -
F ≥ 0,20
and innermost
balls
e  = 0,8
e =0,30 is
0,65
Terminal grid applied to
e    0,50 -
pitch the cavity-
0,40
up FLGA
0,30
e  = 0,80
e =0,30 is
0,65
applied to
Upper side land
0,50
e - the cavity-
grid pitch
0,40
down
0,30
packages
e MIN NOM MAX
0,80 0,45 0,50 0,55
Nominal
0,80 0,40 0,45 0,50
of b is
0,80 0,35 0,40 0,45
recom-
0,65 0,40 0,45 0,50
Ball diameter of b mended
-
0,65 0,35 0,40 0,45
FBGA as the
0,65 0,30 0,35 0,40
diameter
0,50 0,30 0,35 0,40
of raw
0,50 0,25 0,30 0,35
balls.
0,40 0,20 0,25 0,30
e MIN NOM MAX
0,80 0,35 0,40 0,45
e=0,30 is
0,65 0,28 0,33 0,38
Land diameter applied to
0,50 0,20 0,25 0,30
b -
of FLGA the cavity-
0,40 0,15 0,20 0,25
up FLGA
0,30 0,12 0,15 0,18
– 20 – 60191-6-17  IEC:2011
Table 1 – Dimensions, Group 1 (continued overleaf)
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
e MIN NOM MAX
0,80 0,35 0,40 0,45
e =0,30 is
0,65 0,28 0,33 0,38
Diameter of applied to
0,50 0,20 0,25 0,30
the upper b - the
0,40 0,15 0,20 0,25
side lands cavity-down
0,30 0,12 0,15 0,18
packages
e y
0,80 0,10
e=0,30 is
0,65 0,10
applied to
0,50 0,08
Coplanarity y - the
0,40 0,08
cavity-up
0,30 0,05
FLGA
Parallelism For the individual stackable package,
tolerance of y =0,15.
the top y For the stacked package, y =0,20. - -
1 1
mould- cap
surface
Terminal matrix is determined by terminal
pitch e, upper side land pitch e , and matrix
Terminal 1
- -
sizes M and M .
matrix
D E
60191-6-17  IEC:2011 – 21 –
Table 1 – Dimensions, Group 1 (continued overleaf)
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
(1) For both FBGA and FLGA;
Number of
n
n ≤ M  × M
terminals
E D
(M –1) × M
E D
Maximum
M  × (M –1)
E D
Longitudinal
matrix sizes
(M –1) × (M –1)
maximum M E D
D
for these
matrix size
combin-
(2) In addition to the above algorithms, the -
ations are
following combinations are allowed for
listed in
FLGA:
Table 3 to
n ≤ (M +1) × M
Lateral matrix
E D
M Table 7
E
size      M  × (M +1)
E D
(M +1) × (M +1)
E D
6.2 Group 2
Dimensions of group 2 are shown in Table 2.
Table 2 – Dimensions Group 2
Unit: mm
Recom-
Term Symbol Specification mended Remarks
value
Diameter of
the circle that
contains
entire b b = b(MAX) + x - -
3 3 1
terminal with
respect to the
body datum
Diameter of
the circle that
contains
entire b b = b(MAX) + x - -
4 4 2
terminal with
respect to
other balls
– 22 – 60191-6-17  IEC:2011
6.3 Combination of D, E, M , and M
D E
Combinations of D, E, M , and M are shown in Table 3, 4, 5, 6 and 7
D E
Table 3 – Combination of D, E, M , and M , e = 0,80mm pitch FBGA and FLGA
D E
D or E M or M (M -1) or (M -1) (M +1) or (M +1)
D E D E D E
(Only for FLGA)
4,0 4 3 5
4,5
5 4 6
5,0
5,5 6 5 7
6,0
7 6 8
6,5
7,0
8 7 9
7,5
8,0 9 8 10
8,5
10 9 11
9,0
9,5 11 10 12
10,0
12 11 13
10,5
11,0
13 12 14
11,5
12,0 14 13 15
12,5
15 14 16
13,0
13,5 16 15 17
14,0
17 16 18
14,5
15,0
18 17 19
15,5
16,0 19 18 20
16,5
20 19 21
17,0
17,5 21 20 22
18,0
22 21 23
18,5
19,0
23 22 24
19,5
20,0 24 23 25
20,5
25 24 26
21,0
60191-6-17  IEC:2011 – 23 –
Table 4 – Combination of D, E, M , and M , e = 0,65mm pitch FBGA and FLGA
D E
D or E M or M (M -1) or (M -1) (M +1) or (M +1)
D E D E D E
(Only for FLGA)
4,0 5 4 6
4,5
6 5 7
5,0
5,5 7 6 8
6,0 8 7 9
6,5 9 8 10
7,0
10 9 11
7,5
8,0 11 10 12
8,5 12 11 13
9,0
13 12 14
9,5
10,0 14 13 15
10,5 15 14 16
11,0
16 15 17
11,5
12,0 17 16 18
12,5 18 17 19
13,0 19 18 20
13,5
20 19 21
14,0
14,5 21 20 22
15,0 22 21 23
15,5
23 22 24
16,0
16,5 24 23 25
17,0 25 24 26
17,5
26 25 27
18,0
18,5 27 26 28
19,0 28 27 29
19,5 29 28 30
20,0
30 29 31
20,5
21,0 31 30 32
– 24 – 60191-6-17  IEC:2011
Table 5 – Combination of D, E, M , and M , e = 0,50mm pitch FBGA and FLGA
D E
D or E M or M (M -1) or (M -1) (M +1) or (M +1)
D E D E D E
(Only for FLGA)
4,0 7 6 8
4,5 8 7 9
5,0 9 8 10
5,5 10 9 11
6,0 11 10 12
6,5 12 11 13
7,0 13 12 14
7,5 14 13 15
8,0 15 14 16
8,5 16 15 17
9,0 17 16 18
9,5 18 17 19
10,0 19 18 20
10,5 20 19 21
11,0 21 20 22
11,5 22 21 23
12,0 23 22 24
12,5 24 23 25
13,0 25 24 26
13,5 26 25 27
14,0 27 26 28
14,5 28 27 29
15,0 29 28 30
15,5 30 29 31
16,0 31 30 32
16,5 32 31 33
17,0 33 32 34
17,5 34 33 35
18,0 35 34 36
18,5 36 35 37
19,0 37 36 38
19,5 38 37 39
20,0 39 38 40
20,5 40 39 41
21,0 41 40 42
60191-6-17  IEC:2011 – 25 –
Table 6 – Combination of D, E, M , and M , e = 0,40mm pitch FBGA an FLGA
D E
D or E M or M (M -1) or (M -1) (M +1) or (M +1)
D E D E D E
(Only for FLGA)
4,0 8 7 9
4,5 10 9 11
5,0 11 10 12
5,5 12 11 13
6,0 13 12 14
6,5 15 14 16
7,0 16 15 17
7,5 17 16 18
8,0 18 17 19
8,5 20 19 21
9,0 21 20 22
9,5 22 21 23
10,0 23 22 24
10,5 25 24 26
11,0 26 25 27
11,5 27 26 28
12,0 28 27 29
12,5 30 29 31
13,0 31 30 32
13,5 32 31 33
14,0 33 32 34
14,5 35 34 36
15,0 36 35 37
15,5 37 36 38
16,0 38 37 39
16,5 40 39 41
17,0 41 40 42
17,5 42 41 43
18,0 43 42 44
18,5 45 44 46
19,0 46 45 47
19,5 47 46 48
20,0 48 47 49
20,5 50 49 51
21,0 51 50 52
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