Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.

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Published
Publication Date
28-Sep-2004
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DELPUB - Deleted Publication
Completion Date
26-Nov-2009
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IEC 60191-6:2004 - Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Released:9/29/2004 Isbn:2831865484
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INTERNATIONAL IEC
STANDARD 60191-6
Second edition
2004-09
Mechanical standardization
of semiconductor devices –
Part 6:
General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
Reference number
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the

60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.

Consolidated editions
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edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the

base publication incorporating amendment 1 and the base publication incorporating

amendments 1 and 2.
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INTERNATIONAL IEC
STANDARD 60191-6
Second edition
2004-09
Mechanical standardization
of semiconductor devices –
Part 6:
General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
 IEC 2004  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale W
International Electrotechnical Commission
МеждународнаяЭлектротехническаяКомиссия
For price, see current catalogue

– 2 – 60191-6  IEC:2004(E)
CONTENTS
FOREWORD.3

1 Scope.5

2 Normative references .5

3 Definitions .5

4 Design rules .7

5 Dimensions to be specified.7

6 Notes .7

Annex A (informative) Illustration of the rules.11
A.1 Gull-wing lead package with two parallel rows of terminals (SOP,TSOP Type 2).13
A.2  Gull-wing lead package with two parallel rows of terminals (TSOP Type 1).16
A.3 Gull-wing lead package with one row of terminals on each of four sides (QFP) .19
A.4 J-bent lead package with two parallel rows of terminals (SOJ) .22
A.5 Folded lead package with one row of terminals on each of four sides (QFJ).25
A.6 Leadless package .29
A.7-1 Ball grid array package (BGA) Type 1 .32
A.7-2 Ball grid array package (BGA) Type 2 .35

Annex B (informative) Optional table format.38

Figure 1 – Illustrations of terminal projection zone .12
Figure 2 – Isometric view of an example of gauge.12

60191-6  IEC:2004(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings of

surface mounted semiconductor device packages

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
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indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 60191-6 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
This second edition of IEC 60191-6 cancels and replaces the first edition, published in 1990
and its amendment 1 (1999), and constitutes a technical revision. This includes the following
significant changes with respect to the previous edition: improvement of the geometrical
drawing format and addition of the examples of the drawing of major packages.

– 4 – 60191-6  IEC:2004(E)
The text of this standard is based on the following documents:

FDIS Report on voting
47D/584/FDIS 47D/587/RVD
Full information on the voting for the approval of this standard can be found in the report on

voting indicated in the above table.

The committee has decided that the contents of this publication will remain unchanged until

the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in

the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

60191-6  IEC:2004(E) – 5 –
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings of

surface mounted semiconductor device packages

1 Scope
This part of IEC 60191 gives general rules for the preparation of outlines drawings of surface-
mounted semiconductor devices. It supplements IEC 60191-1 and 60191-3. It covers all surface-
mounted devices-discrete semiconductors as well as integrated circuits classified as form E in
Clause 3 of IEC 60191-4.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60191-1:1966, Mechanical standardization of semiconductor devices – Part 1: Preparation of
drawings of semiconductor devices
IEC 60191-3:1999, Mechanical standardization of semiconductor devices – Part 3: General
rules for the preparation of outline drawings of integrated circuits
IEC 60191-4:1999, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor devices
ISO 1101:1983, Technical drawings – Geometrical tolerancing – Tolerancing of form,
orientation, location and run-out – Generalities, definitions, symbols, indications on drawings
3 Definitions
For the purposes of this document, the following definitions apply.

3.1
seating plane
plane which designates the plane of contact of the package, including any stand-off, with the
surface on which it will be mounted
NOTE This plane is often used as the reference plane.
3.2
reference plane
plane parallel to the seating plane at a distance A3 above seating plane (does not apply to
leadless package)
– 6 – 60191-6  IEC:2004(E)
The distance A3 is known as the reference plane distance. It determines the terminal

projection zone (see Figure 1).

NOTE This distance is a theoretical dimension which is not related to any feature of the package. Its value is

chosen for each package so the length of terminal projection zone L is a good approximation of the terminal
p
length used for mounting, e.g. the length of the part of the terminal that is soldered to the substrate.

3.3
terminal position area
maximum area on the seating plane within which the terminal projection zone is located,
taking into account the maximum values of L and b

p p
The surface of the terminal position area is equal to l × b with, generally
1 3
l = L max. + (HDmax – HDmin)/2
1 p
= L max. + (HEmax – HEmin)/2
p
and b = b max. + x
3 p
Checking can be carried out by means of an appropriate gauge (see Figure 2).
3.4
pattern of terminal position areas
group of all terminal position areas of a leaded package or folded lead package in the seating
plane
For a leadless package, it is the projection of its metallized pads or terminals on the seating
plane.
The true positions of the centres of the terminal position areas are located on a grid with as
modulus
e / e or  e / e
D E
The pattern of terminal position areas does not include tolerances stemming from mounting
substrates (printed board) design and placement machine accuracy.
3.5
coplanarity of terminals
the requirement for coplanarity of terminals is given in a tolerance frame showing the ISO
symbol for profile of a surface, the tolerance value y and the reference to the seating plane
Where the part of the terminal intended for soldering is a flat zone of defined dimension b × l,
with nominal position on the seating plane – e.g. pads of leadless packages – then the
requirement for coplanarity of terminals is strictly the ISO requirement for flatness applied to
these zones.
In all the other cases, the requirement for coplanarity of terminals is clarified by note.
3.6
datum
theoretically, the exact geometrical reference is established for controlling the tolerance zone
when specifying a geometrical tolerance as a related feature
NOTE Datum S should be established by seating plane.

60191-6  IEC:2004(E) – 7 –
4 Design rules
The outline drawing of a surface-mounted semiconductor device package shall comprise in

the given sequence
– the drawing (strictly speaking);

– th
...

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