WG 2 - TC 91/WG 2

IEC TR 61191-9:2023, which is a Technical Report, applies to electronic and electromechanical automotive circuit board assemblies and describes current best practices for dealing with electrochemical reactions like migration or corrosion and ionic contamination on the surface of a circuit board as one failure mode under humidity load. This document deals with the evaluation of materials and manufacturing processes for the manufacturing of electronic assemblies with focus on their reliability under humidity loads. The electrical operation of a device in a humid environment can trigger electrochemical reactions that can lead to short circuits and malfunctions on the assembly. In this context, a large number of terms and methods are mentioned, such as CAF (conductive anodic filament), anodic migration phenomena, dendrite growth, cathodic migration, ROSE (resistivity of solvent extract), ionic contamination, SIR (surface insulation resistance), impedance spectroscopy, etc., which are used and interpreted differently. The aim of the document is to achieve a uniform use of language and to list the possibilities and limitations of common measurement methods. The focus of the document is on the error pattern of electrochemical migration on the surface of assemblies with cathodic formation of dendrites.
Evaluation of different test methods of control units under high humidity load are not part of this document.

IEC PAS 61191-10:2022(E) provides guidelines which deal with the requirements for the protective coating,
its properties, as well as the application of liquid coating materials for electronic assemblies. These guidelines help control in practice the application of protective coatings from the layout to the functional test of the assembly after coating.

IEC TR 61191-8:2021(E) gives guidelines for dealing with voiding in surface-mount solder joints of printed board assemblies for use in automotive electronics. This technical report focuses exclusively on voids in solder joints connecting packaged electronic or electromechanical components with printed boards (PBs). Voids in other solder joints (e.g. in a joint between a silicon die and a substrate within an electronic component, solder joints of through-hole components, etc.) are not considered. The technical background for the occurrence of voids in solder joints, the potential impact of voiding on printed board assembly reliability and functionality, the investigation of voiding levels in sample- and series-production by use of X‑ray inspection as well as typical voiding levels in different types of solder joints are discussed. Recommendations for the control of voiding in series production are also given. Annex A collects typical voiding levels of components and recommendations for acceptability.

IEC 61191-1:2018 prescribes requirements for materials, methods and verification criteria for producing quality soldered interconnections and assemblies using surface mount and related assembly technologies. This part of IEC 61191 also includes recommendations for good manufacturing processes. This edition includes the following significant technical changes with respect to the previous edition:
- the requirements have been updated to be compliant with the acceptance criteria in IPC‑A-610F;
- the term "assembly drawing" has been changed to "assembly documentation" throughout;
- references to IEC standards have been corrected;
- Clause 9 was completely rewritten;
- Annex B was removed because there are already procedures for circuit board assemblies.

IEC 61190-1-3:2017 prescribes the requirements and test methods for electronic grade solder alloys, for fluxed and non-fluxed bar, ribbon, powder solders and solder paste, for electronic soldering applications and for "special" electronic grade solders. For the generic specifications of solder alloys and fluxes, see ISO 9453. This document is a quality control document and is not intended to relate directly to the material's performance in the manufacturing process.
This edition includes the following significant technical changes with respect to the previous edition:
a) The maximum impurity level of Pb has been revised and the table of lead free solder alloys includes some additional lead free solder alloys.

IEC 61191-4:2017 prescribes requirements for terminal soldered assemblies. The requirements pertain to those assemblies that are entirely terminal/wire interconnecting structures or to the terminal/wire portions of those assemblies that include other related technologies (i.e. surface mounting, through-hole mounting, chip mounting).
This edition includes the following significant technical changes with respect to the previous edition:
The requirements have been updated to be compliant with the acceptance criteria in IPC‑A-610F.

IEC 61191-3:2017 prescribes requirements for lead and hole solder assemblies. The requirements pertain to those assemblies that totally use through-hole mounting technology (THT), or the THT portions of those assemblies that include other related technologies (i.e.. surface mount, chip mounting, terminal mounting).
This edition includes the following significant technical changes with respect to the previous edition:
a) The requirements have been updated to be compliant wit the acceptance criteria in IPC-A-610F.

IEC 61191-2:2017 gives the requirements for surface mount solder connections. The requirements pertain to those assemblies that are totally surface mounted or to the surface mounted portions of those assemblies that include other related technologies (e.g. through-hole, chip mounting, terminal mounting, etc.).
This edition includes the following significant technical changes with respect to the previous edition:
a) the requirements have been updated to be compliant with the acceptance criteria in IPC‑A-610F;
b) some of the terminology used in the document has been updated;
c) references to IEC standards have been corrected;
d) five termination styles have been added.
The contents of the corrigendum of September 2019 have been included in this copy.

IEC 61190-1-2:2014-02(en-fr) specifies general requirements for the characterization and testing of solder pastes used to make high-quality electronic interconnections in electronics assembly. This standard serves as a quality control document and is not intended to relate directly to the material's performance in the manufacturing process. This edition includes the following significant technical changes with respect to the previous edition:
a) modification of the solder powder size in Table 2;
b) addition of the information of "Reflow condition and profile" in Annex B;
c) addition of a new Annex C.

IEC 61191-2:2013 gives the requirements for surface mount solder connections. The requirements pertain to those assemblies that are totally surface mounted or to the surface mounted portions of those assemblies that include other related technologies (e.g. through-hole, chip mounting, terminal mounting, etc.). This edition includes the following significant technical changes with respect to the previous edition:
- IPC-A-610 on workmanship has been included as a normative reference;
- some of the terminology used in the document has been updated;
- references to IEC standards have been corrected;
- the use of lead-free solder paste and plating are addressed.

IEC 61191-1:2013 prescribes requirements for materials, methods and verification criteria for producing quality soldered interconnections and assemblies using surface mount and related assembly technologies. It also includes recommendations for good manufacturing processes. This edition includes the following significant technical changes with respect to the previous edition:
- reference standard IEC 61192-1 has been replaced by IPC-A-610;
- some of the terminology has been updated;
- references to IEC standards have been corrected;
- the use of lead-free alloys in the assembly have been added.

IEC 61190-1-3:2007 prescribes the requirements and test methods for electronic grade solder alloys, for fluxed and non-fluxed bar, ribbon, powder solders and solder paste, for electronic soldering applications and for "special" electronic grade solders. For the generic specifications of solder alloys and fluxes, see ISO 9453, ISO 9454-1 and ISO 9454-2. This standard is a quality control document and is not intended to relate directly to the material's performance in the manufacturing process. The main changes with regard to the first edition concern a definition of lead-free solder alloy and an amendment to Table B.1 concerning lead-free solder alloys.

IEC 61191-6:2010 specifies the evaluation criteria for voids on the scale of the thermal cycle life, and the measurement method of voids using X-ray observation. This part of IEC 61191 is applicable to the voids generated in the solder joints of BGA and LGA soldered on a board. This part of IEC 61191 is not applicable to the BGA package itself before it is assembled on a board. This standard is applicable also to devices having joints made by melt and re-solidification, such as flip chip devices and multi-chip modules, in addition to BGA and LGA. This standard is not applicable to joints with under-fill between a device and a board, or to solder joints within a device package. This standard is applicable to macrovoids of the sizes of from 10 µm to several hundred micrometres generated in a soldered joint, but is not applicable to smaller voids (typically, planar microvoids) with a size of smaller than 10 µm in diameter. This standard is intended for evaluation purposes and is applicable to research studies, off-line production process control and reliability assessment of assembly.

Defines VHSIC Hardware Description Language (VHDL)accurately. Its primary audiences are the implementor of tools supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books,tutorials,and classes to learn the language in some detail prior to reading this standard. These resources generally focus on how to use the language,rather than how a VHDL-compliant tool is required to behave. This publication has the status of a double logo IEEE/IEC standard

Specifies general requirements for the classification and testing of soldering fluxes for high-quality interconnections in electronics assembly. This standard is a flux characterization, quality control, and procurement document for solder flux and flux containing material in electronics assembly technology.

Prescribes the requirements and test methods for electronic grade solder alloys, for fluxed and non-fluxed bar, ribbon, and powder solders, other than solder paste, for electronic soldering applications as well as for special electronic grade solders. This standard is a quality control document (not intended to relate directly to the material performance in the manufacturing process).

Specifies general requirements for the characterization and testing of solder pastes used to make high quality electronic interconnections in electronics assembly. Prescribes a quality control document (not intended to relate directly to the material performance in the manufacturing process).

Defines methods of registration and analysis of defects on soldered printed board assemblies. These methods are described to allow effective comparison of performance between products, processes and production locations, and can serve as a basis for general quality improvement.

Prescribes requirements for materials, methods and verification criteria for producing quality soldered interconnections and assemblies using surface mounted and related assembly technologies. Also included are recommendations for good manufacturing processes.

Prescribes the requirements for surface mounted solder connections. The requirements pertain to those assemblies that are totally surface mounted or to the surface mounted portions of those assemblies that include other related technologies (e.g. through-hole, chip mounting, terminal mounting, etc.).

Prescribes requirements for lead and hole solder assembly. The requirements pertain to those assemblies that are totally lead and hole, through-hole mounting technology (THT), or the THT portions of those assemblies that include other related technologies (i.e. surface mount, chip mounting, terminal mounting).

Prescribes requirements for terminal soldered assemblies. The requirements pertain to those assemblies that are totally terminal/wire interconnecting structures or to the terminal/wire portions of those assemblies that include other related technologies (i.e. surface mounting, through-hole mounting, chip mounting)

IEC 61192-5:2007 provides information and requirements that are applicable to modification, rework and repair procedures for soldered electronic assemblies. It is applicable to specific processes used to manufacture soldered electronic assemblies where components are attached to printed boards and to the relevant parts of resulting products. The standard is also applicable to activities that can form part of the work in assembling mixed technology products. It also contains guidance on design matters where they have relevance to rework.

Specifies requirements for workmanship in soldered surface-mounted electronic assemblies and multichip modules on organic substrates, on printed boards, and on similar laminates attached to the surface(s) of inorganic substrates. Applies to assemblies that are totally surface-mounted and to the surface-mount portions of assemblies that include other related assembly technologies, for example, through-hole mounting.

Specifies general requirements for workmanship in soldered electronic assemblies on printed boards and on similar laminates attached to the surface(s) of organic substrates. Defines requirements and guidelines for good workmanship and practice in the preparation, soldering, inspection and testing of electronic and electrical assemblies. Enables achievement of high yields and high product quality through process control in production.

Specifies general requirements for workmanship in through-hole mount soldered assemblies on organic substrates, on printed boards, and on similar laminates attached to the surface(s) of inorganic substrates. It applies to assemblies that are totally through-hole or mixed assemblies that include surface-mounting or other related assembly technologies, for example, terminals, wires.

Specifies general requirements for workmanship in terminal soldered assemblies on organic substrates, on printed boards, and on similar laminates attached to the surface(s) of inorganic substrates. It applies to assemblies that are totally terminals or mixed assemblies that include surface-mounting or other related assembly technologies, for example through-hole, wires.

Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions,such as text output display commands; compiler directives,such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines,task/function routines,and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI This publication has the status of a double logo IEEE/IEC standard

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

This set of packages provides a standard for the declaration of most frequently used real and complex elementary functions required for numerically oriented modeling applications. Use of these packages with their defined data types, constants, and functions is intended to provide a mechanism for writing VHDL models (compliant with IEEE Std 1076-1993) that are portable and interoperable with other VHDL models adhering to this standard. The standard serves a broad class of applications with reasonable ease of use and requires implementations that are of high quality. This standard includes package bodies, as described in annex B, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

IEC 61691-2:2001 is embodied in the Std_logic_1164 package package body. This standard is based on IEEE Std 1164-1993: Multivalue logic system for VHDL model interoperatibility.

Provides rules that describe ALF and how tool developers, integrators, library creators, and library users should use it.

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard

This standard is based on IEEE Std 1076. It describes the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)