IEC 61523-2:2002
(Main)Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
General Information
- Status
- Withdrawn
- Publication Date
- 16-May-2002
- Withdrawal Date
- 31-May-2011
- Technical Committee
- TC 91 - Electronics assembly technology
- Drafting Committee
- WG 2 - TC 91/WG 2
- Current Stage
- WPUB - Publication withdrawn
- Start Date
- 01-Jun-2011
- Completion Date
- 14-Feb-2026
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Frequently Asked Questions
IEC 61523-2:2002 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries". This standard covers: Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
IEC 61523-2:2002 is classified under the following ICS (International Classification for Standards) categories: 35.240.50 - IT applications in industry. The ICS classification helps identify the subject area and facilitates finding related standards.
IEC 61523-2:2002 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
INTERNATIONAL IEC
STANDARD
61523-2
First edition
2002-05
Delay and power calculation standards –
Part 2:
Pre-layout delay calculation specification
for CMOS ASIC libraries
Reference number
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the
60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
Consolidated editions
The IEC is now publishing consolidated versions of its publications. For example,
edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
base publication incorporating amendment 1 and the base publication incorporating
amendments 1 and 2.
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INTERNATIONAL IEC
STANDARD
61523-2
First edition
2002-05
Delay and power calculation standards –
Part 2:
pre-layout delay calculation specification
for CMOS ASIC libraries
IEC 2002 Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale
W
International Electrotechnical Commission
Международная Электротехническая Комиссия
For price, see current catalogue
– 2 – 61523-2 IEC:2002(E)
CONTENTS
Foreword .3
1 Scope and object .5
2 Normative references .5
3 Relations with other companion standards activities .6
4 Terms and definitions .6
5 Pre-layout delay calculation method for CMOS ASIC libraries .7
Annex A (informative) Four points interpolation .15
Annex B (informative) Three ponts interpolation .17
Annex C (informative) Selection method of interpolation plane .20
Annex D (informative) Theoretical accuracy comparison between two interpolation
methods .25
Annex E (informative) Application example.31
Annex F (informative) Example of Cn, Ts, Tpd tables by delay calculation language .35
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Two Step Delay Calculation
step 1: Calculate < Input Slew Rate >
step 2: Calculate < Port to Port Propagation Delay;Tpd
by using < Input Slew Rate >
. .
. .
. .
CL0 CL1
Figure 1: CMOS Delay Model & Calculation Steps
5.2. Table Look-Up delay calculation method
The table look-up model of delay calculation specification uses 3 types of table models. First is the
‘Net capacitance table’ (named Cn table). This table is used for ‘load capacitance’ estimation. Second is
‘Input slew rate table’ (named Ts table), and 3rd is ‘Port to port propagation delay time table’ (named
Tpd table). As a first step of delay calculation, input slew rate is calculated by using net capacitance, and
Ts table. And then, port to port propagation delay can be calculated by using net capacitance, input slew
rate, and Tpd table.
The propagation delay is calculated using a Tpd table by applying one of the methods for interpolation
approximation. One is bilinear interpolation approximation by 4 points. This method will be de facto
standard from major EDA vendors. The other is linear interpolation approximation by 3 points. This
approximation is more accurate than bilinear interpolation, and both linear and bilinear methods can use
the same Tpd table.
5.2.1 Load capacitance estimation
First step is to estimate the load capacitance of each net. Load capacitance is estimated
by the following rule.
Load Capacitance = (Input port capacitance) + estimated net capacitanc
where (Input port capacitance) is the summation of input port capacitance
$%&#'(2"!",./:20020.) !"9 "!
in the net
The estimated capacitance is a function of fanout and estimated size which is calculated by summing
up the cell size of all cells in the top hierarchy to which the net belongs. So, to estimate capacitance, a
two dimensional table is used. Indices of the table are fanout and sum of cell size. Different tables
should be prepared according to chip size(standard cell) or type of base array(gate array). As shown in
figure 2, each net capacitance is calculated by step interpolation using Cn table.
Capacitance
Fanout
1,1K 1,2 2,3 3,4 4,10 10,40 40,100
1K,4K
4K,10K
10K,30K
Size
Figure 2. Example of net capacitance estimation
5.2.1.1 Cn table specification
Cn table is a 2 dimensional matrix specified for each design methodology, i.e. gate array, standard
cell.(See Annex F.1)
The 1st index is size( S[i]): sum of cell size, or sum of number of gates, or base array size for gate
array.
The 2nd index( Fo[j]) is the number of fanout in net.
The value( C[i][j]) is pre-defined capacitance value.
where
1 i M (M is effective maximum number of size values used),
1 j N (N is effective maximum number of fanout values used).
C[i][j] has a real value.
Values of S[i] and Fo[j] have 2 integer values each, which are in the following relationship;
0 first value second value,
second value of S[i] = first value of S[i+1],
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!"10"!
second value of Fo[j] = first value of Fo[j+1],
first value effective value second value,
Cn[i][j] is real value, unit is pF or fF.
5.2.1.2 Net capacitance( CnE ) estimation rule
The Net capacitance estimation (CnE) is specified below.
If the size is ranged in S[i] and the fanout is ranged in Fo[j]
then
CnE = Cn[i][j] . .(1)
If the size is less than the first value of S[1], then set i to 1.
If the size is greater than or equal to the second vale of S[M], then set i to M.
If the fanout is less than the first value of Fo[1], then set j to 1.
If the fanout is greater than or equal to the second value of Fo[N],
then set j to N.
Then apply it to function (1).
5.2.2 Input slew rate calculation
Input slew rate is calculated by linear interpolation shown in figure 3.
Time
S[N]
S[i+1]
S0
S[i]
S[1]
C[1] C[i] CL0 C[i+1] C[N] Cap.
Figure 3. Example of input slew rate calculation
5.2.2.1 Ts table specification
A Ts table is a one dimensional matrix for each transient timing group.(See F.2)
The index( C[i]) is the capacitance of the net which includes the input of the target gate,
The value( S[i]) is the characterized input slew rate
where
2 i N (N is effective maximum number of capacitance values used,
C[i] has 1 real value of capacitance, unit is pF or fF,
0 C[i] C[i+1],
S[i] has 1 real value of time, unit is ns.
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5.2.2.2 Input slew rate( Ts0) calculation rule
To calculate input slew rate by Ts table, the linear interpolation method will be applied between C[i]
and C[i+1].
If target input capacitance( C0) is ranged between C[i] and C[i+1]
then
Ts0 = a C0 + b .(2)
where a = (S[i+1] S[i]) (C[i+1] C[i])
b = (C[i+1] S[i] C[i] S[i+1]) (C[i+1] C[i]).
If target input capacitance is less than C[1], then set i to 1.
If target input capacitance is greater than C[N],
then set i to N-1.
Then apply it to function of (2).
5.2.3 Port to Port propagation delay time calculation
Port to port delay is calculated using as Tpd table ,shown in Figure 4, using either a linear or a bilinear
interpolation method.
Time
Tpd0 Tpd[i+1][j+1]
Tpd[i+1][j]
Tpd[i][[j+1]
Ts[1] Ts[i] Ts0 Ts[i+1] Ts[M] Time
Cl[1]
Cl[j]
Cl0
Cl[j+1]
Cl[N]
Capacitance
Figure 4. Example of propagation delay time calculation
5.2.3.1 Tpd table specification
Tpd table is a two dimensional matrix for each transient timing group.(See F.3)
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The 1st index ( Ts[i]) is input slew rate ,
The 2nd index( Cl[j]) is load capacitance of output of gate,
The value ( Tpd[i][j]) is characterized propagation delay time,
where
2 i M (M is effective maximum number of input slew rates used),
Ts[i] has 1 real value of time, unit is ns,
0 Ts[i] Ts[i+1],
2 j N ( N is effective maximum number of load capacitance values of
gate output used),
Cl[j] has 1 real value of capacitance, unit is pF or fF,
0 Cl[j] Cl[j+1],
Tpd[i][j] has 1 real value of time, unit is ns,
Tpd[i][j] Tpd[i+1][j], Tpd[i][j+1] Tpd[i+1][j+1].
5.2.3.2 Selection rule of 4 points
To calculate port to port propagation delay time by Tpd table, both linear and bilinear
interpolation method are applied among 4 points .
(Tpd[i][j],Tpd[i+1][j],Tpd[i][j+1],Tpd[i+1][j+1]) as shown in Figure 4.
If calculated Ts0 is ranged between Ts[i] and Ts[i+1] and
if target load capacitance( CL1) is ranged between Cl[j] and Cl[j+1],
then select
Tpd[i][j],Tpd[i+1][j],Tpd[i][j+1],Tpd[i+1][j+1].
If Ts0 is less than Ts[1], set i to 1.
If Ts0 is greater than Ts[M], set i to M-1.
If CL1 is less than Cl[1], set j to 1.
If CL1 is greater than Cl[N], set j to N-1.
Then select
Tpd[i][j],Tpd[i+1][j],Tpd[i][j+1],Tpd[i+1][j+1].
5.2.3.3 Propagation delay time( Tpd0) approximation
Two methods are specified here.
One is to solve bilinear interpolation (Z = a X + b Y + c X Y + d).
See Annex A in details.
Another method is the linear interpolation based on 3 points which are selected from
4 points shown in figure 5. (See Annex F.4 for detail interpolation example)
5.2.3.3.1 Selection rule of 3 points
Tpd is slowly increasing convex function with negative second derivatives.
In this case, 3 point linear approximation is more accurate than bilinear interpolation
$%&#'(2"!",./:20020.) !"13 !
,especially more accurate for smaller tables.
See Annex B for details.
Tpd[i+1][j+1]
Tpd[i+1][j+1]
Tpd[i][j+1]
Tpd[i+1][j]
Tpd[i][j+1]
Tpd[i][j]
Tpd[i+1][j]
Tpd[i][j]
Figure 5. Selection of 3 points
* 3 points are selected using plane function G(slew, load) which consist of
Tpd[i][j], Tpd[i+1][j], and Tpd[i][j+1] and apply following rule. (See Annex C.)
If G(Ts[i+1], Cl [j+1]) is greater than or equal to Tpd[i+1][j+1],
Then select 2 planes which consist of the following 3 points.
One is Tpd[i+1][j], Tpd[i][j+1], and Tpd[i][j]
Another is Tpd[i+1][j], Tpd[i][j+1] and Tpd[i+1][j+1]
If G(Ts[i+1], Cl [j+1]) is less than Tpd[i+1][j+1],
then select 2 planes which consist of the following 3 points.
One is Tpd[i][j], Tpd[i+1][j+1], and Tpd[i+1][j].
Another is Tpd[i][j], Tpd[i+1][j+1], and Tpd[i][j+1] .
After that ,select 3 points which include point (Ts0, CL1).
See Annex E for examples.
See Annex D for the evaluation of the accuracy comparison between two method.
5.2.3.3.2 Tpd calculation by linear interpolation method
Tpd is calculated using the following equation. ( See Annex B)
Z = Tpd[i][j+1] +(Tpd[i][j] Tpd[i][j+1]) (Cl[j] Cl[j+1]) (CL1 Cl[j+1])
Tpd0 = Z + (Tpd[i+1][j]-Tpd[j][j])/(Ts[i+1]-Ts[i])x(Ts0-Ts[i]) .(3)
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!"14"!
Tpd[i][j+1]
Cl[j+1]
Tpd0
CL1
Cl[j] Tpd[i][j] Tpd[j+1][j]
Ts[i] Ts0 Ts[i+1]
Figure 6. Interpolation for right angle triangle
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Annex A. (Informative)
Four points interpolation
Here, we explain bilinear interpolation by four trapezoidal points.
#
'"% '" '""
!"
Figure A1
$#
(
(%
'%%
!% '%"
&%% $&"% $) &"" &%"
)
When four trapezoidal points(x11,y1), (x12,y1), (x21,y2), (x22,y2) are given and
functional values of each points z11,z12,z21,z22 are known, we estimate
functional value z at (x, y) by following bilinear interpolation method.(see
Figure A.1)
Bilinear interpolation method uses following bilinear approximation
formula.
z = Ax+By+Cxy+D
A.1.Bilinear formula is "linear" on Y=y1, so we can evaluate Z1 by linear
interpolation(x11,z11)and(x12,z12).
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z12-z11
Z1 = z11+ (x-x11)
x12-x11
A.2. Bilinear formula is "linear" on Y=y2, so we can evaluate Z2 by linear
interpolation(x21,z21)and(x22,z22).
z22-z21
Z2 = z21+ (x-x21)
x22-x21
A.3. Bilinear formula is "linear" on X=x, so we can evaluate z by linear
interpolation(y1 ,Z1 ) and (y2 ,Z2 ).
Z2 -Z1
z = Z1 + (y-y1 )
y2 -y1
Consequently, we can evaluate z at(x, y) by the following three-steps
formula.
[Trapezoidal points interpolation formula]
z12-z11
Z1 = z11+ (x-x11)
x12-x11
z22-z21
Z2 = z21+ (x-x21)
x22-x21
Z2 -Z1
z = Z1 + (y-y1 )
y2 -y1
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Annex B. (Informative)
Three points interpolation
Here, we explain linear interpolation by three triangular points.
y2 z3
Figure B.1
Z1 z Z2
y
y1
z1 z2
x1 X1 x x3 X2 x2
When three points (x1,y1),(x2,y1),(x3,y2) are given and functional values of
each points z1 ,z2 ,z3 are known, we estimate functional value z at (x, y) by
following linear interpolation method.(see Figure B.1)
B.1. Evaluate X1 by linear interpolation (y2 ,x3 ) and (y1 ,x1 ).
x1 -x3
X1 = x3 + (y-y2 )
y1 -y2
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B.2. Evaluate Z1 by
...




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