IEC 62014-4:2015

IEC 62014-4 ®
Edition 1.0 2015-03
™
IEEE Std 1685 -2009
INTERNATIONAL
STANDARD
IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within
Tool Flows
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IEC 62014-4 ®
Edition 1.0 2015-03
IEEE Std 1685™-2009
INTERNATIONAL
STANDARD
IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within

Tool Flows
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040 ISBN 978-2-8322-2265-2

IEC 62014-4
i IEEE Std 1685-2009
Contents
1. Overview. 1
1.1 Scope. 1
1.2 Purpose. 2
1.3 Design environment. 2
1.4 IP-XACT Enabled implementations. 6
1.5 Conventions used. 7
1.6 Use of color in this standard . 12
1.7 Contents of this standard. 12
2. Normative references. 13
3. Definitions, acronyms, and abbreviations. 15
3.1 Definitions . 15
3.2 Acronyms and abbreviations . 21
4. Interoperability use model . 23
4.1 Roles and responsibilities . 23
4.2 IP-XACT IP exchange flows . 24
5. Interface definition descriptions . 27
5.1 Definition descriptions. 27
5.2 Bus definition. 27
5.3 Abstraction definition . 30
5.4 Ports . 31
5.5 Wire ports . 32
5.6 Qualifiers . 34
5.7 Wire port group. 36
5.8 Wire port mode constraints. 38
5.9 Wire port mirrored-mode constraints . 39
5.10 Transactional ports. 41
5.11 Transactional port group. 43
5.12 Extending bus and abstraction definitions . 44
5.13 Clock and reset handling. 47
6. Component descriptions . 49
6.1 Component. 49
6.2 Interfaces. 52
6.3 Interface interconnections. 52
6.4 Complex interface interconnections . 54
6.5 Bus interfaces. 56
6.6 Component channels. 67
6.7 Address spaces. 69
6.8 Memory maps . 81
6.9 Remapping . 97
6.10 Registers. 102
6.11 Models . 120
6.12 Component generators . 151
6.13 File sets . 153
6.14 Choices. 165
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEC 62014-4
IEEE Std 1685-2009 ii
6.15 White box elements . 167
6.16 White box element reference . 168
6.17 CPUs . 170
7. Design descriptions. 171
7.1 Design . 171
7.2 Design component instances. 173
7.3 Design interconnections. 175
7.4 Active, monitored, and monitor interfaces . 176
7.5 Design ad hoc connections . 178
7.6 Design hierarchical connections .180
8. Abstractor descriptions . 183
8.1 Abstractor. 183
8.2 Abstractor interfaces . 185
8.3 Abstractor models . 187
8.4 Abstractor views . 189
8.5 Abstractor ports. 191
8.6 Abstractor wire ports . 193
8.7 Abstractor generators. 195
9. Generator chain descriptions . 199
9.1 generatorChain. 199
9.2 generatorChainSelector. 201
9.3 generatorChain component selector. 202
9.4 generatorChain generator. 203
10. Design configuration descriptions . 207
10.1 Design configuration. 207
10.2 designConfiguration. 207
10.3 generatorChainConfiguration . 209
10.4 interconnectionConfiguration . 211
11. Addressing and data visibility. 213
11.1 Calculating the bit address of a bit in a memory map . 213
11.2 Calculating the bus address at the slave bus interface . 214
11.3 Address modifications of an interconnection . 214
11.4 Address modifications of a channel. 215
11.5 Addressing in the master. 216
11.6 Visibility of bits . 216
11.7 Address translation in a bridge . 218
Annex A (informative) Bibliography. 219
Annex B (normative) Semantic consistency rules . 221
Annex C (normative) Common elements and concepts. 245
Annex D (normative) Types. 263
Annex E (normative) Dependency XPATH. 267
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
x Copyright © 2010 IEEE. All rights reserved.

IEC 62014-4
iii IEEE Std 1685-2009
Annex F (informative) External bus with an internal/digital interface . 271
Annex G (normative) Tight generator interface. 273
Annex H (informative) Bridges and channels. 351
Annex I (informative) IEEE List of Participants. .361
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEC 62014-4
IEEE Std 1685-2009 iv
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEC 62014-4
v IEEE Std 1685-2009
– 2 – IEC 62014-4
IEEE Std 1685-2009
IP-XACT, STANDARD STRUCTURE FOR
PACKAGING, INTEGRATING, AND REUSING
IP WITHIN TOOL FLOWS
FOREWORD
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IEC 62014-4
IEEE Std 1685-2009 vi
IEC 62014-4 – 3 –
IEEE Std 1685-2009
International Standard IEC 62014-4/ IEEE Std 1685-2009 has been processed through IEC
technical committee 91: Electronics assembly technology, under the IEC/IEEE Dual Logo
Agreement.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1685 (2009) 91/1207/FDIS 91/1226/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The IEC Technical Committee and IEEE Technical Committee have decided that the contents
of this publication will remain unchanged until the stability date indicated on the IEC web site
under "http://webstore.iec.ch" in the data related to the specific publication. At this date, the
publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEC 62014-4
vii IEEE Std 1685-2009
TM
IEEE Std 1685 -2009
IEEE Standard for IP-XACT,
Standard Structure for Packaging,
Integrating, and Reusing IP within
Tool Flows
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 9 December 2009
IEEE SA-Standards Board
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEC 62014-4
IEEE Std 1685-2009 viii
Grateful acknowledgment is made to The SPIRIT Consortium, Inc., for permission to use the
following source material:
IP-XACT 1.2 and IP-XACT 1.5
Abstract: Conformance checks for eXtensible Markup Language (XML) data designed to describe
electronic systems are formulated by this standard. The meta-data forms that are standardized
include: components, systems, bus interfaces and connections, abstractions of those buses, and
details of the components including address maps, register and field descriptions, and file set
descriptions for use in automating design, verification, documentation, and use flows for electronic ®
systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C )
and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable
across tool environments is provided. The specified combination of methodology-independent
meta-data and the tool-independent mechanism for accessing that data provides for portability of
design data, design methodologies, and environment implementations.
Keywords: abstraction definitions, address space specification, bus definitions, design
environment, EDA, electronic design automation, electronic system level, ESL, implementation
constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight
generator interface, tool and data interoperability, use models, XML design meta-data, XML
schema
AMBA is a registered trademark of ARM Limited.
Design Compiler and VCS are registered trademarks of Synopsys, Inc.
SystemC is a registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries.
Verilog is a registered trademark of Cadence Design Systems, Inc. in the United States and/or other jurisdictions.
W3C is a registered trademark of the World Wide Web Consortium.
XMLSpy is a registered trademark of Altova GmbH in the U.S., the European Union and/or other countries.
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.

IEC 62014-4
ix IEEE Std 1685-2009
I(((,ntroduction
This introduction is not part of IEEE Std 1685-2009, IEEE Standard for IP-XACT, Standard Structure for Packaging,
Integrating, and Reusing IP within Tool Flows.
The purpose of this standard is to provide the electronic design automation (EDA), semiconductor,
electronic design intellectual property (IP) provider, and system design communities with a well-defined
and unified specification for the meta-data that represents the components and designs within an electronic
system. The goal of this specification is to enable delivery of compatible IP descriptions from multiple IP
vendors; better enable importing and exporting complex IP bundles to, from, and between EDA tools for
system on chip (SoC) design environments (DEs); better express configurable IP by using IP meta-data; and
better enable provision of EDA vendor-neutral IP creation and configuration scripts (generators). The data
and data access specification is designed to coexist and enhance the hardware description languages (HDLs)
presently used by designers while providing capabilities lacking in those languages.
The SPIRIT Consortium is a consortium of electronic system, IP provider, semiconductor, and EDA
companies. IP-XACT enables a productivity boost in design, transfer, validation, documentation, and use of
electronic IP and covers components, designs, interfaces, and details thereof. The data specified by IP-
XACT is extensible in locations specified in the schema.
IP-XACT enables the use of a unified structure for the meta specification of a design, components,
interfaces, documentation, and interconnection of components. This structure can be used as the basis of
both manual and automatic methodologies. IP-XACT specifies the tight generator interface (TGI) for access
to the data in a vendor-independent manner.
This standardization project provides electronic design engineers with a well-defined standard that meets
their requirements in structured design and validation, and enables a step function increase in their
productivity. This standardization project will also provide the EDA industry with a standard to which they
can adhere and that they can support in order to deliver their solutions in this area.
The SPIRIT Consortium has prepared a set of bus and abstraction definitions for several common buses. It is
expected, over time, that those standards groups and manufacturers who define buses will include IP-XACT
eXtensible Markup Language (XML) bus and abstraction definitions in their set of deliverables. Until that
time, and to cover existing useful buses, a set of bus and abstraction definitions for common buses has been
created.
A set of reference bus and abstraction definitions allows many vendors who define IP using these buses to
easily interconnect IP together. The SPIRIT Consortium posts these for use by its members, with no
warranty of suitability, but in the hope that these will be useful. The SPIRIT Consortium will, from time-to-
time, update these files and if a Standards body wishes to take over the work of definition, will transfer that
work to that body.
These reference bus and abstraction definition templates (with comments and examples) are available from
a
the public area of The SPIRIT Consortium Web site.
a
Available at http://www.spiritconsortium.org.
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
iv Copyright © 2010 IEEE. All rights reserved.

IEC 62014-4
IEEE Std 1685-2009 x
Notice to users
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Patents
Attention is called to the possibility that implementation of this standard may require use of subject matter
covered by patent rights. By publication of this standard, no position is taken with respect to the existence or
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Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEC 62014-4
1 IEEE Std 1685-2009
IP-XACT,
Standard Structure for Packaging,
Integrating, and Reusing IP within
Tool Flows
IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or
environmental protection in all circumstances. Implementers of the standard are responsible for
determining appropriate safety, security, environmental, and health practices or regulatory requirements.
This IEEE document is made available for use subject to important notices and legal disclaimers. These
notices and disclaimers appear in all publications containing this document and may be found under the
heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.” They
can also be obtained on request from IEEE or viewed at http://standards.ieee.org/IPR/disclaimers.html.
1. Overview
This clause explains the scope and purpose of this standard; gives an overview of the basic concepts, major
semantic components, and conventions used in this standard; and summarizes its contents.
1.1 Scope
This standard describes an eXtensible Markup Language (XML) schema for meta-data documenting
intellectual property (IP) used in the development, implementation, and verification of electronic systems
and an application programming interface (API) to provide tool access to the meta-data. This schema
provides a standard method to document IP that is compatible with automated integration techniques.The
API provides a standard method for linking tools into a system development framework, enabling a more
flexible, optimized development environment. Tools compliant with this standard will be able to interpret,
configure, integrate, and manipulate IP blocks that comply with the IP meta-data description. The standard
is based on version 1.4 IP-XACT of The SPIRIT Consortium. The standard is independent of any specific
design processes. It does not cover those behavioral characteristics of the IP that are not relevant to
integration.
Information on references can be found in Clause 2.
3XEOLVKHGE\,(&XQGHUOLFHQVHIURP,(((‹,((($OOULJKWVUHVHUYHG

Generated
Output
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Tools
Configured
IP
IEEE
IEC 62014-4
Std 1685-2009 IEEE STANDARD FOR IP-XACT, STANDARD STRUCTURE FOR
IEEE Std 1685-2009 2
1.2 Purpose
This standard enables the creation and exchange of IP in a highly automated design environment.
1.3 Design environment
The IP-XACT specification is a mechanism to express and exchange information about design IP and its
required configuration. While the IP-XACT description formats are the core of this standard, describing the
IP-XACT specification in the context of its basic use model, the design environment (DE), more readily
depicts the extent and limitations of the semantic intent of the data. The DE coordinates a set of tools and IP,
or expressions of that IP (e.g., models), through the creation and maintenance of meta-data descriptions of
the system on chip (SoC) such that its system design and implementation flows are efficiently enabled and
reuse centric.
The use of the IP-XACT specified formats and interfaces are shown, in bold, in Figure 1 and described in
the following subclauses.
IP-XACT Compliant IP-XACT Compliant IP-XACT Compliant
Object Descriptions Generators
Design Environment
Component
address
addres
XML
insinteterrffaaccee
pprrototococool
registers
lbuswidth
Bus
Component
Generator
IP Definitions
Chains
CoCoComponmmponponeneet
Design
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PPP
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ntnt
XML
IP-XACT
TGI
system_bus
Abstractor
memememmm
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UARTUARTUART GPGPGPIIIOOO
IP-XACT IP Generator
Abstractor
Generator
Import
IP
Export
Design
Configuration
Bus Abstraction
Bus Bus
Definitions Definitions
Definitions Definitions
IP-XACT Compliant
Object Descriptions
Figure 1—IP-XACT design environment
1.3.1 IP-XACT design environment
A DE enables the designer to work with IP-XACT design IP through a coordinated front-end and IP design
database. These tools create and manage the top-level meta-description of system design and may provide
two basic types of services: design capture, which is the expression of design configuration by the IP
2 ®
IP-XACT uses the World Wide Web Consortium (W3C ) standard for the XML version 1.0 data (http://www.w3.org/TR/2000/REC-
xml-20001006). The valid format of that XML data is described in a schema by using the Schema Description Language described
therein. W3C is a registered trademark of the World Wide Web Consortium.
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2 Copyright © 2010 IEEE. All rights reserved.

IEEE
IEC 62014-4
PACKAGING, INTEGRATING, AND REUSING IP WITHIN TOOL FLOWS Std 1685-2009
3 IEEE Std 1685-2009
provider and design intent by the IP user; and design build, which is the creation of a design (or design
model) to those intentions.
As part of design capture, a system design tool shall recognize the structure and configuration options of
imported IP. In the case of structure, this implies both the structure of the design [e.g., how specific pin-outs
refer to lines in the hardware description language (HDL) code] as well as the structure of the IP package
(e.g., where design descriptions and related generators are provided in the packaged IP data-structure). In the
case of configuration, this is the set of options for handling the imported IP (e.g., setting the base address
and offset, bus width) that may be expressed as configurable parameters in the IP-XACT meta-data.
As part of design build, generators may be provided internally by a system design tool to achieve the
required IP integration or configuration, or provided externally (e.g., by an IP provider) and launched by the
system design tool as appropriate.
The system design tool set defines a DE where the support for conceptual context and management of IP-
XACT meta-data resides. However, the IP-XACT specifications make no requirements upon system design
tool architecture or a tool’s internal data structures. To be considered IP-XACT v1.5 enabled, a system
design tool shall support the import/export of IP expressed with valid IP-XACT v1.5 meta-data for both
component IP and designs, and it needs to support the tight generator interface (TGI) for interfacing with
external generators (to the DE).
1.3.2 IP-XACT object descriptions
The IP-XACT schema is the core of the IP-XACT specification. There are seven top-level schema
definitions. Each schema definition can be used to create object descriptions of the corresponding type.
—A bus definition description defines the type attributes of an bus.
—An abstraction definition description defines the representation attributes of a bus.
—A component description defines an IP or interconnect structure.
—A design description defines the configuration of and interconnection between components.
—An abstractor description defines an adaptor between interfaces of two different abstractions.
—A generator chain description defines the grouping and ordering of generators.
—A design configuration description defines additional configuration information for a generator
chain or design description.
1.3.3 Object interactions
An object description contains a unique identifier in the header. The identifier in IP-XACT terms is called a
VLNV after the four elements that define its value: vendor, library, name, and version. See C.6 for further
details on a VLNV. This VLNV is used to create a reference from one description to another. The links
between these objects are illustrated in Figure 2. The arrows (A � B) illustrate a reference of one object to
another (e.g., reference of object B from object A).
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEEE
IEC 62014-4
Std 1685-2009 IEEE STANDARD FOR IP-XACT, STANDARD STRUCTURE FOR
IEEE Std 1685-2009 4
Component
Component
Design Design Generator
Generator
Design Design
Configuration Chain
Chain
Configuration
Component Abstractor
Component Abstractor
Component Abstractor
Abstraction Bus
Abstraction Bus
Definition Definition
Definition Definition
Generator
Generator
Figure 2—IP-XACT object interactions
1.3.4 IP-XACT generators
Generators are executable objects (e.g., scripts or binary programs) that may be integrated within a DE
(referred to as internal) or provided separately as an executable (referred to as external). Generators may be
provided as part of an IP package (e.g., for configurable IP, such as a bus-matrix generator) or as a way of
wrapping point tools for interaction with a DE (e.g., an external design netlister, external design checker).
An internal generator may perform a wide variety of tasks and may access IP-XACT compliant meta-data by
any method a DE supports. IP-XACT does not describe these protocols.
An external generator (often referred to as a TGI generator) is an executable program or script invoked
from within a DE to query or configure design descriptions and their related component and abstractor
descriptions. External generators can use the TGI to access their IP-XACT meta-data descriptions (as
currently loaded into the DE) and perform the various operations associated with those descriptions. In
addition, external generators shall only operate upon IP-XACT compliant meta-data through the defined
TGI, see 1.3.6.
Generators can be referenced from a component, abstractor, or generator chain description. Generators can
also be grouped and ordered in generator chain descriptions and those chain descriptions contained inside
other chain descriptions. This sequencing of generators is critical for providing script-based support for SoC
flow creation.
1.3.5 IP-XACT design environment interfaces
There are two obvious interfaces expressed in Figure 1: from the DE to the external IP libraries and from the
DE to the generators. In the former case, the IP-XACT specifications are neutral regarding the design tool
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IEEE
IEC 62014-4
PACKAGING, INTEGRATING, AND REUSING IP WITHIN TOOL FLOWS Std 1685-2009
5 IEEE Std 1685-2009
interfaces to IP repositories. Being able to read and write IP with IP-XACT meta-data is required; however,
the formal interaction between an external IP repository and a DE is not specified.
1.3.6 Tight generator interface
The tight generator interface (TGI) is the method a generator uses to efficiently access a design or
component description in a DE-independent and generator-language-independent manner. Therefore, a
generator running on two different DEs produces the same results. The DE and the generator communicate
with each other by sending messages utilizing the Simple Object Access Protocol (SOAP) standard version
3 4
1.2 specified in the Web Services Description Language (WSDL) version 1.1. SOAP provides a simple
means for sending XML-format messages using the Hypertext Transfer Protocol (HTTP) or other transport
protocols. IP-XACT supports using an HTTP protocol or a file protocol.
The SOAP messages passed between the generator and the DE allow the generator to get all information
about the design interconnections (which contain components and abstractors), provide set information for
any configurable elements in a component or abstractor, and make simple modifications of the design
description. For additional details on the DE generator invo
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