TC 91 - Electronics assembly technology

IEC 61189-3-302:2025 describes a method for the detection of plating defects in unpopulated circuit boards using computed tomography (CT).
This document is applicable to non-destructive testing of metallized holes.

IEC 61249-2-53:2025 specifies requirements for properties of PTFE unfilled reinforced laminated sheet of a thickness 0,05 mm up to 10,0 mm of defined flammability (vertical burning test), copper-clad. This part of IEC 61249 is applicable to the design, manufacture, use of PTFE unfilled reinforced laminated sheet of defined flammability (vertical burning test), copper-clad. Its flame resistance is defined in terms of the flammability requirements of 8.4.

IEC 61249-2-52:2025 gives requirements for properties of the thermosetting hydrocarbon resin system, woven E-glass reinforced laminate sheets of defined flammability (vertical burning test), copper-clad in thicknesses of 0,05 mm up to 3,20 mm.

IEC 61967-7:2025 defines SystemC® with Transaction Level Modeling (TLM) as an ISO standard C++ class library for system and hardware design. SystemC®1 as an ANSI standard C++ class library for system and hardware design.
The general purpose of this standard is to provide a C++-based standard for designers and architects who need to address complex systems that are a hybrid between hardware and software. The specific purpose of this standard is to provide a precise and complete definition of the SystemC class library including a TLM library so that a SystemC implementation can be developed with reference to this standard alone. This standard is not intended to serve as a user’s guide or to provide an introduction to SystemC, but it does contain useful information for end users.
The changes with respect to the previous edition are provided in Annex D.
This standard is published as a double logo IEC-IEEE standard.

IEC 62014-4:2025 describes an eXtensible Markup Language (XML) schema for meta-data documenting intellectual property (IP) used in the development, implementation, and verification of electronic systems. This schema provides both a standard method to document IP that is compatible with automated integration techniques and a standard method (generators) for linking tools into a system development framework, enabling a more flexible, optimized development environment. Tools compliant with this standard will be able to interpret, configure, integrate, and manipulate IP blocks that comply with the IP meta-data description. The standard is independent of any specific design processes. It does not cover behavioral characteristics of the IP that are not relevant to integration. This standard enables the creation and exchange of IP in a highly automated design environment.
This standard is published as a double logo IEC-IEEE standard.

IEC 60068-2-83:2025 is available as IEC 60068-2-83:2025 RLV which contains the International Standard and its Redline version, showing all changes of the technical content compared to the previous edition.
IEC 60068-2-83:2025 provides methods for comparative investigation of the wettability of the metallic terminations or metallized terminations of SMDs with solder paste. Data obtained by these methods are not intended to be used as absolute quantitative data for pass/fail purposes.
NOTE Different solderability test methods for SMD are described in IEC 60068‑2‑58 and IEC 60068‑2‑69. IEC 60068‑2‑58 specifies visual evaluation using solder bath and reflow method, IEC 60068‑2‑69 specifies wetting balance evaluation using solder bath and solder globule method.
This edition includes the following significant technical change with respect to the previous edition:
a) revise Clause 5 to align with that in IEC 60068‑2‑20:2021.

IEC 62878-2-603:2025 specifies the electrical test method to detect electrical connectivity defects of the stacked electronic module caused by the stacking assembly process to stack some stackable electronic modules. This method is realized to make use of bidirectional serial communication bus interface applied to the stackable electronic modules which are assured as "known good module" (KGM).

IEC 60194-2:2025 covers terms and definitions related to circuit board and electronic assembly technologies as well as other electronic technologies.
The terms have been classified according to the decimal classification code (DCC) and this DCC number appears just below the defined term. The DCC numbering is fully explained in Annex A.
A list of terms in alphabetical order with code number is provided in Annex B.
This edition includes the following significant technical changes with respect to the previous edition:
a) exclusion of 116 terms transferred to IEV;
b) inclusion of 9 new terms related to printed electronics and packaging technology;
c) revision of definitions of 23 terms reflecting current technology;
d) three "printed wiring" terms were removed;
e) reintroduction of identification codes for terms.

IEC 61188-6-3:2024 specifies the requirements for lands and land pattern on circuit boards for the mounting of components with leads by soldering based on the solder joint requirements of IEC 61191-1 and IEC 61191-3.
This part of IEC 61188 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through hole mounted components. These requirements are based on the solder joint requirements of IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.
This first edition partially cancels and replaces the IEC 61188-5 series of International Standards.
The significant technical changes with respect to the previous edition are listed in the Introduction and further detailed information and calculations can be found in Annex A.

IEC 61189-2-809:2024 defines the method to be followed for the determination of the X/Y coefficient of thermal expansion of electrical insulating materials by the use of a thermomechanical analyser (TMA).
This method is applicable to materials that are solid of the entire range of temperature used and retain sufficient hardness and rigidity over the temperature range so that irreversible indentation of the specimen by the sensing probe does not occur.

IEC TR 60068-3-82:2024, which is a Technical Report, provides technical background information on the whisker test methods from IEC 60068-2-82 and guidance on test selection.

IEC 62529:2024 provides the means to define and describe signals used in testing. It provides a set of common basic signal definitions, built upon formal mathematical specifications, so that signals can be combined to form complex signals usable across all test platforms. The standard provides support for structural textual languages and programming language interfaces for interoperability. This second edition cancels and replaces the first edition, published in 2007, and constitutes a technical revision.

IEC 61189-2-808:2024 describes the thermal transient method to characterize the thermal resistance of an assembly consisting of a heat source (e.g. power device), an attachment material (e.g. solder) and a dielectric layer with electrode. This method is suitable to determine the thermal resistance of materials and assembly methods as well as to optimize the thermal flux to a heat sink.
NOTE: This method is not intended to measure and specify the value of the thermal resistance of a dielectric material. For that purpose, other standards exist. Examples are given in Annex A.

IEC 61189-2-805:2024 defines the method to be followed for the determination of the X/Y coefficient of thermal expansion of thin electrical insulating materials via the use of a thermomechanical analyser (TMA). This method is applicable to materials that are solid for the entire range of temperature used, and that retain sufficient rigidity over the temperature range so that so that irreversible indentation of the specimen by the sensing probe does not occur.

IEC 61189-2-720:2024 provides a method to evaluate specific characteristics of circuit boards by measuring the capacitance between conductor traces and a ground plane and can be used for qualitative comparison of a test specimen to a reference board. This method is not intended for quantitative measurements and for assessment of conformity to a specification.

IEC 61523-4:2023 defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries). This is an IEC/IEEE dual logo standard.

IEC TR 60068-3-15:2024 describes vacuum-assisted soldering considering the thermal profiling, soldering methods, suitability of the components and vacuum features of soldering systems. It is based on practical experiences from manufacturers, component, material, and soldering systems suppliers. It supports manufacturers by providing information about the functionality of vacuum and effect of vacuum on components performance.

IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.

IEC TR 61760-5-1:2024 describes examples of methods using electrical strain gauges for determination of critical mechanical stresses in assembly processes. These stresses can damage chip type ceramic components, causing so called “bending cracks”. Area-array components are excluded from the scope of this document.

IEC 63251:2023 defines the thermal endurance test methods for reliability assessment of flexible opto-electric circuit boards. The purpose of this document is to accommodate the uniform thermal characteristics required by the flexible opto-electric circuit in high temperature environments such as automobiles. In particular, this document specifies a test method to inspect the occurrence of colour exchange, deformation and delamination of flexible opto-electric circuit boards under thermal stress.

IEC 63215-2:2023 applies to the die attach materials and joining system applied to discrete type power electronic devices.
This document specifies the temperature cycling test method which takes into account the actual usage conditions of discrete type power electronic devices to evaluate reliability of the die attach joint materials and joining system, and establishes a classification level for joining reliability (reliability performance index).
The test method specified in this document is not intended to evaluate power semiconductor devices themselves.
The test method specified in this document is not regarded as the one for use to guarantee the reliability of the power semiconductor device packages.
NOTE The test result obtained using this document will not be used as absolute quantitative data, but for intercomparison with the other die attach materials results using the same setup.

IEC 63501-2416:2023 describes a parameterized and abstracted power model enabling system, software, and hardware intellectual property (IP)-centric power analysis and optimization. It defines concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature (PVT) independence; power and thermal management interface; and workload and architecture parameterization. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models to help guide development and usage of other related power, workload, and functional modeling standards. This standard is published as a double logo IEC-IEEE standard.

IEC 63504-2804:2023 defines an architecture description standard from the software design perspective - this provides a common interface that abstracts the hardware properties that are critical to enable multicore tools. The standard includes performance estimation accuracy for complex processors like Very Long Instruction Word (VLIW) core and complex contention scenarios, description of caches to include uncached memory regions and caches for subsets of memories, properties for coarse power consumption estimation, and reusability by separating eXtensible Markup Language (XML) files for processor description and other memory/communication-related information. This is an IEC/IEEE dual logo standard.

IEC 61691-1-1:2023 defines the syntax and semantics of the VHSIC Hardware Description Language (VHDL). The acronym VHSIC (Very High Speed Integrated Circuits) in the language’s name comes from the U.S. government program that funded early work on the standard. This is an IEC/IEEE dual logo standard.

IEC 61523-4:2023 defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries). This is an IEC/IEEE dual logo standard.
The contents of the corrigendum 1 (2024-02) have been included in this copy.

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.

IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.

IEC 63055:2023 defines a common interoperable format that will be used for the design of a) large-scale integration (LSI), b) packages for such LSI, and c) printed circuit boards on which the packaged LSIs are interconnected. Collectively, such designs are referred to as LSI-Package-Board (LPB) designs. The format provides a common way to specify information/data about the project management, netlists, components, design rules, and geometries used in LPB designs. This is an IEC/IEEE dual logo standard.

IEC 61189-2-804:2023 specifies a test method to determine the time to delamination of base materials and printed boards using a thermomechanical analyser (TMA). Temperatures used for this evaluation are typically 260 °C, 288 °C and 300 °C, but are not limited to these values.

IEC 61189-2-801:2023 defines a test method to be followed for thermal performance via carbon ink heating. The method employs a screened-on pattern of carbon ink used to determine the thermal performance of a dielectric layer on a metal base plate.

IEC 61189-2-803:2023 specifies a test method to determine the Z-axis expansion of base materials and printed boards using a thermomechanical analyser (TMA).

IEC 61249-6-3:2023 covers finished fabrics woven from ‘‘E’’ glass electrical grade glass fibre yarns that are intended as a reinforcing material in laminated plastics for electrical and electronic use. All fabrics covered by this specification are plain weave.
This specification determines the nomenclature, definitions, general and chemical requirements for the glass, and physical requirements for finished woven glass fibre fabrics.
Annex A of this document provides a style designator for each finished fabric glass style, with specifications on yarn, fabric count, thickness and weight in both SI and US system.
This standard cancels and replaces IEC/PAS 61249-6-3 published in 2011. This edition constitutes a technical revision.

IEC TR 61191-9:2023, which is a Technical Report, applies to electronic and electromechanical automotive circuit board assemblies and describes current best practices for dealing with electrochemical reactions like migration or corrosion and ionic contamination on the surface of a circuit board as one failure mode under humidity load. This document deals with the evaluation of materials and manufacturing processes for the manufacturing of electronic assemblies with focus on their reliability under humidity loads. The electrical operation of a device in a humid environment can trigger electrochemical reactions that can lead to short circuits and malfunctions on the assembly. In this context, a large number of terms and methods are mentioned, such as CAF (conductive anodic filament), anodic migration phenomena, dendrite growth, cathodic migration, ROSE (resistivity of solvent extract), ionic contamination, SIR (surface insulation resistance), impedance spectroscopy, etc., which are used and interpreted differently. The aim of the document is to achieve a uniform use of language and to list the possibilities and limitations of common measurement methods. The focus of the document is on the error pattern of electrochemical migration on the surface of assemblies with cathodic formation of dendrites.
Evaluation of different test methods of control units under high humidity load are not part of this document.

IEC 61249-2-51:2023 specifies the construction, materials, property requirements, quality assurance, packaging, marking, storage of base materials for integrated circuit card carrier tape, unclad (hereinafter referred to as IC carrier tape base materials).
This document is applicable to IC carrier tape base materials, which is a glue-coated material, one side is woven E-glass reinforced epoxy underlayer, and the other side is coated with adhesive and protected by release film.

IEC 61636-2:2023 (E) provides the definition of an exchange format, utilizing XML, for exchanging maintenance action information (MAI) associated with the removal, repair, and replacement of system components to maintain/support an operational system. This standard is published as a double log IEC-IEEE standard.

IEC 62496-2-5:2022 defines a test method for folding flexibility inspection of flexible opto-electric circuits with a flexibility tester endurance tester and presents a guideline for a step stress test method for finding the predetermined minimum mechanical folding radii below which the flexible opto-electric circuits can be damaged by intended folding distortion. Here, test samples are used instead of products for the flexibility test of their flexible opto-electric circuits, and the test samples have the same material, layer structure, processing technology and equipment as the products.

IEC TR 60068-3-12:2022(E) which is a Technical Report, describes the creation of temperature-time profiles (in specific envelope profiles) for reflow soldering of electronic assemblies, considering tolerances resulting from the accuracy of the measuring equipment, preparation method and specifications of the manufacturers of components, circuit boards, solder paste, etc.).
This edition includes the following significant technical changes with respect to the previous edition: a) Extended purpose Guidance is added on how to create a reflow profile considering the tolerances resulting from the accuracy of the measuring equipment, preparation method and specifications of the component manufacturers (components, PCB, solder paste, etc.). b) Distinction from existing standards The envelope profile given in this document does not represent a temperature-time profile for the qualification of materials but defines the reflow process limits for the soldering of electronic assemblies.
The schematic temperature-time-limit curves of the envelope profile are derived from generally valid findings (literature data). Additionally, tolerance considerations are given for all envelope points of the envelope profile.
In contrast to IEC TR 60068-3-12:2014, the creation of the envelope profile is not primarily linked to a concrete example. c) Subclause 8.2 presents an approach for establishing a possible temperature profile for a lead-free reflow soldering process using SnAgCu solder paste that is taken from IEC TR 60068-3-12:2014. d) Synergies with existing standards Limit values and tolerances from standards and guidelines for the qualification of materials are included in this document and are listed as examples in the references.

IEC PAS 61191-10:2022(E) provides guidelines which deal with the requirements for the protective coating,
its properties, as well as the application of liquid coating materials for electronic assemblies. These guidelines help control in practice the application of protective coatings from the layout to the functional test of the assembly after coating.

IEC TR 61760-3-1:2022(E) supplements IEC 61760-3 to describe examples of solder paste supply methods, the relationship between the terminal position tolerance and the through hole diameter, and provides guidelines for the design of printed circuit boards with solder paste surface printing method, including specific examples.

IEC TR 62878-2-9:2022(E) comprises the long-term discussion among Jisso International Council (JIC) members during 1999 and 2005, when the interim agreement among all JIC members about the “concept of Jisso” as well as the “Jisso product level” for the common understanding on IEC TC 91 (electronic assembly technology) activities was reached. Further discussion on “Jisso Product Level” could be needed among the current JIC members to finalize it in the near future based on this technical report.

IEC 61189-2-501:2022 establishes a method suitable for testing the softness of FCCL (Flexible Copper Clad Laminate) products and related materials. This method determines the resilience under specified conditions. The test is performed on the sample as manufactured and without conditioning. The test does not apply to the resilience force lower than 10 mN.

IEC 61189-2-807:2021 specifies a test method to determine the decomposition temperature (Td) of base laminate materials using thermogravimetric analysis (TGA).

IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

IEC 61691-8:2021(E) defines the Analog/Mixed-Signal extensions for SystemC®, as an ANSI standard C++ class
library based on SystemC for system and hardware design including analog/mixed-signal elements. The general purpose of the SystemC AMS extensions is to provide a C++ standard for designers and architects, who need to address complex heterogeneous systems that are a hybrid between hardware and software. This standard is built on the IEEE Std 1666™-2011 (SystemC Language Reference Manual) and extends it to create analog/mixed-signal, multi-disciplinary models to simulate continuous-time, discrete-time, and discrete-event behavior simultaneously.
This standard is published as a double logo IEC-IEEE standard.

IEC 61760-2:2021 specifies the transportation and storage conditions for surface mounting devices (SMDs) that are fulfilled in order to enable trouble-free processing of surface mounting devices, both active and passive. (Conditions for printed boards are not taken into consideration.)
The object of this document is to ensure that users of SMDs receive and store products that can be further processed (e.g. positioned, soldered) without prejudice to quality and reliability. Improper transportation and storage of SMDs can cause deterioration and result in assembly problems such as poor solderability, delamination and "popcorning". Cross-references for references from this edition 3 to the previous edition 2 of this document are listed in Annex X of this document.

IEC 60068-2-21:2021 is applicable to all electrical and electronic components whose terminations or integral mounting devices are liable to be submitted to stresses during normal assembly or handling operations and is also applicable to surface mount devices (SMDs).
This seventh edition cancels and replaces the sixth edition, published in 2006, and IEC 60068‑2‑77:1999. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition:
integration of parts of IEC 60068-2-77 (see Annex X); IEC 60068-2-77 is withdrawn with the publication of this document;
Annex X is added to show the correlation of the clauses and subclauses in this edition of IEC 60068-2-21 with the clauses in IEC 60068-2-21:2006 and IEC 60068-2-77:1999.

IEC TR 62878-2-8:2021(E) describes a warpage control of active device embedded substrate along with parameters for determining warpage, which are useful during package assembly. Warpage results are explained using warpage driving force, resistance and neutral axis, for typical die embedded substrate, where the discrete active dies are placed in the core of substrate and interconnected to the substrate by direct Cu bonding. The same principles are applicable in other device embedded substrates. Even though the detailed structure of other device embedded substrates might be different, the origin and determination of the parameters of warpage are the same and thus the purpose of this report is to help engineers improve the warpage behaviours of their products by applying this principle.

IEC 62878-2-602:2021 specifies the requirements and evaluation methods of electrical connectivity. It is applicable to stacked electronic modules.

IEC 61636-1:2021 (E) provides the definition of an exchange format, utilizing XML, for exchanging data resulting from executing tests of a unit under test (UUT) via a test program in an automatic test environment. This standard is published as a double logo IEC-IEEE standard.