IEC 61189-2-804:2023 specifies a test method to determine the time to delamination of base materials and printed boards using a thermomechanical analyser (TMA). Temperatures used for this evaluation are typically 260 °C, 288 °C and 300 °C, but are not limited to these values.

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IEC 61249-2-51:2023 specifies the construction, materials, property requirements, quality assurance, packaging, marking, storage of base materials for integrated circuit card carrier tape, unclad (hereinafter referred to as IC carrier tape base materials).
This document is applicable to IC carrier tape base materials, which is a glue-coated material, one side is woven E-glass reinforced epoxy underlayer, and the other side is coated with adhesive and protected by release film.

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IEC 62899-202-10:2023 defines terminology and measurement methods for the resistance change of conductive ink layer(s) as a function of thermoplastic elongation. The method measures resistance changes in-situ or post-elongation.
This document is applicable to thermoformable substrates with conductive ink layers. The thermoformable substrates can have printed graphic ink as well and cover insulation layers.

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IEC 62899-202-9:2023 describes basic patterns to evaluate the electrical reliability of a conductive layer under mechanical deformation. Using the standard pattern described in this document, the comparison of the electrical reliability of a conductive layer under mechanical deformation is possible when the sample dimension is identical.

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IEC 61189-2-801:2023 defines a test method to be followed for thermal performance via carbon ink heating. The method employs a screened-on pattern of carbon ink used to determine the thermal performance of a dielectric layer on a metal base plate.

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IEC 61189-2-803:2023 specifies a test method to determine the Z-axis expansion of base materials and printed boards using a thermomechanical analyser (TMA).

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IEC 61249-2-51:2023 specifies the construction, materials, property requirements, quality assurance, packaging, marking, storage of base materials for integrated circuit card carrier tape, unclad (hereinafter referred to as IC carrier tape base materials). This document is applicable to IC carrier tape base materials, which is a glue-coated material, one side is woven E-glass reinforced epoxy underlayer, and the other side is coated with adhesive and protected by release film.

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IEC 61249-6-3:2023 covers finished fabrics woven from ‘‘E’’ glass electrical grade glass fibre yarns that are intended as a reinforcing material in laminated plastics for electrical and electronic use. All fabrics covered by this specification are plain weave.
This specification determines the nomenclature, definitions, general and chemical requirements for the glass, and physical requirements for finished woven glass fibre fabrics.
Annex A of this document provides a style designator for each finished fabric glass style, with specifications on yarn, fabric count, thickness and weight in both SI and US system.
This standard cancels and replaces IEC/PAS 61249-6-3 published in 2011. This edition constitutes a technical revision.

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IEC TR 61191-9:2023, which is a Technical Report, applies to electronic and electromechanical automotive circuit board assemblies and describes current best practices for dealing with electrochemical reactions like migration or corrosion and ionic contamination on the surface of a circuit board as one failure mode under humidity load. This document deals with the evaluation of materials and manufacturing processes for the manufacturing of electronic assemblies with focus on their reliability under humidity loads. The electrical operation of a device in a humid environment can trigger electrochemical reactions that can lead to short circuits and malfunctions on the assembly. In this context, a large number of terms and methods are mentioned, such as CAF (conductive anodic filament), anodic migration phenomena, dendrite growth, cathodic migration, ROSE (resistivity of solvent extract), ionic contamination, SIR (surface insulation resistance), impedance spectroscopy, etc., which are used and interpreted differently. The aim of the document is to achieve a uniform use of language and to list the possibilities and limitations of common measurement methods. The focus of the document is on the error pattern of electrochemical migration on the surface of assemblies with cathodic formation of dendrites.
Evaluation of different test methods of control units under high humidity load are not part of this document.

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IEC 61249-2-51:2023 specifies the construction, materials, property requirements, quality assurance, packaging, marking, storage of base materials for integrated circuit card carrier tape, unclad (hereinafter referred to as IC carrier tape base materials).
This document is applicable to IC carrier tape base materials, which is a glue-coated material, one side is woven E-glass reinforced epoxy underlayer, and the other side is coated with adhesive and protected by release film.

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IEC 62899-202:2023 is available as IEC 62899-202:2023 RLV which contains the International Standard and its Redline version, showing all changes of the technical content compared to the previous edition.
IEC 62899-202:2023 defines the terms and specifies the standard test methods for characterization and evaluation of conductive inks. This document also provides measurement methods for evaluating the properties of conductive layers made both from an additive process using conductive inks and from a subtractive process used in printed electronics. This edition includes the following significant technical changes with respect to the previous edition:
a) definitions of conductive material, conductive ink and conductive layer have been revised;
b) a summary of test methods is added;
c) mechanical tests for conductive layer are added.

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This part of IEC 62496-2 defines a test method for folding flexibility inspection of flexible opto-electric circuits with a MIT folding endurance tester and presents a guideline for a step stress test method for finding the predetermined minimum mechanical folding radii below which the flexible opto-electric circuits can be damaged by intended folding distortion. Here, test samples are used instead of products for the flexibility test of their flexible opto-electric circuits, and the test samples have the same layer structure as the products.

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IEC 62878-1:2019(E) specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3. This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components. The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

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IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material. This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers. IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

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This part of IEC 61189 establishes a method suitable for testing the softness of FCCL (Flexible
Copper Clad Laminate) products and related materials. This method determines the resilience
under specified conditions. The test is performed on the sample as manufactured and without
conditioning. The test does not apply to the resilience force lower than 10 mN.

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IEC PAS 61191-10:2022(E) provides guidelines which deal with the requirements for the protective coating,
its properties, as well as the application of liquid coating materials for electronic assemblies. These guidelines help control in practice the application of protective coatings from the layout to the functional test of the assembly after coating.

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IEC 61188-6-4:2019 specifies generic requirements for dimensional drawings of SMD from the viewpoint of land pattern design. The purpose of this document is to prevent land pattern design issues caused by lack of information and/or misuse of the information from SMD outline drawing as well as to improve the utilization of IEC 61188 series. This document is applicable to the SMD of semiconductor devices and electrical components.

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IEC TR 62878-2-9:2022(E) comprises the long-term discussion among Jisso International Council (JIC) members during 1999 and 2005, when the interim agreement among all JIC members about the “concept of Jisso” as well as the “Jisso product level” for the common understanding on IEC TC 91 (electronic assembly technology) activities was reached. Further discussion on “Jisso Product Level” could be needed among the current JIC members to finalize it in the near future based on this technical report.

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This part of IEC 61189 establishes a method suitable for testing the softness of FCCL (Flexible Copper Clad Laminate) products and related materials. This method determines the resilience under specified conditions. The test is performed on the sample as manufactured and without conditioning. The test does not apply to the resilience force lower than 10 mN.

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IEC 61189-2-501:2022 establishes a method suitable for testing the softness of FCCL (Flexible Copper Clad Laminate) products and related materials. This method determines the resilience under specified conditions. The test is performed on the sample as manufactured and without conditioning. The test does not apply to the resilience force lower than 10 mN.

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This part of IEC 61189 specifies a test method to determine the decomposition temperature (Td)
of base laminate materials using thermogravimetric analysis (TGA).

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IEC 62899-202-4:2021(E) defines the terminology and measurement methods for the properties of stretchable printed layers, such as conductive ink, for forming stretchable conductors by printing, stretchable conductive films obtained from conductive ink, and stretchable printed wiring consisted by conductive ink with insulator.
Stretchable printed layers (conductive and insulating) handled by this document apply to the stretchable electric wiring printed on stretchable substrates, for example fabric integrated wearable devices, skin patchable devices, and so on.

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IEC 61189-2-807:2021 specifies a test method to determine the decomposition temperature (Td) of base laminate materials using thermogravimetric analysis (TGA).

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IEC 62899-201-2:2021(E) defines measurement methods for the properties of stretchable substrates, in order to use evaluating stretchable functional layers (conductive, semiconducting, and insulating) formed by printing technologies. If the same types of materials as the substrates are used for the cover lay film, they are also subjected to the measurement defined in this document.
Stretchable substrates handled by this document apply to substrates subjected to repeated bending with wiring elements demanding a high level of performance, such as fabric integrated wearable devices or skin patchable devices.
This document does not define the required characteristics of the stretchable substrate. It provides test methods to characterize (pre-qualify) the substrates that are intended to be used for printing conductors and insulators for the purposes of manufacturing stretchable layers or structures.

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IEC TR 62899-402-4:2021(E), which is a Technical Report, is a preparatory work for the documents dealing with the measurement method of the vertical direction (surface forms) of printed patterns made by printed electronics technology.
The printed pattern of interest in this document is limited to straight lines on substrates with a flat surface. This document focuses on the classification and measurement methods for surface forms from the nanometer scale to the micrometer scale, and suggests the strategy for the subsequent documents.

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This part of IEC 61188 describes the requirements of design and use for soldering surfaces of
land pattern on circuit boards. This document includes land pattern for surface mounted
components. These requirements are based on the solder joint requirements of
IEC 61191-2:2017.

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This part of IEC 61188 specifies the requirements for soldering surfaces on circuit boards. This
includes lands and land pattern for surface mounted components and also solderable hole
configurations for through-hole mounted components. These requirements are based on the
solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

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IEC 61189-2-807:2021 specifies a test method to determine the decomposition temperature (Td) of base laminate materials using thermogravimetric analysis (TGA).

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This part of IEC 62878 specifies the requirements and evaluation methods of electrical
connectivity. It is applicable to stacked electronic modules.

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IEC 62878-2-602:2021 specifies the requirements and evaluation methods of electrical connectivity. It is applicable to stacked electronic modules.

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IEC 61189-2-630:2018 specifies a test method to determine the amount of water absorbed by metal-clad laminates after conditioning in a pressure vessel for 1 h, 2 h, 3 h, 4 h or 5 h.

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IEC TR 62878-2-8:2021(E) describes a warpage control of active device embedded substrate along with parameters for determining warpage, which are useful during package assembly. Warpage results are explained using warpage driving force, resistance and neutral axis, for typical die embedded substrate, where the discrete active dies are placed in the core of substrate and interconnected to the substrate by direct Cu bonding. The same principles are applicable in other device embedded substrates. Even though the detailed structure of other device embedded substrates might be different, the origin and determination of the parameters of warpage are the same and thus the purpose of this report is to help engineers improve the warpage behaviours of their products by applying this principle.

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IEC 62878-2-602:2021 specifies the requirements and evaluation methods of electrical connectivity. It is applicable to stacked electronic modules.

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This part of IEC 61189 specifies methods for testing the characteristics of soldering paste using
fine solder particles (hereinafter referred to as solder paste).
This document is applicable to the solder paste using fine solder particle such as type 6, type 7
specified in IEC 61190-1-2 or finer particle sizes.
This type of solder paste is used for connecting wiring and components in high-density printed
circuit boards which are used in electronic or communication equipment and such, equipping
fine wiring (e.g., minimum conductor widths and minimum conductor gaps of 60 μm or less).
Test methods for the characteristics of solder paste in this document are considering the effect
of surface activation force due to the fine sized solder particles which could affect the test result
by existing test methods.

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IEC 62878-1:2019(E) specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3.
This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components.
The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

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This part of IEC 61189 is used to quantify the deleterious effects of flux residues on surface
insulation resistance (SIR) in the presence of moisture.
Interdigitated comb patterns comprising long parallel electrodes on an IPC B53 standardized
test coupon are used for the evaluation. Coupons are conditioned and measurements taken at
a high temperature and humidity. The electrodes are electrically biased during conditioning to
facilitate electrochemical reactions, as shown in Figure 1 and Figure 3.
Reference can be made to IEC TR 61189-5-506, which examines different geometry comb
patterns: 400 μm x 500 μm; 400 μm x 200 μm; and 318 μm x 318 μm.
Specifically, this method is designed to simultaneously assess:
• leakage current caused by ionized water films and electrochemical degradation of test
vehicle, (corrosion, dendritic growth);
• provide metrics that can appropriately be used for binary classification (e.g. go/no go;
pass/fail);
• compare, rank or characterize materials and processes.
This test is carried out at high humidity and heat conditions.

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IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

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IEC 61189-5-301:2021 specifies methods for testing the characteristics of soldering paste using fine solder particles (hereinafter referred to as solder paste). This document is applicable to the solder paste using fine solder particle such as type 6, type 7 specified in IEC 61190-1-2 or finer particle sizes. This type of solder paste is used for connecting wiring and components in high-density printed circuit boards which are used in electronic or communication equipment and such, equipping fine wiring (e.g., minimum conductor widths and minimum conductor gaps of 60 µm or less). Test methods for the characteristics of solder paste in this document are considering the effect of surface activation force due to the fine sized solder particles which could affect the test result by existing test methods.

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This part of IEC 61189 is used for evaluating the changes to the surface insulation resistance
of a pre-selected material set on a representative test coupon and quantifies the deleterious
effects of improperly used materials and processes that can lead to decreases in electrical
resistance.
An assembly process involves a number of different process materials including solder flux,
solder paste, solder wire, underfill materials, adhesives, staking compounds, temporary
masking materials, cleaning solvents, conformal coatings and more. The test employs two
different test conditions of 85 °C and 85 % relative humidity (RH), preferred for a process that
includes cleaning, or 40 °C and 90 % relative humidity (RH), preferred for processes where no
cleaning is involved.
NOTE 40 °C and 93 % RH can be used as an alternative to 40 °C and 90 % RH. Additional information is provided
in 5.4 and A.5.2.
Testing is material (set) and process / equipment specific. Qualifications are to be performed
using the production intent equipment, processes and materials.

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This part of IEC 61189 specifies the reflow soldering ability test method for components
mounted on organic rigid printed boards, the reflow heat resistance test method for organic rigid
printed boards, and the reflow soldering ability test method for the lands of organic rigid printed
boards in applications using solder alloys, which are eutectic or near-eutectic tin-lead (Pb), or
lead-free alloys.
The printed boards materials for this organic rigid printed boards are epoxide woven E-glass
laminated sheets that are specified in IEC 61249-2 (all parts).
The objective of this document is to ensure the soldering ability of the solder joint and of the
lands of the printed boards. In addition, test methods are provided to ensure that the printed
boards can resist the heat load to which they are exposed during soldering.
This document covers tests Tg1, Tg2, Tg3, Tg4, Tg5, and Tg6 listed in Table 1:

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IEC 62899-402-3:2021(E) specifies the optical measurement method for acquiring two-dimensional images of voids and obtaining the void-related attributes in the dried or cured printed patterns which are part of the electronic products in the field of printed electronics. The measurable voids using this document are limited to those that are distinguishable by the optical image measurement.
NOTE In this document, void means an imperfection of pattern observed from a two-dimensional (2D) top-view.

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IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

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IEC TR 61191-8:2021(E) gives guidelines for dealing with voiding in surface-mount solder joints of printed board assemblies for use in automotive electronics. This technical report focuses exclusively on voids in solder joints connecting packaged electronic or electromechanical components with printed boards (PBs). Voids in other solder joints (e.g. in a joint between a silicon die and a substrate within an electronic component, solder joints of through-hole components, etc.) are not considered. The technical background for the occurrence of voids in solder joints, the potential impact of voiding on printed board assembly reliability and functionality, the investigation of voiding levels in sample- and series-production by use of X‑ray inspection as well as typical voiding levels in different types of solder joints are discussed. Recommendations for the control of voiding in series production are also given. Annex A collects typical voiding levels of components and recommendations for acceptability.

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IEC 61189-5-301:2021 specifies methods for testing the characteristics of soldering paste using fine solder particles (hereinafter referred to as solder paste).
This document is applicable to the solder paste using fine solder particle such as type 6, type 7 specified in IEC 61190-1-2 or finer particle sizes.
This type of solder paste is used for connecting wiring and components in high-density printed circuit boards which are used in electronic or communication equipment and such, equipping fine wiring (e.g., minimum conductor widths and minimum conductor gaps of 60 µm or less).
Test methods for the characteristics of solder paste in this document are considering the effect of surface activation force due to the fine sized solder particles which could affect the test result by existing test methods.

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IEC 61189-5-502:2021 is used for evaluating the changes to the surface insulation resistance of a pre-selected material set on a representative test coupon and quantifies the deleterious effects of improperly used materials and processes that can lead to decreases in electrical resistance.

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IEC 61189-5-601:2021 specifies the reflow soldering ability test method for components mounted on organic rigid printed boards, the reflow heat resistance test method for organic rigid printed boards, and the reflow soldering ability test method for the lands of organic rigid printed boards in applications using solder alloys, which are eutectic or near-eutectic tin-lead (Pb), or lead-free alloys. The printed boards materials for this organic rigid printed boards are epoxide woven E-glass laminated sheets that are specified in IEC 61249-2 (all parts). The objective of this document is to ensure the soldering ability of the solder joint and of the lands of the printed boards. In addition, test methods are provided to ensure that the printed boards can resist the heat load to which they are exposed during soldering.

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IEC 61188-6-2:2021 describes the requirements of design and use for soldering surfaces of land pattern on circuit boards. This document includes land pattern for surface mounted components. These requirements are based on the solder joint requirements of IEC 61191‑2:2017.

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IEC 61189-5-501:2021 is used to quantify the deleterious effects of flux residues on surface insulation resistance (SIR) in the presence of moisture.

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IEC 62899-202-7:2021(E) provides a test method to measure the peel strength of a printed layer on a flexible substrate. This method calls for peeling the flexible substrate instead of an additional metal electroplating on the printed layer. The method described in this document can be used to compare the peel strengths of the printed layers on the same flexible substrate and thickness conditions. It can be used when the adhesion between the printed layer and flexible substrate is weaker than any other interface between the printed layer and the adhesive, the adhesive and the panel.

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IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

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