IEC 61189-2-720:2024

IEC 61189-2-720 ®
Edition 1.0 2024-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, circuit boards and other interconnection
structures and assemblies –
Part 2-720: Detection of defects in interconnection structures by measurement
of capacitance
Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres
structures d'interconnexion et ensembles –
Partie 2-720 : Détection de défauts présents dans les structures
d'interconnexion par mesurage de la capacité
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IEC 61189-2-720 ®
Edition 1.0 2024-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, circuit boards and other interconnection

structures and assemblies –
Part 2-720: Detection of defects in interconnection structures by measurement

of capacitance
Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres

structures d'interconnexion et ensembles –

Partie 2-720 : Détection de défauts présents dans les structures

d'interconnexion par mesurage de la capacité

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180  ISBN 978-2-8322-8327-1

– 2 – IEC 61189-2-720:2024 © IEC 2024
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Objective . 5
5 Test specimen . 6
6 Test method . 6
7 Test procedures . 7
8 Report . 8
Annex A (informative) The capacitive test method . 9
A.1 Test schematic . 9
A.2 Test result. 9

Figure 1 – Capacitance difference depending on the defect of mouse bite . 6
Figure 2 – Test specimen . 6
Figure 3 – Schematic of the capacitance test method . 7
Figure A.1 – Test schematic . 9

Table 1 – Definition of uppercase . 8
Table A.1 – Test result for the test specimen . 10

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
TEST METHODS FOR ELECTRICAL MATERIALS, CIRCUIT BOARDS AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 2-720: Detection of defects in interconnection
structures by measurement of capacitance

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
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shall not be held responsible for identifying any or all such patent rights.
IEC 61189-2-720 has been prepared by IEC technical committee 91: Electronics assembly
technology. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
91/1923/FDIS 91/1934/RVD
Full information on the voting for the approval of this International Standard can be found in the
report on voting indicated in the above table.
The language used for the development of this International Standard is English.

– 4 – IEC 61189-2-720:2024 © IEC 2024
This document has been drafted in accordance with the ISO/IEC Directives, Part 2 2, and
developed in accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC
Supplement, available at www.iec.ch/members_experts/refdocs. The main document types
developed by IEC are described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 61189 series, published under the general title Test methods for
electrical materials, circuit boards and other interconnection structures and assemblies, can be
found on the IEC website.
Future standards in this series will carry the new general title as cited above. Titles of existing
standards in this series will be updated at the time of the next edition.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

TEST METHODS FOR ELECTRICAL MATERIALS, CIRCUIT BOARD AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 2-720: Detection of defects in interconnection
structures by measurement of capacitance

1 Scope
This part of IEC 61189 provides a method to evaluate specific characteristics of circuit boards
by measuring the capacitance between conductor traces and a ground plane and can be used
for qualitative comparison of a test specimen to a reference board. This method is not intended
for quantitative measurements and for assessment of conformity to a specification.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60194-2, Printed boards design, manufacture and assembly – Vocabulary – Part 2:
Common usage in electronic technologies as well as printed board and electronic assembly
technologies
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194-2 apply. No
terms and definitions are listed in this document.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
4 Objective
For testing electrical characteristics of circuit board, generally an electrical open/short test that
shall measure the resistance between nets is the main test method. This open/short test is
possible only to look at the pass/the fail of circuits and not to look for any reliability issues of
circuit board like as mouse bite, delamination, void, and crack. Therefore, the general electrical
test has a limitation. Along with the capacitance test method, the electrical test method shall
check the existing reliability issues of circuit boards and this standardization of the additional
electrical test is necessary from the development stage. It is possible to accurately measure
the differences in the capacitance values of circuit boards before and after the reliability test.
This is sufficient for the development stage and reliability testing rather than in-production
testing because of the long test time of electrical test. Other than the probing contact issues,
there is no problem with the measurement uncertainty. It is possible to look for defects such as
open/short, mouse bite, delamination, void, and so on by analysing the test defect nets. In
looking for the capacitance test method, it shows the capacitance difference depending on the
pad width, pad length, and pad distance as shown in Figure 1. Figure 1 shows the defect of
mouse bite.
– 6 – IEC 61189-2-720:2024 © IEC 2024
Dimensions in micromillimetres

Figure 1 – Capacitance difference depending on the defect of mouse bite
5 Test specimen
Figure 2 shows the test specimen with top test pads and bottom test pads. It shall be prepared
to test real circuit boards and test coupons with a warpage specification of less than 2 mm for
improving adhesion with the ground metal plate.

Figure 2 – Test specimen
6 Test method
Figure 3 shows the schematic of the capacitance test method for measuring capacitance using
a capacitance tester such as an LCR meter and Impedance tester. After contacting the ground
metal plate of one side, the capacitance of all of pads of the other side shall be tested. The top
probing tests and the bottom probing tests are conducted.

(a) Top probing tests for all top pads

(b) Bottom probing tests for all bottom pads
Figure 3 – Schematic of the capacitance test method
7 Test procedures
The specimen shall be attached to the ground metal plate without any attached materials, and
it may need the ground metal plate with the vacuum suction holes for improving the attachment
between test specimen and ground metal plate. The 2-port capacitance tester shall be
connected at each probing point and ground metal plate. If looking at the test schematic in
Figure A.1, after attaching the test specimen to the ground metal plate, the 2-port impedance
tester shall be connected to the pads of the test specimen and ground metal plate. The ground
metal plate shall be the common ground and the capacitance shall be measured at each one-
side probing point. Also, it is necessary to measure at each other-side probing point. After that,
it shall analyze all the test results by comparing the average error ratio of all test specimens.
The test sequences to test the capacitance of circuit boards are as follows:
1) Reference board and test specimen shall be kept without packaging at standard
laboratory conditions for a minimum of 24 h before measurement.
2) Looking for the reference values with the average value for each test pad by testing 10
specimens, then determining the high limit ratio and the low limit ratio.
3) Cleaning the contamination on the ground metal plate.
4) Putting the test specimen on the ground metal plate and attaching the vacuum suction
without any attached materials.
5) Firstly, testing the capacitance characteristics of the one-side test specimen with the
impedance tester.
6) Repeat sequence 2).
– 8 – IEC 61189-2-720:2024 © IEC 2024
7) Secondly, attaching the other-side test specimen on the ground metal plate without any
attached materials.
8) Testing the capacitance characteristics of test specimen with the impedance tester.
9) Comparing the capacitance characteristics of all of test results with the average error
ratio according to high limit and low limit (referred to in Annex A).
Table 1 – Definition of uppercase
A B C D E F
REF- MEAS- Average High Low
Judgement
VALUE VALUE error LIMIT LIMIT
(Pass/Failure)
(F) (F) ratio (%) (%) (%)
A = the average capacitance value of 10 times testing values
B = the measured capacitance value
C (%) = (B/A) * 100
F(Pass) range = E ≤ C ≤ D
F(Failure) range = E > C or C > D
10) Judging the pass/failure rate for the electrical characteristics of the circuit board.
8 Report
The test report shall include:
a) test schematic for the capacitance test method;
b) measuring frequency;
c) the impedance tester for measuring the capacitance used;
d) the ground metal plate as the common ground used;
e) humidity to room temperature;
f) the date of the test;
g) the room temperature under which the test was conducted;
h) the test sequences;
i) high limit and low limit;
j) the table of the average error ratio for comparing all test results;
k) the pass/failure rate of the circuit board.

Annex A
(informative)
The capacitive test method
A.1 Test schematic
As shown in Figure A.1, the test schematic of the top (Figure A.1a)) and bottom pad probing
testing (Figure A.1b)) shall be prepared.

a) Top pad probing testing
b) Bottom pad probing testing
Figure A.1 – Test schematic
A.2 Test result
The average error ratio shall be calculated by comparing the reference value and the
measurement value. According to the high limit and low limit of 18 % each way, the pass/failure
of the test specimen shall be judged. As shown in Table A.1, 4 probing pads among the bottom
probing pads shall be failed and the test specimen shall be judged to have a reliability issue.
The high li
...