IEC 61189-2-808:2024

IEC 61189-2-808 ®
Edition 1.0 2024-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, printed board and other interconnection
structures and assemblies –
Part 2-808: Thermal resistance of an assembly by thermal transient method

Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres
structures et assemblages d'interconnexion –
Partie 2-808 : Résistance thermique d'un assemblage par la méthode du
transitoire thermique
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IEC 61189-2-808 ®
Edition 1.0 2024-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, printed board and other interconnection

structures and assemblies –
Part 2-808: Thermal resistance of an assembly by thermal transient method

Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres

structures et assemblages d'interconnexion –

Partie 2-808 : Résistance thermique d'un assemblage par la méthode du

transitoire thermique
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180  ISBN 978-2-8322-8804-7

– 2 – IEC 61189-2-808:2024 © IEC 2024
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Objective . 5
5 Test specimen . 6
6 Test equipment and procedures . 7
6.1 Test method and recommended test parameters . 7
6.2 Test equipment . 7
6.3 Test procedure . 8
7 Test result . 8
8 Report . 9
Annex A (informative) Additional test methods for thermal resistance . 11
Annex B (informative) Thermal resistance of die attach materials . 13
B.1 Test specimen . 13
B.2 Die attach materials . 13
B.3 Test result. 14
Annex C (informative) Uncertainty and repeatability for thermal resistance test . 16
C.1 Test specimen . 16
C.2 Test result. 16
Annex D (informative) Thermostat equipment . 18
Bibliography . 20

Figure 1 – Structure of an assembly . 6
Figure 2 – The fabricated test sample . 6
Figure 3 – Test structure for measuring thermal resistance . 8
Figure 4 – Test result for thermal resistance of an assembly . 9
Figure B.1 –Structure of test sample using die attach material . 13
Figure B.2 –The fabricated test sample using die attach material . 13
Figure B.3 – Test graph for die attach materials . 15
Figure C.1 – Test structure for measuring thermal resistance . 16
Figure C.2 – Test result for thermal resistance of assembly . 16
Figure D.1 – Connection of the thermostat unit to the T3Ster® main system unit . 18
Figure D.2 –Calibration diagram recorded by the T3Ster® thermostat . 19

Table 1 – Test result for thermal resistance of an assembly . 9
Table A.1 – ASTM C1113 . 11
Table A.2 – ASTM E1461 . 11
Table A.3 – ASTM D5470 . 12
Table B.1 – Properties for die attach materials . 14
Table B.2 – Test result for die attach materials . 15
Table C.1 – Test result for thermal resistance of assembly . 17

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARD AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 2-808: Thermal resistance of an assembly
by thermal transient method
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
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shall not be held responsible for identifying any or all such patent rights.
IEC 61189-2-808 has been prepared by IEC technical committee 91: Electronics assembly
technology. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
91/1935/FDIS 91/1955/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
– 4 – IEC 61189-2-808:2024 © IEC 2024
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 61189 series, published under the general title Test methods for
electrical materials, printed board and other interconnection structures and assemblies, can be
found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARD AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 2-808: Thermal resistance of an assembly
by thermal transient method
1 Scope
This part of IEC 61189 describes the thermal transient method to characterize the thermal
resistance of an assembly consisting of a heat source (e.g. power device), an attachment
material (e.g. solder) and a dielectric layer with electrode. This method is suitable to determine
the thermal resistance of materials and assembly methods as well as to optimize the thermal
flux to a heat sink.
NOTE This method is not intended to measure and specify the value of the thermal resistance of a dielectric
material. For that purpose, other standards exist. Examples are given in Annex A.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60194-2, Printed boards design, manufacture and assembly – Vocabulary – Part 2:
Common usage in electronic technologies as well as printed board and electronic assembly
technologies
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194-2 apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
4 Objective
The increasing power consumption of devices such as LED require a close examination of the
heat dissipating path within thermal conductive printed circuit boards (Annex A). Therefore,
effective removal of heat to maintain a safe junction temperature is the key to meeting the heat
flux by using thermal conductive material for printed circuit boards. Thermal resistance is the
crucial factor of heat dissipation dielectric materials in printed circuit board. Therefore, with the
aim to reduce the thermal resistance in circuit boards, it is proposed to determine the thermal
resistance by measuring the thermal transient characteristics of an assembly.

– 6 – IEC 61189-2-808:2024 © IEC 2024
5 Test specimen
To test the thermal resistance of an assembly, at first a test specimen shall be built, which
consists of a heat source (e.g. power device), an attachment material (e.g. solder) and a
dielectric layer with metal electrode. See Figure 1 for the structure. In the next step, the thermal
resistance of the assembly can be determined by comparison of the thermal transient
characteristics obtained when testing the assembly attached to a thermostat with or without a
thermal interface material (TIM). See Figure 3 and Clause 6 for the test description.

Key
1 Heat source
2 Solder
3 Electrode layer
4 Dielectric layer
Figure 1 – Structure of an assembly
To obtain an adequate thermal resistance, a layer of around 200 µm thick solder shall be used
for the die attach. The power source is a chip type device of the size 3,45 mm × 3,45 mm,
powered with 1 W through voltage common collector (VCC) and ground (GND). The dielectric
layer is a 2 cm × 2 cm substrate of 1 mm thickness. Figure 2 shows an example of such a test
specimen.
Key
1 Voltage common collector (VCC)
2 Ground (GND)
Figure 2 – The fabricated test sample

6 Test equipment and procedures
6.1 Test method and recommended test parameters
The thermal transient test equipment is a unique equipment for performing thermal
measurements on semiconductor devices like ICs, transistors, diodes, etc. The thermal
transient test equipment is most suitable for analyzing their thermal behavior, evaluating
packages and device mounting, and detecting defects. This equipment is a computer-controlled
equipment that can be used along with a PC hosting a special control and evaluation software.
This equipment as a mandatory part of configuration can apply programmed thermal excitations
and record complex thermal responses and provides built-in results evaluation procedures.
Results of these post-processing procedures include the pulse thermal resistance diagram,
time-constant spectrum, complex locus of the thermal impedance, differential and integral
structure or profile function (Annex B).
6.2 Test equipment
The thermal transient measurements can be performed using a commercially available test
equipment and specifically built test fixtures (Annex C). The test sample is mounted on the
temperature-controlled heat sink. The heat sink is maintained at a temperature of 25 °C and
controlled by a Keithley temperature controller. Initially, a junction-to-case thermal equilibrium
is ensured by applying a drive current (I ) for a sufficiently long duration; then the I is
drive drive
switched off and a small sense current (I ) is applied. When the system shifts to its new
sense
thermal equilibrium, the cooling down of the junction is measured.
From the transient time curves, the duration of cooling down can be taken to be how long the
heating current I needs to be applied to load the thermal capacities. The same time must
drive
be measured applying I to resolve the thermal path downstream to the respective capacity.
sense
One approach to determine the required measurement time is to modify the thermal interface
between the heat sink and the module. The time value at which the curve with the best possible
thermal interface and one with a bad thermal interface separate is approximately the
appropriate time duration for I and I when the thermal path upstream of the varied
drive sense
thermal interface is to be investigated. One can stepwise shorten the heat-up and cool-down
time afterward and observe at what setting, and at which time, values change in the logarithmic
time-derived curve. The shortest time for which the deviation of the time curves is still within
the signal-to-noise range of the curve with long heating and cooling times is still acceptable.
The thermal response at initial ‘0’ cycles and after 'n' cycles was measured. The measurement
time of 40 s is unnecessarily long. For the second test run with test samples B, the
measurement time was reduced to 5 s. In principle, this allowed us to reduce the heating up
and cooling down time further to 0,5 s, because data later than 300 ms are not included for data
analysis. The shape of the transient signal does not change when the cycle of heating up and
cooling down times is shortened. In this experiment, the thermal tape (thermal conductivity:
6,5 W/mK) with the thickness of 500 µm is used. Thermal tape as a thermal interface material
is used for separating the interface of the test sample through the comparison of thermal
transient characteristics depending on whether or not the test sample has thermal interface
material.
– 8 – IEC 61189-2-808:2024 © IEC 2024

Key
1 Heat source (1 W)
2 SAC305 solder (T: 200 µm)
3 Electrode layer (T: 35 µm)
4 Dielectric layer (T: 500 µm)
5 Thermal interface material (T: 500 µm)
6 Thermostat
NOTE The thermostat is the temperature-controlled system (Annex D). The thermostat has the thermocouples
inside system.
Figure 3 – Test structure for measuring thermal resistance
6.3 Test procedure
The test sequences to test the thermal resistance of an assembly are as follows:
1) cleaning the contamination on the thermostat;
2) firstly, attaching the test sample on the thermostat without the thermal interface material;
3) testing the thermal transient characteristics of the test sample by biasing the power;
• driving current (I ): 1 500 mA
drive
• sensor current (I ) for test: 10 mA
sense
• total power: 4,548 W
• TIM: thermal pad (thickness: 500 µm)
• temperature coefficient: −1,272 mV/°C
4) repeat the sequence 1);
5) secondly, attaching the test sample on the thermostat by using thermal interface material;
6) testing the thermal transient characteristics of the test sample by biasing the power;
7) comparing the thermal transient characteristics of the test sample depending on with or
without the thermal interface material;
8) extracting the thermal resistance value of an assembly with test results.
7 Test result
From the cumulative structure function of the thermal transient characteristics, after converting
to the cumulative structure function because it is eased to look for the separation point, the
thermal resistance value is extracted by looking for the separated point from the measurement
excel sheet instead of the visible graph (see Figure 4 and Table 1). Detailed information can be
found in JESD-51-14(Published: Nov 2010), clause 4, Junction-to-Case Thermal Resistance
Measurement (Test Method).
Key
1 The measured of thermal resistance of an assembly
2 The measured thermal resistance of assembly without TIM
3 The measured thermal resistance of assembly with TIM
NOTE C is thermal capacitance and K is temperature (Kelvin).
th
Figure 4 – Test result for thermal resistance of an assembly
In order to extract value for thermal resistance of assembly, the separated value from the
measurement results, depending on with TIM and without TIM, should be looked for.
Table 1 – Test result for thermal resistance of an assembly
Total thermal resistance Total thermal resistance Thermal resistance of
(without TIM) (with TIM) an assembly
K/W K/W K/W
10,86 9,68 9,2
8 Report
This test report shall include:
a) structure of the test specimen;
b) thermal tape used as TIM;
c) the used power sources;
d) the date of the test;
e) the room temperature under which the test was conducted;
f) the test sequences;
g) the graph of the cumulative structure function;
h) the total thermal resistance of the test specimen with or without TIM;
i) the thermal resistance of an assembly.

– 10 – IEC 61189-2-808:2024 © IEC 2024
The result value of an assembly separated differently from the measurement results, depending
on the presence or absence of TIM, is defined as the thermal resistance and assembly. Detailed
information can be found in JESD-51-14 (Published: Nov 2010), clause 4, Junction-to-Case
Thermal Resistance Measurement (Test Method).

Annex A
(informative)
Additional test methods for thermal resistance
Table A.1, Table A.2 and Table A.3 show additional test methods for thermal resistance.
Table A.1 – ASTM C1113
Measuring method Hot wire type （ASTM C1113)
Principle of measurement
λ (q / 4π) ln(t2−−t1)/ (T2 T1)
where
λ thermal conductivity
t time
q heat value
T temperature
Features Thin film sample： > 300 μm
Contact measuring
(Low precision because of the contact thermal resistance at probe/sample)

Table A.2 – ASTM E1461
Measuring method Laser flash type (ASTM E1461)
Principle of measurement
Calculate the thermal conductivity from temperature rising curve by simulation
fitting.
Features Thin film sample OK
Non-contact measuring (high precision)
Multi-layer sample OK (CCL etc.)

=
– 12 – IEC 61189-2-808:2024 © IEC 2024
Table A.3 – ASTM D5470
Measuring method Thermal resistance type (ASTM D5470)
Principle of measurement
Calculate the thermal resistance from amount of heat (W) and temperature rising
(∆T) at heat insulating box. Convert the thermal conductivity:
λ=h / (R・ A)
Where
h thickness
R thermal resistance
A sample area
Features Standard for thermal resistance measuring
(Have a tendency to show high thermal conductivity)

Annex B
(informative)
Thermal resistance of die attach materials
B.1 Test specimen
As shown in Figure B.1, high power packages largely consist of high-power source chip (size:
3.45 mm × 3.45 mm), die attach material and Si heat slug. This package was designed to be
used in checking die attach quality. The width of top electrode was 300 µm and the whole
package was 500 µm. High power packages have a sandwich-like heat removal path of different
materials ending in the cooling slug. Table B.2 shows the fabricated test sample.

Figure B.1 –Structure of test sample using die attach material

Figure B.2 –The fabricated test sample using die attach material
B.2 Die attach materials
The material specification used in the fabricated high-power package is presented in Table B.1.
Here, thermal conductivity is a property of materials that expresses the heat that will flow
through the material if a certain temperature gradient exists over the material. The thermal
conductivity is usually expressed in W/m K. It is so very difficult to measure thermal conductivity
because it usually requires a carefully planned laboratory experiment and a lot of time to get to
equilibrium. In Table B.1, the thermal conductivity of structures is the crucial value in the
thermal transient. In this experiment, high power packages are fabricated with die attach
materials such as Ag paste, SAC305 type solder paste and 80Au–20Sn eutectic alloy by using
E-beam evaporator.
– 14 – IEC 61189-2-808:2024 © IEC 2024
Table B.1 – Properties for die attach materials
Material Thickness Thermal Conductivity
(µm) (W/mK)
Au/Sn eutectic bonding 5 28
Solder paste 10 4,2
Ag paste 10 0,616
B.3 Test result
Figure B.3 shows measured differential structure functions of high-power packages for the good
case of three different die attach materials. As shown in Figure B.3, we know that the
measurements of the thermal resistance of die attach materials take into account the difference
of die attach quality by using the differential structure functions. The measurement principle is
based on the shift of peaks in the differential structure function for die attach materials as
illustrated by Figure B.3. In Figure B.3, among die attach materials we can see the result that
die attach quality of Au/Sn eutectic bonding is much better than that of Ag paste and solder
paste, and that the thermal resistance of Au/Sn eutectic bonding is about 1 K/W and 8 K/W less
than that of solder paste and Ag paste, respectively. The summary for simulated and measured
thermal transient characteristics of die attach in high power packages is presented in Table B.2.
We know that all the die attach quality and reliability can be done with the cumulative and
differential structure functions using the thermal transient analysis in high power packages.

a) Au/Sn eutectic bonding
b) solder paste
c) Ag paste
Figure B.3 – Test graph for die attach materials
Table B.2 – Test result for die attach materials
Structure Simulation result Measured result
(K/W) (K/W)
Au/Sn eutectic bonding 3,56 3,5
Solder paste 4,49 4,4 to 4,6
Ag paste 11,9 11,5 to 14,2
– 16 – IEC 61189-2-808:2024 © IEC 2024
Annex C
(informative)
Uncertainty and repeatability for thermal resistance test
C.1 Test specimen
As shown in Figure C.1, the test specimen shall be prepared with the other assembly with the
different dielectric layer for checking the uncertainty and repeatability for the thermal resistance
test.
Figure C.1 – Test structure for measuring thermal resistance
C.2 Test result
Figure C.2 and Table C.1 show the test results of the thermal resistance for a test specimen
with the other assembly. It shall be easy to check the thermal resistance of an assembly
depending on the structure of the assembly with the different dielectric material.

Figure C.2 – Test result for thermal resistance of assembly

Table C.1 – Test result for thermal resistance of assembly
Total thermal resistance Total thermal resistance Thermal resistance of
(without TIM) (with TIM) assembly
K/W K/W K/W
7,65 8,24 7,65
– 18 – IEC 61189-2-808:2024 © IEC 2024
Annex D
(informative)
Thermostat equipment
A Peltier-cell cooled, dry thermostat (Figure D.1) is available for the thermal transient
equipment as an add-on option. The thermostat unit is controlled by the thermostat control port
of the thermal transient main system unit. The thermostat connection cable has to be connected
to the socket on the T3Ster® controller. The T3Ster® Measurement Control & Evaluation
software performs simultaneous control of the thermostat unit and the entire thermal transient
equipment. The thermostat unit is suitable to calibrate temperature sensors used for
steady-state and transient thermal testing semiconductor devices and packages, and to be used
as a "cold plate" for thermal testing as well.

Figure D.1 – Connection of the thermostat unit to the T3Ster® main system unit
The temperature of the thermostat – when properly connected and switched on – is controlled
by the thermal transient software. That is why the thermostat temperature may run away if the
thermostat is switched on without software control, thus switch on the thermostat only if the
thermal is transient. The main system unit is switched on and the thermal transient software is
in the position to control the thermostat.
Major parameters:
• Temperature range: 5 to 90 °C;
• Accuracy: ± 0,2 °C;
• Settling time: 90 s for ∆T = +10 °C (in case of an empty cavity);
3 3
• Cavity size: 46 × 46 ×10 mm (extendable to 46 × 46 × 15 mm );
• Power sinking capability: min 10 W (above 30 °C);
• Overheating protection: above 95 °C;
• Size (w/h/d): 24 cm × 16 cm × 37 cm;
___________
T3Ster® is an example of a suitable product(s) available commercially. This information is given for the
convenience of users of this document and does not constitute an endorsement by IEC of this product.

• Weight: approximately 4 kg;
• Supply: own 110 V to 230 V / 50 Hz to 60 Hz power mains.
The thermostat module of the thermal transient measurement control and evaluation tool
provides automatic temperature excursion and calculation of the sensitivity parameter of diode
or resistance sensors. The recorded calibration diagrams can be saved for later use
(Figure D.2).
Figure D.2 –Calibration diagram recorded by the T3Ster® thermostat

– 20 – IEC 61189-2-808:2024 © IEC 2024
Bibliography
JESD51-14, Transient Dual Interface Test Method for the Measurement of the Thermal
Resistance Junction-to-Case of Semiconductor Devices with Heat Flow Through a Single Path
JESD-51-50, Overview of Methodologies for the Thermal Measurement of Single- and Multi-
Chip, Single- and Multi-PN-Junction Light-Emitting Diodes (LEDs)
JESD-51-51, Implementation of the Electrical Test Method for the Measurement of the Real
Thermal Resistance and Impedance of Light-emitting Diodes with Exposed Cooling Surface
JEDEC JESD51-1, Integrated circuit thermal measurement method - electrical test method
(single semiconductor device)
___________
– 22 – IEC 61189-2-808:2024 © IEC 2024
SOMMAIRE
AVANT-PROPOS . 23
1 Domaine d'application . 25
2 Références normatives . 25
3 Termes et définitions . 25
4 Objectif . 25
5 Échantillon d’essai . 26
6 Équipement d’essai et modes opératoires . 27
6.1 Méthode d’essai et paramètres d’essai recommandés . 27
6.2 Équipement d'essai . 27
6.3 Procédure d’essai . 28
7 Résultat d’essai . 29
8 Rapport . 30
Annexe A (informative) Méthodes d'essai supplémentaires de la résistance thermique . 31
Annexe B (informative) Résistance thermique des matériaux de fixation de puce . 33
B.1 Échantillon d’essai . 33
B.2 Matériaux de fixation de puce . 34
B.3 Résultat d’essai . 34
Annexe C (informative) Incertitude et répétabilité pour l’essai de résistance thermique . 37
C.1 Échantillon d’essai . 37
C.2 Résultat d’essai . 37
Annexe D (informative) Thermostat de l’équipement . 38
Bibliographie . 40

Figure 1 – Structure d’un assemblage . 26
Figure 2 – Échantillon d’essai fabriqué . 26
Figure 3 – Structure d’essai pour la mesure de la résistance thermique . 28
Figure 4 – Résultat d’essai pour la résistance thermique d’un assemblage . 29
Figure B.1 – Structure de l’échantillon d’essai avec matériau de fixation de puce . 33
Figure B.2 – Échantillon d’essai fabriqué avec matériau de fixation de puce . 33
Figure B.3 – Graphique d’essai pour les matériaux de fixation de puces . 36
Figure C.1 – Structure d’essai pour la mesure de la résistance thermique . 37
Figure C.2 – Résultat d’essai pour la résistance thermique d’un assemblage . 37
Figure D.1 – Connexion de l’unité thermostatique à l’unité principale du
système T3Ster® . 38
Figure D.2 – Diagramme d'étalonnage enregistré par le thermostat T3Ster® . 39

Tableau 1 – Résultat d’essai pour la résistance thermique d’un assemblage . 29
Tableau A.1 – ASTM C1113 . 31
Tableau A.2 – ASTM E1461 . 31
Tableau A.3 – ASTM D5470 . 32
Tableau B.1 – Propriétés des matériaux de fixation de puce . 34
Tableau B.2 – Résultat d’essai pour les matériaux de fixation de puces . 36
Tableau C.1 – Résultat d’essai pour la résistance thermique d’un assemblage . 37

COMMISSION ÉLECTROTECHNIQUE INTERNATIONALE
____________
MÉTHODES D’ESSAI POUR LES MATÉRIAUX ÉLECTRIQUES,
LES CARTES IMPRIMÉES ET AUTRES STRUCTURES
ET ASSEMBLAGES D’INTERCONNEXION –

Part 2-808: Résistance thermique d'un assemblage
par la méthode du transitoire thermique

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