IEC 61691-1-1:2004

INTERNATIONAL IEC
STANDARD 61691-1-1
First edition
2004-10
™
IEEE 1076
Behavioural languages –
Part 1-1:
VHDL language reference manual

Reference number
IEC 61691-1-1(E):2004
IEEE Std. 1076(E):2002
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the
60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
Consolidated editions
The IEC is now publishing consolidated versions of its publications. For example,
edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
base publication incorporating amendment 1 and the base publication incorporating
amendments 1 and 2.
Further information on IEC publications
The technical content of IEC publications is kept under constant review by the IEC,
thus ensuring that the content reflects current technology. Information relating to
this publication, including its validity, is available in the IEC Catalogue of
publications (see below) in addition to new editions, amendments and corrigenda.
Information on the subjects under consideration and work in progress undertaken
by the technical committee which has prepared this publication, as well as the list
of publications issued, is also available from the following:
• IEC Web Site (www.iec.ch)
• Catalogue of IEC publications
The on-line catalogue on the IEC web site (www.iec.ch/searchpub) enables you to
search by a variety of criteria including text searches, technical committees
and date of publication. On-line information is also available on recently issued
publications, withdrawn and replaced publications, as well as corrigenda.
• IEC Just Published
This summary of recently issued publications (www.iec.ch/online_news/ justpub)
is also available by email. Please contact the Customer Service Centre (see
below) for further information.
• Customer Service Centre
If you have any questions regarding this publication or need further assistance,
please contact the Customer Service Centre:

Email: custserv@iec.ch
Tel: +41 22 919 02 11
Fax: +41 22 919 03 00
INTERNATIONAL IEC
STANDARD 61691-1-1
First edition
2004-10
™
IEEE 1076
Behavioural languages –
Part 1-1:
VHDL language reference manual

Copyright © IEEE 2004 ⎯ All rights reserved
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by the Institute of Electrical and Electronics Engineers, Inc.
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
The Institute of Electrical and Electronics Engineers, Inc, 3 Park Avenue, New York, NY 10016-5997, USA
Telephone: +1 732 562 3800 Telefax: +1 732 562 1571 E-mail: stds-info@ieee.org Web: www.standards.ieee.org
Commission Electrotechnique Internationale
International Electrotechnical Commission
Международная Электротехническая Комиссия

– 2 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)
CONTENTS
FOREWORD . 5
IEEE Introduction . 9
0. Overview of this standard . 10
0.1 Intent and scope of this standard. 10
0.2 Structure and terminology of this standard. 10
1. Design entities and configurations. 13
1.1 Entity declarations . 13
1.2 Architecture bodies . 17
1.3 Configuration declarations. 20
2. Subprograms and packages. 26
2.1 Subprogram declarations . 26
2.2 Subprogram bodies . 29
2.3 Subprogram overloading. 32
2.4 Resolution functions . 34
2.5 Package declarations. 35
2.6 Package bodies. 36
2.7 Conformance rules. 38
3. Types. 39
3.1 Scalar types . 40
3.2 Composite types. 46
3.3 Access types. 51
3.4 File types. 54
3.5 Protected types. 56
4. Declarations . 60
4.1 Type declarations. 60
4.2 Subtype declarations . 61
4.3 Objects . 62
4.4 Attribute declarations. 76
4.5 Component declarations. 77
4.6 Group template declarations . 77
4.7 Group declarations. 78
5. Specifications. 80
5.1 Attribute specification. 80
5.2 Configuration specification. 82
5.3 Disconnection specification. 90
6. Names . 93
6.1 Names . 93
6.2 Simple names. 94
6.3 Selected names. 95
6.4 Indexed names . 97
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEE 1076-2002(E)
6.5 Slice names . 98
6.6 Attribute names. 98
7. Expressions . 100
7.1 Expressions . 100
7.2 Operators. 101
7.3 Operands . 109
7.4 Static expressions. 116
7.5 Universal expressions . 118
8. Sequential statements. 120
8.1 Wait statement . 122
8.2 Assertion statement. 119
8.3 Report statement . 123
8.4 Signal assignment statement. 123
8.5 Variable assignment statement . 128
8.6 Procedure call statement . 129
8.7 If statement. 130
8.8 Case statement . 130
8.9 Loop statement. 131
8.10 Next statement . 132
8.11 Exit statement. 133
8.12 Return statement . 133
8.13 Null statement . 133
9. Concurrent statements. 135
9.1 Block statement. 135
9.2 Process statement. 136
9.3 Concurrent procedure call statements. 137
9.4 Concurrent assertion statements . 138
9.5 Concurrent signal assignment statements . 139
9.6 Component instantiation statements . 144
9.7 Generate statements . 150
10. Scope and visibility. 151
10.1 Declarative region. 151
10.2 Scope of declarations . 152
10.3 Visibility . 153
10.4 Use clauses. 156
10.5 The context of overload resolution . 157
11. Design units and their analysis . 158
11.1 Design units . 158
11.2 Design libraries . 158
11.3 Context clauses . 159
11.4 Order of analysis. 160
vi Copyright © 2002 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

– 4 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)
12. Elaboration and execution. 161
12.1 Elaboration of a design hierarchy . 161
12.2 Elaboration of a block header . 163
12.3 Elaboration of a declarative part. 164
12.4 Elaboration of a statement part . 168
12.5 Dynamic elaboration. 171
12.6 Execution of a model . 171
13. Lexical elements . 178
13.1 Character set. 178
13.2 Lexical elements, separators, and delimiters . 181
13.3 Identifiers . 182
13.4 Abstract literals . 182
13.5 Character literals . 184
13.6 String literals. 184
13.7 Bit string literals. 185
13.8 Comments . 186
13.9 Reserved words. 187
13.10 Allowable replacements of characters . 190
14. Predefined language environment. 189
14.1 Predefined attributes . 189
14.2 Package STANDARD . 203
14.3 Package TEXTIO. 210
Annex A (informative) Syntax summary . 215
Annex B (informative) Glossary . 234
Annex C (informative) Potentially nonportable constructs. 253
Annex D (informative) Changes from IEEE Std 1076, 2000 Edition . 254
Annex E (informative) Features under consideration for removal. 255
Annex F (informative) Bibliography. 256
Annex G (informative) List of Participants. 257
Index . 258
vii
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEE 1076-2002(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
BEHAVIOURAL LANGUAGES –
Part 1-1: VHDL language reference manual

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization
comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to
promote international co-operation on all questions concerning standardization in the electrical and
electronic fields. To this end and in addition to other activities, IEC publishes International Standards,
Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter
referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National
Committee interested in the subject dealt with may participate in this preparatory work. International,
governmental and non-governmental organizations liaising with the IEC also participate in this preparation.
IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with
conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has
representation from all interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly
indicated in the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC/IEEE 61691-1-1 has been processed through IEC technical
committee 93: Design automation.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1076 (2002) 93/193/FDIS 93/198/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives.
The committee has decided that the contents of this publication will remain unchanged until
2007.
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

– 6 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)
IEC 61691 consists of the following parts, under the general title Behavioural languages:
IEC/IEEE 61691-1-1, Part 1-1: VHDL language reference manual
IEC 61691-2, Part 2: VHDL multilogic system for model interoperability
IEC 61691-3-1, Part 3-1: Analog description in VHDL (under consideration)
IEC 61691-3-2, Part 3-2: Mathematical operation in VHDL
IEC 61691-3-3, Part 3-3: Synthesis in VHDL
IEC 61691-3-4, Part 3-4: Timing expressions in VHDL (under consideration)
IEC 61691-3-5, Part 3-5: Library utilities in VHDL (under consideration)
IEC/IEEE 61691-4, Part 4: Verilog® hardware description language
IEC/IEEE 61691-5, Part 5: VITAL ASIC (application specific integrated circuit) modeling
specification
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEE 1076-2002(E)
IEC/IEEE Dual Logo International Standards
This Dual Logo International Standard is the result of an agreement between the IEC and the Institute of
Electrical and Electronics Engineers, Inc. (IEEE). The original IEEE Standard was submitted to the IEC for
consideration under the agreement, and the resulting IEC/IEEE Dual Logo International Standard has been
published in accordance with the ISO/IEC Directives.
IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating
Committees of the IEEE Standards Association (IEEE-SA) Standards Board. The IEEE develops its standards
through a consensus development process, approved by the American National Standards Institute, which
brings together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers
are not necessarily members of the Institute and serve without compensation. While the IEEE administers the
process and establishes rules to promote fairness in the consensus development process, the IEEE does not
independently evaluate, test, or verify the accuracy of any of the information contained in its standards.
Use of an IEC/IEEE Dual Logo International Standard is wholly voluntary. The IEC and IEEE disclaim liability for
any personal injury, property or other damage, of any nature whatsoever, whether special, indirect,
consequential, or compensatory, directly or indirectly resulting from the publication, use of, or reliance upon
this, or any other IEC or IEEE Standard document.
The IEC and IEEE do not warrant or represent the accuracy or content of the material contained herein, and
expressly disclaim any express or implied warranty, including any implied warranty of merchantability or fitness
for a specific purpose, or that the use of the material contained herein is free from patent infringement.
IEC/IEEE Dual Logo International Standards documents are supplied “AS IS”.
The existence of an IEC/IEEE Dual Logo International Standard does not imply that there are no other ways to
produce, test, measure, purchase, market, or provide other goods and services related to the scope of the
IEC/IEEE Dual Logo International Standard. Furthermore, the viewpoint expressed at the time a standard is
approved and issued is subject to change brought about through developments in the state of the art and
comments received from users of the standard.
Every IEEE Standard is subjected to review at least every five years for revision or reaffirmation. When a
document is more than five years old and has not been reaffirmed, it is reasonable to conclude that its contents,
although still of some value, do not wholly reflect the present state of the art. Users are cautioned to check to
determine that they have the latest edition of any IEEE Standard.
In publishing and making this document available, the IEC and IEEE are not suggesting or rendering
professional or other services for, or on behalf of, any person or entity. Neither the IEC nor IEEE is undertaking
to perform any duty owed by any other person or entity to another. Any person utilizing this, and any other
IEC/IEEE Dual Logo International Standards or IEEE Standards document, should rely upon the advice of a
competent professional in determining the exercise of reasonable care in any given circumstances.
Interpretations – Occasionally questions may arise regarding the meaning of portions of standards as they relate
to specific applications. When the need for interpretations is brought to the attention of IEEE, the Institute will
initiate action to prepare appropriate responses. Since IEEE Standards represent a consensus of concerned
interests, it is important to ensure that any interpretation has also received the concurrence of a balance of
interests. For this reason, IEEE and the members of its societies and Standards Coordinating Committees are
not able to provide an instant response to interpretation requests except in those cases where the matter has
previously received formal consideration.
Comments for revision of IEC/IEEE Dual Logo International Standards are welcome from any interested party,
regardless of membership affiliation with the IEC or IEEE. Suggestions for changes in documents should be in
the form of a proposed change of text, together with appropriate supporting comments. Comments on standards
and requests for interpretations should be addressed to:
Secretary, IEEE-SA Standards Board, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331, USA and/or
General Secretary, IEC, 3, rue de Varembé, PO Box 131, 1211 Geneva 20, Switzerland.
Authorization to photocopy portions of any individual standard for internal or personal use is granted by the
Institute of Electrical and Electronics Engineers, Inc., provided that the appropriate fee is paid to Copyright
Clearance Center. To arrange for payment of licensing fee, please contact Copyright Clearance Center,
Customer Service, 222 Rosewood Drive, Danvers, MA 01923 USA; +1 978 750 8400. Permission to photocopy
portions of any individual standard for educational classroom use can also be obtained through the Copyright
Clearance Center.
NOTE – Attention is called to the possibility that implementation of this standard may require use of subject
matter covered by patent rights. By publication of this standard, no position is taken with respect to the
existence or validity of any patent rights in connection therewith. The IEEE shall not be responsible for
identifying patents for which a license may be required by an IEEE standard or for conducting inquiries into the
legal validity or scope of those patents that are brought to its attention.

Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

– 8 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)
IEEE Standard VHDL
Language Reference Manual
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 26 July 2002
American National Standards Institute
Approved 21 March 2002
IEEE-SA Standards Board
Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation
intended for use in all phases of the creation of electronic systems. Because it is both machine read-
able and human readable, it supports the development, verification, synthesis, and testing of hard-
ware designs; the communication of hardware design data; and the maintenance, modification, and
procurement of hardware. Its primary audiences are the implementors of tools supporting the lan-
guage and the advanced users of the language.
Keywords: computer languages, electronic systems, hardware, hardware design, VHDL

Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEE 1076-2002(E)
IEEE Introduction
The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of
the creation of electronic systems. Because it is both machine readable and human readable, it supports the
development, verification, synthesis, and testing of hardware designs; the communication of hardware design
data; and the maintenance, modification, and procurement of hardware.
This document specifies IEEE Std 1076-2002™, which is a revision of IEEE Std 1076, 2000 Edition™. This
revision incorporates the addition of protected types and enhancements to the specification of shared vari-
ables which were completed in IEEE Std 1076, 2000 Edition™. As VHDL is now in wide use throughout the
world, the 1076 Working Group endeavored to maintain a high level of stability with this revision. Although
this revision does not provide significant changes to VHDL, it does enhance and clarify the language specifi-
cation in several areas. Most notable is the improvement in the specification of default binding rules, buffer
ports, scope and visibility, allowance of multi-byte characters in comments and other areas which will
increase the portability of descriptions.
The maintenance of the VHDL language standard is an ongoing process. The chair of the VHDL Analysis
and Standardization Group (VASG), otherwise known as the 1076 Working Group, extends his gratitude to
all who have participated in this revision and encourages the participation of all interested parties in future
language revisions. If interested in participating, please contact the VASG at stds-vasg@ieee.org or visit the
following website: http://www.eda.org/pub/vasg.

IEEE-SA Trademark Usage/Compliance Statement
Proper usage of the trademark IEEE Std 1076-2002™ is mandatory and is to be followed in all references of ®
the Standard. The mark IEEE is the registered trademark of the Institute of Electrical and Electronics
Engineers, Inc., and must be used in bold type. It is to appear with the registered trademark symbol “®” the
first time “IEEE” appears in the text. The use of “IEEE Std 1076-2002” should include the trademark symbol
“TM” (e.g., IEEE Std 1076-2002™) at least the first time it is used in text, unless the number of the ®
standard is also trademark registered (e.g., 802 ), then the symbol “®” must be used.
It is not permissible to use the standard number alone or with “IEEE” to indicate conformance or compliance
with the associated standard. The user of the Standard should contact the Manager, Standards Licensing and
Contracts for information concerning issues regarding indicating product compliance with an IEEE standard.
To represent that a product has been designed to meet an IEEE standard, it is permissible to state that “the
product has been engineered, designed or manufactured with the intent to meet the requirements of IEEE Std
1076-2002™.” However, it is not permissible to state or refer to a product as “1076 compliant,” “1076
certified,” “IEEE 1076 conformant,” “IEEE 1076 certified,” or the like, unless the user has obtained a
Certification License from the IEEE.

Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

– 10 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)
BEHAVIOURAL LANGUAGES –
Part 1-1: VHDL language reference manual
0. Overview of this standard
This clause describes the purpose and organization of this standard, the IEEE Standard VHDL Language
Reference Manual.
0.1 Intent and scope of this standard
The intent of this standard is to define VHSIC Hardware Description Language (VHDL) accurately. Its
primary audiences are the implementor of tools supporting the language and the advanced user of the
language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the
language in some detail prior to reading this standard. These resources generally focus on how to use the
language, rather than how a VHDL-compliant tool is required to behave.
At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it
may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications
may be published in separate documents. Such documents modify this standard at the time of their publica-
tion and remain in effect until superseded by subsequent documents or until the standard is officially revised.
0.2 Structure and terminology of this standard
This standard is organized into clauses, each of which focuses on some particular area of the language.
Within each clause, individual constructs or concepts are discussed in each subclause.
Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of the
construct is described using one or more grammatical productions.
A set of paragraphs describing the meaning and restrictions of the construct in narrative form then follow.
Unlike many other IEEE standards, which use the verb shall to indicate mandatory requirements of the stan-
dard and may to indicate optional features, the verb is is used uniformly throughout this document. In all
cases, is is to be interpreted as having mandatory weight.
Additionally, the word must is used to indicate mandatory weight. This word is preferred over the more com-
mon shall, as must denotes a different meaning to different readers of this standard.
a) To the developer of tools that process VHDL, must denotes a requirement that the standard imposes.
The resulting implementation is required to enforce the requirement and to issue an error if the
requirement is not met by some VHDL source text.
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEEIEEE 1076-2002(E)
Std 1076-2002 IEEE STANDARD VHDL
b) To the VHDL model developer, must denotes that the characteristics of VHDL are natural conse-
quences of the language definition. The model developer is required to adhere to the constraint
implied by the characteristic.
c) To the VHDL model user, must denotes that the characteristics of the models are natural conse-
quences of the language definition. The model user can depend on the characteristics of the model
implied by its VHDL source text.
Finally, each clause may end with examples, notes, and references to other pertinent clauses.
0.2.1 Syntactic description
The form of a VHDL description is described by means of context-free syntax using a simple variant of the
backus naur form; in particular:
a) Lowercase words in roman font, some containing embedded underlines, are used to denote syntactic
categories, for example:
formal_port_list
Whenever the name of a syntactic category is used, apart from the syntax rules themselves, spaces
take the place of underlines (thus, “formal port list” would appear in the narrative description when
referring to the above syntactic category).
b) Boldface words are used to denote reserved words, for example:
array
Reserved words must be used only in those places indicated by the syntax.
c) A production consists of a left-hand side, the symbol “::=” (which is read as “can be replaced by”),
and a right-hand side. The left-hand side of a production is always a syntactic category; the right-
hand side is a replacement rule. The meaning of a production is a textual-replacement rule: any
occurrence of the left-hand side may be replaced by an instance of the right-hand side.
d) A vertical bar (|) separates alternative items on the right-hand side of a production unless it occurs
immediately after an opening brace, in which case it stands for itself, as follows:
letter_or_digit ::= letter | digit
choices ::= choice { | choice }
In the first instance, an occurrence of “letter_or_digit” can be replaced by either “letter” or “digit.” In
the second case, “choices” can be replaced by a list of “choice,” separated by vertical bars [see item
f) for the meaning of braces].
e) Square brackets [ ] enclose optional items on the right-hand side of a production; thus, the following
two productions are equivalent:
return_statement ::= return [ expression ] ;
return_statement ::= return ; | return expression ;
Note, however, that the initial and terminal square brackets in the right-hand side of the production
for signatures (see 2.3.2) are part of the syntax of signatures and do not indicate that the entire right-
hand side is optional.
f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may
appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive
rule. Thus, the following two productions are equivalent:
term ::= factor { multiplying_operator factor }
term ::= factor | term multiplying_operator factor
2 Copyright © 2002 IEEE. All rights reserved.
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

– 12 – IEC 61691-1-1:2004(E)
IEEE 1076-2002(E)IEEE
LANGUAGE REFERENCE MANUAL Std 1076-2002
g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category
name without the italicized part. The italicized part is intended to convey some semantic informa-
tion. For example, type_name and subtype_name are both syntactically equivalent to name alone.
h) The term simple_name is used for any occurrence of an identifier that already denotes some declared
entity.
0.2.2 Semantic description
The meaning and restrictions of a particular construct are described with a set of narrative rules immediately
following the syntactic productions. In these rules, an italicized term indicates the definition of that term and
identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see 14.2).
The following terms are used in these semantic descriptions with the following meanings:
erroneous: The condition described represents an ill-formed description; however, implementations are not
required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in
general to detect the condition during the processing of the language.
error: The condition described represents an ill-formed description; implementations are required to detect
the condition and report an error to the user of the tool.
illegal: A synonym for “error.”
legal: The condition described represents a well-formed description.
0.2.3 Front matter, examples, notes, references, and annexes
Prior to this subclause are several pieces of introductory material; following Clause 14 are some annexes and
an index. The front matter, annexes, and index serve to orient and otherwise aid the user of this standard, but
are not part of the definition of VHDL.
Some clauses of this standard contain examples, notes, and cross-references to other clauses of the standard;
these parts always appear at the end of a clause. Examples are meant to illustrate the possible forms of the
construct described. Illegal examples are italicized. Notes are meant to emphasize consequences of the rules
described in the clause or elsewhere. In order to distinguish notes from the other narrative portions of this
standard, notes are set as enumerated paragraphs in a font smaller than the rest of the text. Cross-references
are meant to guide the user to other relevant clauses of the standard. Examples, notes, and cross-references
are not part of the definition of the language.
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.

IEEE 1076-2002(E) IEEE
LANGUAGE REFERENCE MANUAL Std 1076-2002
1. Design entities and configurations
The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design
that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent
an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in
between. A configuration can be used to describe how design entities are put together to form a complete
design.
A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the
whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external
block that resides in a library and may be used as a component of other designs. Nested blocks in the hierar-
chy are internal blocks, defined by block statements (see 9.1).
A design entity may also be described in terms of interconnected components. Each component of a design
entity may be bound to a lower-level design entity in order to define the structure or behavior of that
component. Successive decomposition of a design entity into components, and binding those components to
other design entities that may be decomposed in like manner, results in a hierarchy of design entities
representing a complete design. Such a collection of design entities is called a design hierarchy. The
bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in
the hierarchy.
This clause describes the way in which design entities and configurations are defined. A design entity is
defined by an entity declaration together with a corresponding architecture body. A configuration is defined
by a configuration declaration.
1.1 Entity declarations
An entity dec
...