VHDL Register Transfer Level (RTL) synthesis

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

General Information

Status
Withdrawn
Publication Date
18-Jul-2005
Withdrawal Date
03-Aug-2010
Drafting Committee
Current Stage
WPUB - Publication withdrawn
Completion Date
04-Aug-2010
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IEC 62050:2005 - VHDL Register Transfer Level (RTL) synthesis Released:7/19/2005 Isbn:2831880386
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INTERNATIONAL IEC
STANDARD 62050
First edition
2005-07
IEEE

1076.6
VHDL Register Transfer Level (RTL) synthesis

Reference number
IEC 62050(E):2005
IEEE Std. 1076.6(E):2004
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INTERNATIONAL IEC
STANDARD 62050
First edition
2005-07
IEEE

1076.6
VHDL Register Transfer Level (RTL) synthesis

© IEEE 2005  Copyright - all rights reserved
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by the Institute of Electrical and Electronics Engineers, Inc.
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
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International Electrotechnical Commission
Международная Электротехническая Комиссия

– 2 – IEC 62050:2005(E)
IEEE 1076.6-2004(E)
CONTENTS
FOREWORD . 3

IEEE Introduction . 6

1. Overview. 9

1.1 Scope. 9
1.2 Compliance to this standard. 9

1.3 Terminology. 10

1.4 Conventions . 10

2. References.11

3. Definitions and acronyms .11
3.1 Definitions .11
3.2 Acronyms.12
4. Predefined types.13
5. Verification methodology .13
5.1 Combinational verification .14
5.2 Sequential verification .14
6. Modeling hardware elements.15
6.1 Edge-sensitive sequential logic.15
6.2 Level-sensitive sequential logic.27
6.3 Three-state logic and busses . 31
6.4 Combinational logic. 31
6.5 ROM and RAM memories.32
7. Pragmas.37
7.1 Attributes . 37
7.2 Metacomments. 54
8. Syntax . 55
8.1 Design entities and configurations. 55
8.2 Subprograms and packages. 60
8.3 Types. 64
8.4 Declarations . 69
8.5 Specifications. 75
8.6 Names . 77
8.7 Expressions . 79

8.8 Sequential statements. 83
8.9 Concurrent statements. 89
8.10 Scope and visibility. 94
8.11 Design units and their analysis . 95
8.12 Elaboration. 96
8.13 Lexical elements . 96
8.14 Predefined language environment . 96
Annex A (informative) Syntax summary. 99
Annex B (normative) Synthesis package RTL_ATTRIBUTES.118
Annex C (informative) List of Participants.119
Index . 120
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

IEEE 1076.6-2004(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION

___________
VHDL REGISTER TRANSFERT LEVEL (RTL) SYNTHESIS

FOREWORD
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International Standard IEC/IEEE 62050 has been processed through IEC technical
committee 93: Design automation.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1076.6 (2004) 93/212/FDIS 93/217/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

This publication has been drafted in accordance with the ISO/IEC Directives.
The committee has decided that the contents of this publication will remain unchanged
until 2009.
“Attention!
It should be noted that this International Standard IEC 62050 is totally unrelated to
IEC/PAS 62050 despite the identical numbering.”
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

– 4 – IEC 62050:2005(E)
IEEE 1076.6-2004(E)
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