IEC TR 61191-8:2021

IEC TR 61191-8 ®
Edition 1.0 2021-03
TECHNICAL
REPORT
colour
inside
Printed board assemblies –
Part 8: Voiding in solder joints of printed board assemblies for use in automotive
electronic control units – Best practices

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IEC TR 61191-8 ®
Edition 1.0 2021-03
TECHNICAL
REPORT
colour
inside
Printed board assemblies –
Part 8: Voiding in solder joints of printed board assemblies for use in automotive

electronic control units – Best practices

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-9575-5

– 2 – IEC TR 61191-8:2021  IEC 2021
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Technical background of voiding in solder joints and potential impact on assembly
reliability . 8
4.1 Void categories . 8
4.2 Void occurrence in surface-mount technology solder joints . 11
4.3 Influence of voiding on solder joint performance . 14
4.3.1 Introductory remarks . 14
4.3.2 Thermomechanical reliability . 15
4.3.3 Mechanical reliability . 17
4.3.4 Thermal functionality . 18
4.3.5 Electrical functionality . 19
5 Determination of voiding levels in solder joints . 20
5.1 Instrumentation available for investigation of voiding in solder joints . 20
5.1.1 General . 20
5.1.2 X-ray inspection equipment operating in two-dimensional mode. 20
5.1.3 X-ray inspection equipment operating in three-dimensional mode . 21
5.2 Challenges for the X-ray inspection of voiding: two case studies . 22
5.2.1 Influence of shadowing effects on measuring reproducibility – first
results for 3D X-ray inspection equipment . 22
5.2.2 Influence of X-ray parameters . 23
5.2.3 Manual determination of voiding levels in solder joints in sample
production . 24
6 Recommendations for sample qualification . 25
7 Recommendations for mass production . 26
7.1 General remarks . 26
7.2 Ramp-up quality assurance for voiding . 26
7.3 X-ray sampling inspection . 26
7.3.1 General . 26
7.3.2 Control limits . 26
7.3.3 Exceeding the control limits . 26
7.4 Process control without X-ray sampling inspection . 27
Annex A (informative) Types of voids and guidelines for acceptability . 28
A.1 Types of voids – Summary . 28
A.2 Typical voiding levels of components and guidelines for acceptability . 29
A.2.1 General . 29
A.2.2 Ball-grid array (BGA) components with collapsing balls . 30
A.2.3 Bottom-termination components involving a lead-frame construction, as
quad-flat no lead packages, dual-flat no lead packages . 30
A.2.4 Exposed pads of components with gull wing solder joints as quad-flat
packages . 31
A.2.5 Transistors with thermal plane as D2PAK and TOLL (TO lead-less) . 31
A.2.6 Rectangular or square end chip components (2, 3 or 5 side
terminations) . 32

A.2.7 Light-emitting diodes . 32
A.3 Further components currently under discussion . 32
A.4 Tabular summary . 32
Bibliography . 34

Figure 1 – Example of inclusion/macro void . 8
Figure 2 – Example of design induced void . 9
Figure 3 – Example of shrinkage void . 9
Figure 4 – Example of planar micro voids . 10
Figure 5 – Example of intermetallic voids . 10
Figure 6 – Example of pinholes . 11
Figure 7 – Example of blowhole voids . 11
Figure 8 – Theoretical model for voiding behaviour of preballed components . 12
Figure 9 – Online X-ray images and trend of void level during melting phase . 13
Figure 10 – Principal influencing parameters affecting solder joint reliability . 14
Figure 11 – Correlation of BGA lifetime with average and maximum void levels . 16
Figure 12 – Correlation void level standoff chip resistor 1206 and shear force after TC. 17
Figure 13 – Sketch of heat transfer with exposed pad solder joints . 18
th
Figure 14 – Calculation of void influence within exposed pads on overall R . 19
Figure 15 – Average voiding results for different shadowing conditions . 22
Figure 16 – Gauge reproducibility of void measurement with different shadowing . 23
Figure 17 – Void measurement of BGA region with varying X-ray parameters . 24

Table A.1 – Types of voids with indication of root cause, occurrence in automotive
electronic assemblies, detectability, effect on thermomechanical reliability, thermal and
electrical function and overall assessment . 28
Table A.2 – Recommendations for acceptable minimum solder coverage or maximum
void level as well as ranges for process indicators . 33

– 4 – IEC TR 61191-8:2021  IEC 2021
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
PRINTED BOARD ASSEMBLIES –
Part 8: Voiding in solder joints of printed board assemblies
for use in automotive electronic control units – Best practices

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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The main task of IEC technical committees is to prepare International Standards. However, a
technical committee may propose the publication of a technical report when it has collected
data of a different kind from that which is normally published as an International Standard, for
example "state of the art".
IEC TR 61191-8, which is a technical report, has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this technical report is based on the following documents:
DTR Report on voting
91/1665/DTR 91/1689/RVDTR
Full information on the voting for the approval of this technical report can be found in the report
on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

A list of all parts in the IEC 61191 series, published under the general title Printed board
assemblies, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

– 6 – IEC TR 61191-8:2021  IEC 2021
INTRODUCTION
This document applies to electronic and electromechanical automotive printed board
assemblies and describes current best-practices for dealing with voiding in solder joints of
surface-mount components soldered onto printed boards.
This document is an informative document which serves to illustrate the technically feasible
options and to provide a basis for customer and supplier discussions and agreements. It is not
intended to be regarded as a specification or standard.
Related standards are gathered in the bibliography.
This document has been prepared based on material provided by the working group DKE
AK682.0.7 (Assembly and interconnect technology in automotive electronics).

PRINTED BOARD ASSEMBLIES –
Part 8: Voiding in solder joints of printed board assemblies
for use in automotive electronic control units – Best practices

1 Scope
This part of IEC 61191 gives guidelines for dealing with voiding in surface-mount solder joints
of printed board assemblies for use in automotive electronics. This technical report focuses
exclusively on voids in solder joints connecting packaged electronic or electromechanical
components with printed boards (PBs). Voids in other solder joints (e.g. in a joint between a
silicon die and a substrate within an electronic component, solder joints of through-hole
components, etc.) are not considered. The technical background for the occurrence of voids in
solder joints, the potential impact of voiding on printed board assembly reliability and
functionality, the investigation of voiding levels in sample- and series-production by use of X-ray
inspection as well as typical voiding levels in different types of solder joints are discussed.
Recommendations for the control of voiding in series production are also given.
Annex A collects typical voiding levels of components and recommendations for acceptability.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194 and the
following apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
design authority
individual, organization, company, contractually designated authority, or agency responsible for
the design of electrical / electronic hardware, having the authority to define variations or
restrictions to the requirements of applicable standards, i.e., the originator/custodian of the
applicable design standard and the approved or controlled documentation
3.2
manufacturer
individual, organization, or company responsible for the assembly process and verification
operations
– 8 – IEC TR 61191-8:2021  IEC 2021
3.3
preballed component
component delivered with solder balls attached, as ball-grid arrays
3.4
solder coverage
ratio of the overlapping area between parallel and wettable surfaces of printed board and
component termination covered with a vertically continuous layer of solder divided by the total
overlapping area between parallel and wettable surfaces of printed board and component
termination
Note 1 to entry: Voids and empty space are not part of the vertically continuous layer of solder and therefore do
not contribute to the solder coverage.
3.5
user
individual, organization, company or agency responsible for the procurement of
electrical/electronic hardware, and having the authority to define any variation or restrictions to
the requirements of applicable standards, i.e., the originator/custodian of the contract detailing
these requirements
4 Technical background of voiding in solder joints and potential impact on
assembly reliability
4.1 Void categories
Different categories of voids exist (see also Annex A). Those are illustrated in Figure 1 to
Figure 7:
a) Inclusions / macro voids (type I)
Voids generated by the evolution of volatiles during the reflow process when the solder is
molten. The sources of volatiles are fluxes and solder paste, absorbed moisture in laminates
or resulting from oxide reduction during the flux reaction. See Figure 1 for an example.

Figure 1 – Example of inclusion/macro void
b) Design induced voids, (type II)
Voids generated due to the presence of microvia(s) in the land pattern (via in pad design).
During reflow, the microvia traps the volatile gases and prevents them from escaping from
the solder joint. See Figure 2 for an example.

Figure 2 – Example of design induced void
c) Shrinkage voids (type III)
Voids caused by the reduction in solder volume when the solder is in the process of
solidification from liquid to solid. See Figure 3 for an example.

Figure 3 – Example of shrinkage void
d) Planar micro voids (type IV)
Small voids (typically < 20 µm in diameter) residing substantially at the interface between
PB land or component termination and solder; this type of voiding is sometimes also known
as "champagne voids". See Figure 4 for an example.

– 10 – IEC TR 61191-8:2021  IEC 2021

Figure 4 – Example of planar micro voids
e) Intermetallic micro voids (type V)
Voids formed within intermetallic layers, between base metal and component termination,
due to organic impurities in the Cu during electroplating. See Figure 5 for an example.

Figure 5 – Example of intermetallic voids
f) Pinhole micro voids (type VI)
Micron-sized voids within the intermetallic compound (IMC), between the IMC and the PB
Cu land or (rarely) close to the IMC in the solder; these are due to an unstable plating
process, which can lead to chemicals becoming entrapped during the PB fabrication process.
See Figure 6 for an example.
Figure 6 – Example of pinholes
g) Blowholes (type VII)
Voids caused by escaping gaseous flux residues, characterized by a hole in the surface of
the solder that is connected with a sub-surface cavity. See Figure 7 for an example.

Figure 7 – Example of blowhole voids
4.2 Void occurrence in surface-mount technology solder joints
Voiding in solder joints is primarily caused by outgassing of entrapped flux volatiles in molten
solder and the presence of oxides and contaminants on the PB and/or component surfaces that
inhibit wetting during the reflow soldering process. Based on the results of most void
investigations, it is generally accepted that the most relevant parameters that influence void
formation are: solder paste flux chemistry, the cleanliness of PB and component surfaces, the
time it takes for the solder powder to coalesce during reflow versus the time it takes for
eliminating the metallization oxide(s), paste type (grain size) and, in combination with paste,
also the temperature profile of the reflow soldering process. Based on the reflow profile, if the
paste coalesces much sooner than the substrate oxide removal at reflow, the flux can adhere
to the surface of the substrate oxide (an immobile phase) and become entrapped in the molten
solder. Consequently, this entrapped flux will serve as an outgassing source and will constantly
release vapour which directly contributes to void formation. The void content also decreases
___________
Reproduced from Aspandiar, R., Voids in Solder Joints, Presentation made at the SMTAI 2006 Conference, with
the permission of the author.
– 12 – IEC TR 61191-8:2021  IEC 2021
with increasing solderability. With increasing solderability, the substrate oxide can be cleaned
more readily, hence allowing less opportunity for the flux to be entrapped to form voids.
The quality of the surface finish of PBs such as ImSn, OSP, ENIG, ImAg, also plays an important
role. Organic residues on surfaces or inclusions from chemical processes can have a significant
influence, but if cleanliness and the quality of surface finishes of components and PBs are well
controlled, the effect on voiding should be low.
Component surfaces also have a certain impact on voiding behavior, especially if there are
surface defects like cracks or holes within component terminations in combination with
underlying organic layers. Passing of wettability testing (e.g. IEC 60068-2-58 IEC 60068-2-69,
IEC 61189-5-601, J-STD-002, J-STD-003) is mandatory. But good wettability based on these
tests is not necessarily a sufficient indicator for obtaining low void levels. Currently there is no
sensitive generic test for components which can predict the tendency to voiding with acceptable
accuracy.
Note that some of these parameters are not independent of each other, for example, the reflow
profile needs to be adapted to the solder paste flux to control outgassing during the melting
phase.
An important aspect to be considered to limit void levels is the solder paste volume. For
components with different standoff levels, like gullwing components, the solder volume at the
standoff (this can be, for example, the exposed thermal pads for quad flat packages – QFPs)
must be sufficient to fill the whole gap defined by the standoff level. Otherwise the solder joint
will either not cover the whole wettable area or form large voids. In addition to the total solder
paste volume, the geometry of the stencil apertures also plays a role. In general, separating a
given total volume of solder paste in smaller printed areas tends to reduce voiding levels.
One additional topic to be considered is the non-uniform behaviour of void formation with
different types of components, especially preballed components, area-array components with
solder balls, versus standard SMT components like chip capacitors and QFPs. For standard
solder joints, higher wetting performance of the solder surfaces generally reduces voiding. This
can be explained by a lower chance of flux residues remaining on the PB or termination surfaces
during the soldering process, acting as potential void sources. Another case is the voiding for
area-array components with solder balls. For such components, higher wetting performance
generally results in higher voiding levels. This phenomenon can be explained by a simple model,
as shown in Figure 8.
Figure 8 – Theoretical model for voiding behaviour of preballed components

The assumption is that there is some kind of more or less stable “skin” of the BGA ball, which
could be an oxidation layer or some phase separation effect at the ball surface. This “skin” is
stable during the reflow process until it is penetrated by thermal convection, wetting forces or
flux activity. Up to this moment of penetration, all gaseous products forming within the solder
paste pass along the ball and will easily leave the solder joint. As soon as the skin is cracked,
a significant share of rising gases can enter the ball and voids are captured within. The cracking
is accelerated by a higher temperature gradient or higher wetting performance resulting in a
higher final void content of the solder joint.
Since this behaviour of preballed components is different from standard SMT components, a
general void reduction strategy for panels with mixed component spectrum is limited. In these
cases, void reduction for one component can increase void level for others. A reasonable
compromise for the whole assembly needs to be sought.
Similarly, a higher peak temperature typically results in higher voiding levels for preballed
components, whereas the opposite trend is generally found for other SMT components such as
QFPs.
An additional factor for void formation of area-array components is the use of high density
interconnect PB technology. In case of microvia in pad designs, so-called design induced
voiding can occur.
All these findings show that voiding can be reduced to a certain level, but not reduced to zero
with standard convection reflow processes. But if material and process parameters can be kept
stable, the variation of average void level can also be kept under control, since the sensitivity
of void level to process parameters was found to not be very high.
When voiding levels in solder joints are analyzed, it turns out that typically a rather wider scatter
of voiding levels are observed, even for the same joints (i.e. joints at the same layout positions)
investigated on a set of printed board assemblies of a certain type. This can be understood as
follows: online X-ray analysis during reflow processes has shown that void formation during
reflow is a quite dynamic process. Voids are generated, grow and, upon reaching a certain
critical size where the voids touch the outer surface of a solder joint, they escape from the
solder joint. A few seconds later new voids are forming, often at the same location from flux
residues not visible in X-ray inspection. This process can be observed using online X-ray
analysis like the images of open solder pads in Figure 9. Thus, the void level in a solder joint
during the melting phase of a reflow process can look like an irregular saw-tooth cycle.

Figure 9 – Online X-ray images and trend of void level during melting phase

– 14 – IEC TR 61191-8:2021  IEC 2021
For the final state of solder joints, this mechanism implies that the overall average void level
can be quite stable, but the void level distribution between different solder joints can exhibit
considerable scatter.
4.3 Influence of voiding on solder joint performance
4.3.1 Introductory remarks
Most voiding concerns concentrate on reliability issues related to the thermomechanical,
mechanical, thermal and electrical performance of solder joints. The reliability assessment is
difficult since solder-joint reliability is a highly complex and multi-faceted topic. Specific types
of voids can reduce the lifetime of solder joints under certain loads, thus having a detrimental
effect on the reliability of components and therefore products (as shown below). In the context
of solder joint reliability, many parameters like materials, surfaces and process parameters,
including voiding, influence solder joint formation as well as solder joint reliability. As solder
joint reliability is the primary target and void formation is only a problem if it reduces reliability
of the assembly, void reduction only makes sense in case it leads to increased reliability.

Figure 10 – Principal influencing parameters affecting solder joint reliability
Figure 10 demonstrates the complexity of the subject. On the left side, the principle of reliability
is illustrated. Stress profiles and strengths of design elements have to be adjusted to each other,
not only on the product level, but likewise also on more detailed levels like the PB, electrical
component, solder joint and grain structure. For all practical cases, load levels should be lower
than load capacities of design elements, even respecting statistical distributions.
The strength of solder joints on the right side is influenced by many parameters like PB materials
and build-up, component materials and quality, solder paste, process and machine parameters,
general and individual solder joint geometry and solder joint microstructure. Voiding is only one
parameter out of the solder joint geometry parameters. Voiding is influenced by many other
parameters like solder paste or component termination, as explained previously. The main
parameters influencing void level are underlined in this Figure 10.

It is important to understand that the overall assembly reliability is also a multi-faceted topic:
An assembly has to demonstrate satisfactory performance under all relevant internal and
environmental loads. As an example, an optimization focusing exclusively on voiding levels in
solder joints can result in the use of a solder flux generating residues which are detrimental for
the electrochemical reliability of the assembly at elevated temperature and humidity. In such a
complex system, a reduction of voiding does not generally enhance the overall assembly
reliability. An optimization of voiding levels alone does not necessarily assure the best overall
assembly reliability, which should be the main target. Nevertheless, reduction of voiding levels
in solder joints is generally aspired to, providing there is no detrimental effect on the reliability
of the overall assembly from the actions needed to reduce the voiding.
4.3.2 Thermomechanical reliability
Since voiding affects the solder joint geometry and microstructure, and interacts with crack
propagation, it also has an impact on thermomechanical solder joint reliability. For most types
of solder joints, preferred crack paths during temperature cycling of boards can be identified.
Especially if voids are positioned within these critical paths, the stability against cracking can
be reduced as specific types of voids can accelerate the crack propagation and weaken the
solder joint stability. This highlights that in addition to its size, the location of a void can have a
pronounced effect on its effect on reliability. On the other hand, voids can increase the flexibility
of solder joints and improve reliability, at least locally, for certain solder-joint geometries, e.g.
for BGA solder joints. The overall effect on solder joint reliability is difficult to assess, especially
for components with multiple solder joints like BGAs or QFPs. For these components
interactions between the solder joints also have to be taken into account. For example, voids
in one solder joint can increase flexibility of that joint but can also partially transfer stress to
neighboring solder joints.
The effect of voids on solder joint reliability has been studied by FEM simulation in various
investigations, mainly for BGA components. Positive as well as negative effects of voids on
solder joint reliability, mainly depending on size and positions of voids within the ball, have been
reported. But most of them try to identify a direct correlation between void rate and crack
behavior within single balls. Only few examine the interactions between different solder joints.
Simulations are mainly facing two limitations:
• a suitable model for crack propagation within solder joints or BGA balls is missing, which
would be required to judge the exact influence of voids on this crack propagation process;
• the accuracy of stress level comparison between balls with different geometry (here void
content) is very limited with available simulations models.
Since voiding effect on thermomechanical reliability is difficult to assess only by theoretical
simulations, some experimental evaluations have been done and reported in literature.
Independent of the limitations discussed above, the two main conclusions that can be obtained
from literature (Hillman et al. 2011, Holle et al. 2018) for BGA voiding are:
• the effect of < 30 % void level is generally rated as insignificant for area-array components;
• the effect of voids on solder joint reliability is strongly depending on the location of the voids,
i.e. their relative positions with respect to a potential crack path.
Due to the great amount of effort that is involved in these investigations, they are concentrated
on the components that are seen as the most critical concerning both thermomechanical
reliability and void level. General experience shows that three groups of components can be
selected as the most challenging:
• BGA
• Chip components (resistors or capacitors)
• Bottom-terminated components like QFNs (quad-flat no lead packages), SON (small-outline
no lead), etc.
– 16 – IEC TR 61191-8:2021  IEC 2021
For these groups, some experimental evaluations can be reported in addition to theoretical
studies. In one study (Holle et al. 2018) the TC lifetime of BGA416 (pitch 1,0) with normal and
intentionally increased voiding has been compared. Lifetime in this study is the time until
electrical failure during online measurement with temperature cycling between −40 °C and
+125 °C (see Figure 11).
Figure 11 – Correlation of BGA lifetime with average and maximum void levels
These results confirm the conclusion of theoretical studies that maximum voiding, even
exceeding 30 %, is not significantly affecting reliability. This result also confirms the current
limit for BGA voiding adopted in different standards (see, for example, IPC-A-610, J-STD-001,
IEC 61191-2). The second important finding from this investigation is the high variation of
lifetime values independent of maximum void level. This effect is confirming the general remark
at the beginning of this chapter that voiding is only one effect, maybe only a minor one, on
solder joint reliability. To some extent the reason for this variation might also be that detailed
void positions are not taken into account with this integral consideration, but this direct
correlation between void position and reliability of a component is almost not possible on an
experimental level due to the high complexity of interactions.
For the other two component types there are only a few investigations reported in literature.
One result from the same study shows the shear force performance of soft terminated 1206
chip resistor solder joints after different levels of temperature cycling −40 °C/+125 °C
(see Figure 12, Holle et al. 2018). For the components in this study, the void level within the
standoff area was highly variable due to a component specific termination outgassing issue.

Figure 12 – Correlation void level standoff chip resistor 1206 and shear force after TC
This evaluation shows that independent of TC level, the shear force is almost not affected by
void level. The conclusion from this result is that the void level does not affect
thermomechanical lifetime performance significantly up to about 35 % void level in the standoff
area. This result is primarily valid for voids in the standoff area due to a different cracking
behavior of the meniscus. But in most cases, especially for standard SnAgCu solder alloys, the
void rate within the meniscus is normally rather low.
For bottom terminated components (BTC) currently only very limited data is available but
investigations within different institutions are ongoing. Thus, additional results can be added
later. A very rigorous recent study focused on how board design (i.e. vias) affect the formation
of voids and whether the presence of voids in the thermal pad impacts the solder joint reliability
of the signal interconnect. For the tested components, this study concluded that the magnitude
of voiding at the thermal pad does not affect the reliability (Hillman et al., 2019).
As an overall conclusion for the effect of voiding on thermomechanical reliability, voiding can
have a negative influence on TC reliability if certain threshold levels are exceeded. Those
thresholds are depending on component type. Below such thresholds, the thermomechanical
reliability is largely independent of the voiding level.
4.3.3 Mechanical reliability
Influence of voids on mechanical solder joint reliability under vibration, drop, or shock load is
not investigated very deeply. Thus, at this place only general assessments based on long term
field experience can be reported: Based on field experience, mechanical loads are not generally
expected to result in failures related to voiding in solder joints.
For chip components, at least up to 1206 size and also multi-pin components, there is no
negative effect of voiding seen, because these components are not critical concerning
mechanical load. Some potential risks are seen for 2 groups of components:

– 18 – IEC TR 61191-8:2021  IEC 2021
• heavy components (electrolytic capacitors, SMD coils, chokes, shunts, etc. ) with small pin
count (< 4). In these cases, voids could be relevant for shock/drop reliability due to high
shear force load during mechanical impact;
• area-array components with low standoff and a high number of solder joints like
LGA > 2 x 2 cm and castellation modules. For these cases, bending induced failures could
be relevant with voids playing a role.
Due to limited experience and knowledge about void influence on drop, shock, and vibration
performance, deeper investigations are recommended, but only in case of exceptionally high
requirements concerning mechanical loads.
4.3.4 Thermal functionality
Another concern, in the context of voiding, is a potential heat transfer reduction for large thermal
pads, referred to as exposed pads. Within these large area solder joints, void content is normally
significantly higher than in small standard I/O solder joints. The voiding in such solder joints
reduces the area with a connection between the exposed pad of the components and the PB
land (called "soldered area"). A relative percentage of soldered area can be calculated by taking
the ratio of the area with a vertically continuous solder connection between exposed pad and
PB land with respect to the total wettable area (i.e. area where the exposed pad of the
component is overlapping with open Cu on the PB). This ratio is also called solder coverage.
The range that can usually be found with standard production parameters is between 90 % and
50 %, sometimes down to approximately 40 % solder coverage. The influence of the reduction
in soldered area on overall thermal resistivity can be calculated.

Figure 13 – Sketch of heat transfer with exposed pad solder joints
A sketch of the simplified model behind this calculation is shown in Figure 13. The overall heat
resistivity between component surface and heat sink or housing surface on the other PB side
is calculated for the whole exposed pad area.
For the model illustrated in Figure 13, the influence of voiding on vertical thermal resistivity of
solder joint plus PB is illustrated in Figure 14. Since via filling can reduce the thermal resistance
of the PB and enhance the influence of voids, this effect was also considered.

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Figure 14 – Calculation of void influence within exposed pads on overall R
This calculation clearly shows that the solder joints of exposed pads on standard PBs are not
sensitive to voiding down to a soldered area of about 20 % or even 10 %. The main bottleneck
for heat transfer is the PB with the plated through holes, and not the exposed-pad solder joint,
even if a high number of thermal vias is supporting the vertical transfer of heat through the PB.
Solder filling of thermal vias also does not change the situation substantially.
The influence of voiding within exposed pads on solder-j
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