31.080.30 - Transistors
ICS 31.080.30 Details
Transistors
Transistoren
Transistors
Tranzistorji
General Information
Frequently Asked Questions
ICS 31.080.30 is a classification code in the International Classification for Standards (ICS) system. It covers "Transistors". The ICS is a hierarchical classification system used to organize international, regional, and national standards, facilitating the search and identification of standards across different fields.
There are 49 standards classified under ICS 31.080.30 (Transistors). These standards are published by international and regional standardization bodies including ISO, IEC, CEN, CENELEC, and ETSI.
The International Classification for Standards (ICS) is a hierarchical classification system maintained by ISO to organize standards and related documents. It uses a three-level structure with field (2 digits), group (3 digits), and sub-group (2 digits) codes. The ICS helps users find standards by subject area and enables statistical analysis of standards development activities.
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IEC 63505:2025 gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope.
SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI).
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IEC 63275-2:2022 gives the test method and a procedure using this method to evaluate the on-state voltage change, on-state resistance change and reverse drain voltage change of silicon carbide (SiC) power MOSFET devices due to body diode operation. This test is not generally requested for Si power transistors.
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IEC 63284:2022 covers the protocol of performing a stress procedure and a corresponding test method to evaluate the reliability of gallium nitride (GaN) power transistors by inductive load switching, specifically hard-switching stress
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IEC 63275-1:2022 gives a test method to evaluate gate threshold voltage shift of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) using room temperature readout after applying continuous positive gate-source voltage stress at elevated temperature. The proposed method accepts a certain amount of recovery by allowing large delay times between stress and measurement (up to 10 h).
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IEC 62899-503-3:2021(E) specifies a measuring method of contact resistance for printed thin film transistors (TFTs) by the transfer length method (TLM). The method requires the fabrication of a test element group (TEG) with varying channel length (L) between source and drain electrodes. The method is intended for quality assessment of TFT electrode contacts and is suited for determining whether the contact resistance lies within a desired range.
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IEC 60747-8:2010 gives standards for the following categories of field-effect transistors:
- type A: junction-gate type;
- type B: insulated-gate depletion (normally on) type;
- type C: insulated-gate enhancement (normally off) type.
The main changes with respect to the previous edition are listed below.
a) "Clause 3 Classification" was moved and added to Clause 1.
b) "Clause 4 Terminology and letter symbols" was divided into "Clause 3 Terms and definitions" and "Clause 4 Letter symbols" was amended with additions and deletions.
c) Clause 5, 6 and 7 were amended with necessary additions and deletions.
This publication is to be read in conjunction with IEC 60747-1:2006.
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IEC 62373-1:2020 provides the measurement procedure for a fast BTI (bias temperature instability) test of silicon based metal-oxide semiconductor field-effect transistors (MOSFETs).
This document also defines the terms pertaining to the conventional BTI test method.
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IEC 62899-503-1:2020(E) specifies a test method for displacement current measurement (DCM) for printed thin film transistors (TFTs) or organic thin film transistors (OTFTs).
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IEC 60747-9:2019 specifies product specific standards for terminology, letter symbols, essential ratings and characteristics, verification of ratings and methods of measurement for insulated-gate bipolar transistors (IGBTs).
This third edition includes the following significant technical changes with respect to the previous edition:
reverse-blocking IGBT and its related technical contents have been added;
reverse-conducting IGBT and its related technical contents have been added;
some parts of the previous edition have been amended, combined or deleted.
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IEC 60747-7:2010 gives the requirements applicable to the following sub-categories of bipolar transistors excluding microwave transistors.
- Small signal transistors (excluding switching and microwave applications);
- Linear power transistors (excluding switching, high-frequency, and microwave applications);
- High-frequency power transistors for amplifier and oscillator applications;
- Switching transistors for high speed switching and power switching applications;
- Resistor biased transistors. The main changes with respect to previous edition are listed below.
a) Clause 1 was amended by adding an item that should be included.
b) Clauses 3, 4, 5, 6 and 7 were amended by adding terms, definitions, suitable additions and deletions those should be included.
c) The text of the second edition was combined with that of IEC 60747-7-5.
This publication is to be read in conjunction with IEC 60747-1:2006.
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IEC 62416:2010 describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.
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IEC 62416:2010 describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.
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IEC 62417:2010 provides a wafer level test procedure to determine the amount of positive mobile charge in oxide layers in metal-oxide semiconductor field effect transistors. It is applicable to both active and parasitic field effect transistors. The mobile charge can cause degradation of microelectronic devices, e.g. by shifting the threshold voltage of MOSFETs or by inversion of the base in bipolar transistors.
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This part of IEC 60747 gives product specific standards for terminology, letter symbols, essential ratings and characteristics, verification of ratings and methods of measurement for insulated-gate bipolar transistors (IGBTs). The major changes with respect to the previous edition are mainly of an editorial nature.
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Provides requirements for the following categories of discrete devices: variable capacitance diodes and snap-off diodes, mixer diodes and detector diodes, avalanche diodes, gunn diodes,bipolar transistors and field-effect transistors. This second edition cancels and replaces the first edition, published in 1991, its amendments 1, 2 and 3 (1993, 1999 and 2001, respectively), and constitutes a technical revision.
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Provides a test procedure for a bias-temperature (BT) stability test of metal-oxide semiconductor, field-effect transistors (MOSFET)
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Provides a test procedure for a bias-temperature (BT) stability test of metal-oxide semiconductor, field-effect transistors (MOSFET)
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Supersedes CECC 20 004 Issue 2:1987 and A1 * TC 86D disbanded at 105 BT
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Supersedes CECC 20 003 Issue 1:1986 (and A1) * TC 86D disbanded at 105 BT
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Gives product specific standards for terminology, letter symbols, essential ratings and characteristics and measuring methods for insulated-gate bipolar transistors (IGBTs).
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Gives standards for the following categories of discrete devices: variable capacitance diodes and snap-off diodes, mixer diodes and detector diodes, avalanche diodes, gunn diodes, bipolar transistor and field-effet transistors.
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Gives the requirements applicable to the following sub-categories of bipolar transistors: -low power signal transistors (excluding switching applications); -power transistors (excluding switching and high-frequency applications); -high-frequency power transistors for amplifier and oscillator applications; -switching transistors.
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Gives standards for the following categories of field-effect transistors : -Type A: junction-gate type; -Type B: insulated-gate depletion type; -Type C: insulated-gate enhancement type.
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SIGNIFICANCE AND USE
5.1 The electrical properties of gate and field oxides are altered by ionizing radiation. The method for determining the dose delivered by the source irradiation is discussed in Practices E666, E668, E1249, and Guide E1894. The time dependent and dose rate effects of the ionizing radiation can be determined by comparing pre- and post-irradiation voltage shifts, ΔVot and ΔVit. This test method provides a means for evaluation of the ionizing radiation response of MOSFETs and isolation parasitic MOSFETs.
5.2 The measured voltage shifts, ΔVot and ΔVit, can provide a measure of the effectiveness of processing variations on the ionizing radiation response.
5.3 This technique can be used to monitor the total-dose response of a process technology.
SCOPE
1.1 This test method covers the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconductor-field-effect transistor (MOSFET) and an isolation dielectric in a parasitic MOSFET.2,3,4 The subthreshold technique is used to separate the ionizing radiation-induced inversion voltage shift, ΔVINV into voltage shifts due to oxide trapped charge, ΔVot and interface traps, ΔV it. This technique uses the pre- and post-irradiation drain to source current versus gate voltage characteristics in the MOSFET subthreshold region.
1.2 Procedures are given for measuring the MOSFET subthreshold current-voltage characteristics and for the calculation of results.
1.3 The application of this test method requires the MOSFET to have a substrate (body) contact.
1.4 Both pre- and post-irradiation MOSFET subthreshold source or drain curves must follow an exponential dependence on gate voltage for a minimum of two decades of current.
1.5 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.
1.7 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
WITHDRAWN RATIONALE
This test method covered the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconductor-field-effect transistor (MOSFET) and an isolation dielectric in a parasitic MOSFET.
Formerly under the jurisdiction of F01 on Electronics, this test method was withdrawn in November 2023. This standard is being withdrawn without replacement because Committee F01 was disbanded.
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SIGNIFICANCE AND USE
The current gain of a transistor is basic to its operation and is its single most important parameter.
Ionizing radiation, that is, gamma radiation due to a nuclear burst, will degrade the current gain due to lifetime damage in the bulk material. Degradation of gain will be greatest immediately following a burst of ionizing radiation and the gain will rapidly recover to a quasi steady-state value. Defect annealing may continue for weeks but usually the current gain recovery is small or negligible.
This method provides a procedure that does not require special-purpose test equipment.
This method is suitable for use for specification acceptance, service evaluation, or manufacturing control.
SCOPE
1.1 This test method covers the measurement of common-emitter d-c current gain (forward, hFE, or inverted, hFEI) of bipolar transistors, for which the collector-emitter leakage current, ICEO, is less than 10% of the collector current, IC, at which the measurement is to be made, and for which the shunt leakage current in the base circuit is less than 10% of the base current required.
1.2 This test method is suitable for measurement of common-emitter d-c current gain at a single given value of test transistor collector current or over a given range of collector currents (for example, over the range of the transistor to be tested).
1.2.1 The nominal ranges of collector current over which the three test circuits are intended to be used are as follows:
1.2.1.1 Circuit 1, less than 100 [mu]A,
1.2.1.2 Circuit 2, from 100 [mu]A to 100 mA, and
1.2.1.3 Circuit 3, greater than 100 mA.
1.3 This test method incorporates tests to determine if the power dissipated in the transistor is low enough that the temperature of the junction is approximately the same as the ambient temperature.
1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address the safety problems, if any, associated with its use. It is the responsibility of whoever uses this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
WITHDRAWN RATIONALE
This test method covers the measurement of common-emitter dc current gain (forward, hFE, or inverted, hFEI) of bipolar transitors, for which the collector-emitter leakage current, ICEO, is less than 10 % of the collector current, IC, at which the measurement is to be made, and for which the shunt leakage current in the base circuit is less than 10 % of the base current required.
This standard is being withdrawn because it does not have any relevance to Nuclear and Space Effects. This is strictly an electronic document with nothing to do with radiation and should be related to a group that deals strictly with electronics.
Formerly under the jurisdiction of Committee F01 on Electronics, and the direct responsibility of Subcommittee F01.11 on Nuclear and Space Radiation Effects, this test method was withdrawn in June 2011 with no replacement.
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D116/196: TC 217 disbanded * D122/065: Withdrawn
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D114/033: Withdrawn
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D114/033: Withdrawn
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D114/033: Withdrawn
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D114/033: Withdrawn
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SCOPE
1.1 This test method covers the measurement of leakage currents of transistors and diodes. Electronic devices exposed to ionizing radiation may show increases in leakage current as the accumlated total dose rises.
1.2 These procedures are intended for the measurement of currents in the range from 10 -11 to 10 -3 A.
1.3 This test method may be used with either a virtual-ground current meter or a resistance-shunt current meter.
1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this test method.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
WITHDRAWN RATIONALE
This test method covers the measurement of leakage currents of transistors and diodes. Electronic devices exposed to ionizing radiation may show increases in leakage current as the accumulated total dose rises.
Formerly under the jurisdiction of Committee F01 on Electronics, this test method was withdrawn in June 2006 in accordance with section 10.6.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
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SCOPE
1.1 This test method covers the measurement of MOSFET (see Note 1) linear threshold voltage under very low sweep rate or d-c conditions. It is a d-c conductance method applicable in the linear region of MOSFET operation where a drain voltage V D of approximately 0.1 V is typical.
Note 1--MOS is an acronym for metal-oxide semiconductor; FET is an acronym for field-effect transistor.
1.2 This test method is applicable to both enhancement-mode and depletion-mode MOSFETs, and for both silicon-on-insulator (SOI) and bulk-silicon MOSFETs. The test method specifies positive voltage and current conventions specifically applicable to n-channel MOSFETs. The substitution of negative voltage and negative current make the test method directly applicable to p-channel MOSFETs.
1.3 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this test method.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
WITHDRAWN RATIONALE
This test method covers the measurement of MOSFET (see Note 1) linear threshold voltage under very low sweep rate or d-c conditions. It is a d-c conductance method applicable in the linear region of MOSFET operation where a drain voltage VD of approximately 0.1 V is typical.
Note 1-MOS is an acronym for metal-oxide semiconductor, FET is an acronym for field-effect transistor.
Formerly under the jurisdiction of Committee F01 on Electronics, this test method was withdrawn in June 2006 in accordance with section 10.6.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
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This part of IEC 60747 gives requirements for bipolar switching transistors used for power switching application above 1 A. NOTE: Requirements concerning bipolar transistors in general can be found in IEC 60747-7.
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Gives details for the following categories of metal-oxide semiconductor field-effect transistors (MOSFETs) with inverse diodes: type B depletion (normally on) type and Type C enhancement (normally off) type.
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SCOPE
1.1 This test method covers the detection of epitaxial spikes on silicon wafers. It is applicable to any wafer diameter or surface orientation.
1.2 This test method is a pass or fail test for the presence of spikes on a wafer. If there are relatively few spikes and they are not close together the test method can also be used to count spikes.
1.3 For purposes of this test method, a detectable spike is one with a nominal height of 4 [mu]m or more.
1.4 This test method does not have the ability to measure spike heights.
1.5 This test method is ordinarily nondestructive but its use may require subsequent cleaning of the tested wafers.
1.6 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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