SIST
SIST-TP CLC/R217-004:2004
(Main)JESSI 0.8µm CMOS transistor model for analogue and digital circuit simulation
JESSI 0.8µm CMOS transistor model for analogue and digital circuit simulation
D116/196: TC 217 disbanded * D122/065: Withdrawn
Model transistorja JESSI 0.8µm CMOS za simuliranje analognih in digitalnih tokokrogov
General Information
Status
Withdrawn
Publication Date
31-Aug-2004
Withdrawal Date
20-Oct-2009
Technical Committee
Current Stage
9900 - Withdrawal (Adopted Project)
Start Date
20-Oct-2009
Due Date
12-Nov-2009
Completion Date
21-Oct-2009
Standards Content (Sample)
SLOVENSKI STANDARD
SIST-TP CLC/R217-004:2004
01-september-2004
Model transistorja JESSI 0.8µm CMOS za simuliranje analognih in digitalnih
tokokrogov
JESSI 0.8µm CMOS transistor model for analogue and digital circuit simulation
Ta slovenski standard je istoveten z: R217-004:1995
ICS:
31.080.30 Tranzistorji Transistors
SIST-TP CLC/R217-004:2004 en
2003-01.Slovenski inštitut za standa
...
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