29.045 - Semiconducting materials
ICS 29.045 Details
Semiconducting materials
Halbleitende Stoffe
Materiaux semi-conducteurs
Polprevodniški materiali
General Information
Frequently Asked Questions
ICS 29.045 is a classification code in the International Classification for Standards (ICS) system. It covers "Semiconducting materials". The ICS is a hierarchical classification system used to organize international, regional, and national standards, facilitating the search and identification of standards across different fields.
There are 154 standards classified under ICS 29.045 (Semiconducting materials). These standards are published by international and regional standardization bodies including ISO, IEC, CEN, CENELEC, and ETSI.
The International Classification for Standards (ICS) is a hierarchical classification system maintained by ISO to organize standards and related documents. It uses a three-level structure with field (2 digits), group (3 digits), and sub-group (2 digits) codes. The ICS helps users find standards by subject area and enables statistical analysis of standards development activities.
- Corrigendum3 pagesEnglish and French languagee-Library read for1 day
- Corrigendum3 pagesEnglish and French languagee-Library read for1 day
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
- Standard1 pageEnglish and French languagesale 15% off
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
- Standard92 pagesEnglish languagee-Library read for1 day
IEC 62899-203:2024 defines terms and specifies standard methods for characterization and evaluation of semiconductor inks and semiconductive layers that are made from semiconductor inks. This edition includes the following significant technical changes with respect to the previous edition:
a) addition of 6.3.1.2.2 - Normalised on-current measurement of the TFT device;
b) in 6.3.2, correction of formula for calculation of permittivity.
- Standard23 pagesEnglish languagesale 15% off
- Standard47 pagesEnglish languagesale 15% off
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fifth edition introduces four main changes: a) re-edition of the whole standard according to the current directives; b) deletion of safety-related descriptions considering coordination with IEC 62477 series; c) changes of calculation methods of inductive voltage regulation; d) changes considering coordination with IEC 61378 series.
- Standard92 pagesEnglish languagee-Library read for1 day
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
The content of the corrigendum 1 (2025-03) has been included in this copy.
- Standard295 pagesEnglish languagesale 15% off
- Standard182 pagesEnglish and French languagesale 15% off
SIGNIFICANCE AND USE
5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of survivability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1),2 but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Guide7 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
4.1 The electrical behavior of semiconducting extruded shielding materials is important for a variety of reasons, such as safety, static charges, and current transmission. This test method is useful in predicting the behavior of such semiconducting compounds. Also see Test Method D4496.
SCOPE
1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 In common practice the conductor shield is often referred to as the strand shield.
1.3 Technically, this test method is the measurement of a resistance between two electrodes on a single surface and modifying that value using dimensions of the specimen geometry to calculate a resistivity. However, the geometry of the specimen is such as to support the assumption of a current path primarily throughout the volume of the material between the electrodes, thus justifying the use of the term “longitudinal volume resistivity.” (See 3.1.2.1.)
1.4 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see 7.1.
1.6 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Standard3 pagesEnglish languagesale 15% off
IEC 62899-503-3:2021(E) specifies a measuring method of contact resistance for printed thin film transistors (TFTs) by the transfer length method (TLM). The method requires the fabrication of a test element group (TEG) with varying channel length (L) between source and drain electrodes. The method is intended for quality assessment of TFT electrode contacts and is suited for determining whether the contact resistance lies within a desired range.
- Standard13 pagesEnglish languagesale 15% off
ABSTRACT
This specification covers extruded cross linked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables. The materials covered are not compatible with hydro carbon derivatives of a swelling or deteriorating nature. Different tests shall be performed in order to determine physical properties like brittleness, aging requirements, and elongation at rupture and volume resistivity.
SCOPE
1.1 This specification covers crosslinked and thermoplastic extruded semi-conducting, conductor, and insulation shielding materials for electrical wires and cables.
1.2 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
1.3 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Technical specification2 pagesEnglish languagesale 15% off
IEC 62899-503-1:2020(E) specifies a test method for displacement current measurement (DCM) for printed thin film transistors (TFTs) or organic thin film transistors (OTFTs).
- Standard15 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
5.1 Although it would be desirable to measure the extent of profile distortion in any unknown sample by using a standard sample and this guide, measurements of interface width (profile distortion) can be unique to every sample composition (1, 2).4 This guide, describes a method that determines the unique width of a particular interface for the chosen set of operating conditions. It is intended to provide a method for checking on proper or consistent, or both, instrument performance. Periodic analysis of the same sample followed by a measurement of the interface width, in accordance with this guide, will provide these checks.
5.2 The procedure described in this guide is adaptable to any layered sample with an interface between layers in which a nominated element is present in one layer and absent from the other. It has been shown that for SIMS in particular (3, 4) and for surface analysis in general (5, 6), only rigorous calibration methods can determine accurate interface widths. Such procedures are prohibitively time-consuming. Therefore the interface width measurement obtained using the procedure described in this guide may contain significant systematic error (7). Therefore, this measure of interface width may have no relation to similar measures made with other methods. However, this does not diminish its use as a check on proper or consistent instrument performance, or both.
5.3 This guide can be used for both elemental and molecular depth profiles, provided that the materials have constant sputter rates throughout the depth of the overlayer, and minimal interlayer mixing is occurring. For more detailed information regarding measurements of interface widths during organic depth profiling, please see Mahoney (8).
SCOPE
1.1 This guide provides the SIMS analyst with a method for determining the width of interfaces from SIMS sputtering data obtained from analyses of layered specimens (both organic and inorganic). This guide does not apply to data obtained from analyses of specimens with thin markers or specimens without interfaces such as ion-implanted specimens.
1.2 This guide does not describe methods for the optimization of interface width or the optimization of depth resolution.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Guide3 pagesEnglish languagesale 15% off
IEC TR 60146-1-2:2019 gives guidance on variations to the specifications given in IEC 60146-1-1:2009 to enable the specification to be extended in a controlled form for special cases. Background information is also given on technical points, which facilitates the use of IEC 60146-1-1:2009. This technical report primarily covers line commutated converters and is not in itself a specification, except as regards certain auxiliary components, in so far as existing standards may not provide the necessary data. This fifth edition includes the following significant technical changes with respect to the previous edition:
a) addition of annexes concerning the applications of converter transformers and of fuses for overcurrent protection;
b) changes of calculation methods related the inductive voltage regulation and changes of description on transformer losses to be consistent with the latest transformer standards;
c) addition and updates of references based on the latest information.
- Technical report105 pagesEnglish languagesale 15% off
- Technical report215 pagesEnglish languagesale 15% off
IEC 62899-203:2018(E) defines terms and specifies standard methods for characterisation and evaluation. This document is applicable to semiconductor inks and semiconductive layers that are made from semiconductor inks.
- Standard22 pagesEnglish languagesale 15% off
IEC/TR 62572-4:2013(E) which is a technical report, provides guidelines for optical connector end-face cleaning methods for receptacle style optical transceivers. It includes details about handling receptacle style optical transceivers, internal structures of optical transceivers, information on cleaning tools and machines, applicable cleaning methods and cleaning procedures. Receptacle style optical transceivers as well as optical fibre patch cords are handled by operators and maintenance staff of optical network systems. This technical report may be used as a guideline to prepare instruction manuals for the operators and maintenance staff of optical network systems. Keywords: optical connector end-face cleaning methods, receptacle style optical transceivers, optical network systems.
- Technical report23 pagesEnglish languagesale 15% off
- Technical report23 pagesEnglish languagesale 15% off
IEC 60146-1-1:2009 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of a.c. power to d.c. power or vice versa. Parts of this standard are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fourth edition constitutes a technical revision and introduces five main changes: - re-edition of the whole standard according to the current directives; - correction of definitions and addition of new terms, especially terms concerning EMC, harmonic distortion and insulation co-ordination; - the service condition tolerances have been revised according to the IEC 61000 series; - the insulation tests have been revised considering the insulation co-ordination; - addition of three annexes.
- Standard99 pagesEnglish languagee-Library read for1 day
IEC 60146-1-2:2011(E) gives guidance on variations to the specifications given in IEC 60146-1-1:2009 to enable the specification to be extended in a controlled form for special cases. Background information is also given on technical points which should facilitate the use of IEC 60146-1-1:2009. This technical report primarily covers line commutated converters and is not in itself a specification, except as regards certain auxiliary components, in so far as existing standards may not provide the necessary data. This fourth edition includes the following main changes with respect to the previous edition:
a) re-edition of the whole document according to the current Directives;
b) correction of some errors.
- Technical report83 pagesEnglish languagesale 15% off
IEC 60146-1-1:2009 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of a.c. power to d.c. power or vice versa. Parts of this standard are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fourth edition constitutes a technical revision and introduces five main changes:
- re-edition of the whole standard according to the current directives;
- correction of definitions and addition of new terms, especially terms concerning EMC, harmonic distortion and insulation co-ordination;
- the service condition tolerances have been revised according to the IEC 61000 series;
- the insulation tests have been revised considering the insulation co-ordination;
- addition of three annexes.
- Standard189 pagesEnglish and French languagesale 15% off
Specifies the requirements for the performance of all electronic power convertors and electronic power switches using controllable and/or non-controllable electronic valves. Specifies the requirements applicable to line commutated convertors for conversion of a.c. power to d.c. power or vice versa including tests and service conditions which influence the basis of rating. The contents of the corrigendum of August 1993 have been included in this copy.
- Standard10 pagesEnglish and French languagesale 15% off
SIGNIFICANCE AND USE
4.1 In order to choose the proper material for producing semiconductor devices, knowledge of material properties such as resistivity, Hall coefficient, and Hall mobility is useful. Under certain conditions, as outlined in the Appendix, other useful quantities for materials specification, including the charge carrier density and the drift mobility, can be inferred.
SCOPE
1.1 These test methods cover two procedures for measuring the resistivity and Hall coefficient of single-crystal semiconductor specimens. These test methods differ most substantially in their test specimen requirements.
1.1.1 Test Method A, van der Pauw (1) 2—This test method requires a singly connected test specimen (without any isolated holes), homogeneous in thickness, but of arbitrary shape. The contacts must be sufficiently small and located at the periphery of the specimen. The measurement is most easily interpreted for an isotropic semiconductor whose conduction is dominated by a single type of carrier.
1.1.2 Test Method B, Parallelepiped or Bridge-Type—This test method requires a specimen homogeneous in thickness and of specified shape. Contact requirements are specified for both the parallelepiped and bridge geometries. These test specimen geometries are desirable for anisotropic semiconductors for which the measured parameters depend on the direction of current flow. The test method is also most easily interpreted when conduction is dominated by a single type of carrier.
1.2 These test methods do not provide procedures for shaping, cleaning, or contacting specimens; however, a procedure for verifying contact quality is given.
Note 1: Practice F418 covers the preparation of gallium arsenide phosphide specimens.
1.3 The method in Practice F418 does not provide an interpretation of the results in terms of basic semiconductor properties (for example, majority and minority carrier mobilities and densities). Some general guidance, applicable to certain semiconductors and temperature ranges, is provided in the Appendix. For the most part, however, the interpretation is left to the user.
1.4 Interlaboratory tests of these test methods (Section 19) have been conducted only over a limited range of resistivities and for the semiconductors, germanium, silicon, and gallium arsenide. However, the method is applicable to other semiconductors provided suitable specimen preparation and contacting procedures are known. The resistivity range over which the method is applicable is limited by the test specimen geometry and instrumentation sensitivity.
1.5 The values stated in acceptable metric units are to be regarded as the standard. The values given in parentheses are for information only. (See also 3.1.4.)
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
1.7 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
WITHDRAWN RATIONALE
These test methods covered two procedures for measuring the resistivity and Hall coefficient of single-crystal semiconductor specimens.
Formerly under the jurisdiction of Committee F01 on Electronics, these test methods were withdrawn in November 2023. This standard is being withdrawn without replacement because Committee F01 was disbanded.
- Standard14 pagesEnglish languagesale 15% off
- Standard14 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
4.1 Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.
4.2 This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.Note 2—The practice may be extended to infer the survivability of untested metallization adjacent to the specimen metallization on a semiconductor die or wafer if care is taken that appropriate similarities exist in the design and fabrication variables.
SCOPE
1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration. Note 1—In this practice, “metallization” refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term “burnout” refers to either fusing or vaporization.
1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.
1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.
1.4 This practice is not intended to determine the nature of any defect causing failure.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
WITHDRAWN RATIONALE
This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.
Formerly under the jurisdiction of Committee F01 on Electronics, this practice was withdrawn in January 2022 in accordance with section 10.6.3 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
- Standard5 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
This test method can be used to ensure absolute reproducibility of WSix film deposition systems over the course of many months. The time span of measurements is essentially the life of many process deposition systems.
This test method can be used to qualify new WSix deposition systems to ensure duplicability of existing systems. This test method is essential for the coordination of global semiconductor fabrication operations using different analytical services. This test method allows samples from various deposition systems to be analyzed at different sites and times.
This test method is the chosen calibration technique for a variety of analytical techniques, including, but not limited to:
Electron spectroscopy for chemical analysis (ESCA or XPS),
Auger electron spectroscopy (AES),
Fourier transform infrared red spectroscopy (FTIR),
Secondary ion mass spectrometry (SIMS), and
Electron dispersive spectrometry (EDS) and particle induced x-ray emission (PIXE).
SCOPE
1.1 This test method covers the quantitative determination of tungsten and silicon concentrations in tungsten/silicon (WSix) semiconductor process films using Rutherford Backscattering Spectrometry (RBS). (1) This test method also covers the detection and quantification of impurities in the mass range from phosphorus Å (31 atomic mass units (amu) to antimony (122 amu).
1.2 This test method can be used for tungsten silicide films prepared by any deposition or annealing processes, or both. The film must be a uniform film with an areal coverage greater than the incident ion beam (∼2.5 mm).
1.3 This test method accurately measures the following film properties: silicon/tungsten ratio and variations with depth, tungsten depth profile throughout film, WSix film thickness, argon concentrations (if present), presence of oxide on surface of WSix films, and transition metal impurities to detection limits of 1×1014 atoms/cm2.
1.4 This test method can detect absolute differences in silicon and tungsten concentrations of ±3 and ±1 atomic percent, respectively, measured from different samples in separate analyses. Relative variations in the tungsten concentration in depth can be detected to ±0.2 atomic percent with a depth resolution of ±70Å.
1.5 This test method supports and assists in qualifying WSix films by electrical resistivity techniques.
1.6 This test method can be performed for WSix films deposited on conducting or insulating substrates.
1.7 This test method is useful for WSix films between 20 and 400 nm with an areal coverage of greater than 1 by 1 mm2.
1.8 This test method is non-destructive to the film to the extent of sputtering.
1.9 A statistical process control (SPC) of WSix films has been monitored since 1993 with reproducibility to ±4 %.
1.10 This test method produces accurate film thicknesses by modeling the film density of the WSix film as WSi2 (hexagonal) plus excess elemental Si2. The measured film thickness is a lower limit to the actual film thickness with an accuracy less than 10 % compared to SEM cross-section measurements (see 13.4).
1.11 This test method can be used to analyze films on whole wafers up to 300 mm without breaking the wafers. The sites that can be analyzed may be restricted to concentric rings near the wafer edges for 200-mm and 300-mm wafers, depending on system capabilities.
1.12 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.13 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. The reader is referenced to Section 8 of this test method for references to some of the regulatory, radiation, and safety considerations involved with accelerator operation.
WITHD...
- Standard7 pagesEnglish languagesale 15% off
ABSTRACT
This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials. This standard sets purity grade levels, analytical methods and impurity content reporting method and format. The grade designation is a measure of total metallic impurity content. It does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance. Analysis for trace metallic impurities and gases shall be performed on samples that represent the finished sputtering target. Carbon, oxygen, and sulfur shall be analysed by fusion and gas extraction/infrared spectroscopy. Nitrogen and hydrogen shall be analysed by fusion and gas extraction.
SCOPE
1.1 This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials and should be referenced therein.
1.2 This standard sets purity grade levels, analytical methods and impurity content reporting method and format.
1.2.1 The grade designation is a measure of total metallic impurity content. The grade designation does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance.
WITHDRAWN RATIONALE
This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials and should be referenced therein.
Formerly under the jurisdiction of Committee F01 on Electronics, this guide was withdrawn in January 2020 in accordance with section 10.6.3 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
- Guide2 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
The use of GaAs for semiconductor devices requires a consistent atomic lattice structure. However, lattice or crystal line defects of various types and quantities are always present, and rarely homogeneously distributed. It is important to determine the mean value and the spatial distribution of the etch pit density.
SCOPE
1.1 This test method is used to determine whether an ingot or wafer of gallium arsenide is monocrystalline and, if so, to measure the etch pit density and to judge the nature of crystal imperfections. To the extent possible, it follows the corresponding test method for silicon, Test Method F 47. Test Method F 47 also presents the definition of many crystallographic terms, applicable to this test method.
1.2 This procedure is suitable for gallium arsenide crystals with etch pit densities between 0 and 200 000/cm2.
1.3 Gallium arsenide, either doped or undoped, and with various electrical properties, may be evaluated by this test method. The front surface normal direction of the sample must be parallel to the 001> within ± 5° and must be suitably prepared by polishing or etching, or both. Unremoved processing damage may lead to etch pits, obscuring the quality of the bulk crystal.
1.4 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and to determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 8.
WITHDRAWN RATIONALE
This test method is used to determine whether an ingot or wafer of gallium arsenide is monocrystalline and, if so, to measure the etch pit density and to judge the nature of crystal imperfections.
Formerly under the jurisdiction of Committee F01 on Electronics, this test method was withdrawn in January 2016 in accordance with section 10.6.3 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
- Standard6 pagesEnglish languagesale 15% off
IEC TS 61439-7:2014-02(en-fr) defines the specific requirements of ASSEMBLIES as follows:
- ASSEMBLIES for which the rated voltage does not exceed 1 000 V in case of a.c. or 1 500 V in case of d.c;
- stationary or movable ASSEMBLIES with enclosure;
- ASSEMBLIES intended for use in connection with the generation, transmission, distribution and conversion of electric energy, and for the control of electric energy consuming equipment;
- ASSEMBLIES operated by ordinary persons;
- ASSEMBLIES intended to be installed and used in marinas, camping sites, market squares and other similar external public sites or similar sites;
- ASSEMBLIES intended for charging stations for electric vehicles.
This publication is to be read in conjunction with IEC 61439-1:2011
- Technical specification60 pagesEnglish and French languagesale 15% off
SCOPE
1.1 This test method covers the techniques used to determine the wavelength of the photoluminescence peak and the mole percent phosphorus content of gallium arsenide phosphide, GaAs(1 x)Px.
1.2 Photoluminescence measurements indicate the composition only in the illuminated region and only within a very short distance from the surface, a distance limited by the penetration of the radiation and the diffusion length of the photo-generated carriers, as contrasted to X-ray measurements which sample a much deeper volume.
1.3 This test method is limited by the surface preparation procedure to application to epitaxial layers of the semiconductor grown in a vapor-phase reactor on a flat substrate. It is directly applicable to n-type GaAs(1x)Px with the wavelength, PL, of the photoluminescence peak in the range from 640 to 670 nm, corresponding to mole percent phosphorus in the range from 36 to 42 % ( x = 0.36 to 0.42). The calibration data provided for the determination of x from P L is applicable to material doped with tellurium or selenium at concentrations in the range from 1016 to 1018 atoms/cm3.
1.4 The principle of this test method is more broadly applicable. Other material preparation methods may require different surface treatments. Extension to other dopants, doping ranges or composition ranges requires further work to relate PL to the phosphorus content as determined by X-ray measurements of the precise dimensions of the unit cell upon which the calibration data are based. It is essential that calibration specimens have uniform composition in the volume sampled.
1.5 This test method is essentially nondestructive. It requires a light etching of the sample to be measured. The removal of a layer of material approximately 0.5 to 1.0 m in thickness is required. This etching does not degrade the specimen in that devices can still be fabricated from it.
1.6 This test method is applicable to process control in the preparation of materials and to materials acceptance.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 7.
WITHDRAWN RATIONALE
Formerly under the jurisdiction of Committee F01 on Electronics, this test method was withdrawn in June 2008 in accordance with section 10.5.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
- Standard4 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
The efficiency of light-emitting diodes is known to vary with the carrier density of the starting material. This procedure provides a technique to prepare specimens in which the Hall carrier density can be measured in a region typical of that in which devices are fabricated. This quantity, which is related to the carrier density, can be used directly as a quality control parameter.
Mobility is a function of a number of parameters of a semiconductor, including ionized impurity density, compensation, and lattice defects, some or all of which may be relatable to material quality as reflected in device quality. Use of this procedure makes the measurement of the mobility of the constant composition region possible.
Since in GaAs (1−x)Px with x near 0.38, as is most often used for light-emitting diodes, the direct (000 or Γ) minimum and the indirect (100 or X) minima are within a few millielectronvolts in energy of each other, both are populated with current-carrying electrons. The mobility in the two bands is significantly different, and the relative population of the two is dependent upon the precise composition (x value), doping level, and temperature. Therefore, both Hall coefficient and Hall mobility must be interpreted with care (2,3). In particular, a measurement of Hall carrier density will not agree with a carrier density measurement on the same specimen made by capacitance-voltage techniques. Nevertheless, if the intent of measuring the carrier density of purchased or grown specimens is to find those which are optimum for diode fabrication, Hall measurements can be of value because a curve of efficiency versus Hall carrier density can be derived for the device process to be used based upon data taken on specimens prepared in accordance with this procedure.
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1.1 This practice covers a procedure to be followed to free the constant composition region of epitaxially grown gallium arsenide phosphide, GaAs(1x)Px, from the substrate and graded region on which it was grown in order to measure the electrical properties of only the constant composition region, which is typically 30 to 100 m thick. It also sets forth two alternative procedures to be followed to make electrical contact to the specimen.
1.2 It is intended that this practice be used in conjunction with Test Methods F 76.
1.3 The specific parameters set forth in this recommended practice are appropriate for GaAs0. 62P0. 38, but they can be applied, with changes in etch times, to material with other compositions.
1.4 This practice does not deal with making or interpreting the Hall measurement on a specimen prepared as described herein, other than to point out the existence and possible effects due to the distribution of the free carriers among the two conduction band minima.
1.5 This practice can also be followed in the preparation of specimens of the constant composition region for light absorption measurements or for mass or emission spectrometric analysis.
1.6 This practice becomes increasingly difficult to apply as specimens become thinner.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. For hazard statement, see Section 9 and 11.9.2.4.
WITHDRAWN RATIONALE
Formerly under the jurisdiction of Committee F01 on Electronics, this practice was withdrawn in June 2008 in accordance with section 10.5.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
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1.1 This destructive test method determines whether a given sample of semi-insulating gallium arsenide (GaAs) will remain semi-insulating after exposure to the high temperatures normally required for the activation of implanted layers.
1.2 The underlying assumption is that other wafers of GaAs, whose manufacturing history was the same as the wafer from which the test sample was taken, will respond to high temperatures in like manner.
1.3 The emphasis in this test method is on simplicity and safety of apparatus, and on securing a measurement that is independent of the apparatus used.
1.4 This test method is directly applicable to uncapped and unimplanted samples of GaAs. However, users of this test method may extend it to capped or implanted samples, or both, in which case a controlled test of capped versus uncapped samples, or implanted versus unimplanted samples, is recommended.
1.5 This test method detects impurities "from the bulk" (that is, from within the GaAs wafer) that will likely affect the electrical behavior of devices formed on the surface of the wafer. This test method is not sensitive to surface impurities or process-induced impurities, except as interferences (see Interferences).
1.6
WITHDRAWN RATIONALE
Formerly under the jurisdiction of Committee F01 on Electronics, this practice was withdrawn in June 2008 in accordance with section 10.5.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
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1.1 This test method covers the direct measurement of the sheet resistance and its variation for all but the periphery (amounting to three probe separations) for circular conducting layers pertinent to silicon semiconductor technology. These layers may be fabricated on substrates of any diameter that is capable of being securely mounted on a prober stage.
Note 1-The equation used to calculate the sheet resistance data from measurements is not perfectly accurate out to the edge of the wafer for probes oriented at an arbitrary angle with respect to a wafer radius. Further, automatic instruments on which this test method will be performed may not have perfect centering of the wafer on the measurement stage. These factors require that the periphery of the layer being measured be excluded. Also, many thin film processes use wafer clamps that preclude forming layers out to the edge of the substrate. The edge exclusion in this test method applies to the film that is being measured, rather than to the substrate. The equation used is based on mathematics developed for layers of circular shape. It is expected to work well for layers of other shapes such as rectangular, if edge exclusion requirements are met; however, the accuracy near the edge of other shapes has not been demonstrated.
1.2 This test method is intended primarily for assessing the uniformity of layers formed by diffusion, epitaxy, ion implant and chemical vapor, or other deposition processes on a silicon substrate. The deposited film, which may be single crystal, polycrystalline or amorphous silicon, or a metal film, must be electrically isolated from the substrate. This can be accomplished if the layer is of opposite conductivity type from the substrate or is deposited over a dielectric layer such as silicon dioxide. This test method is capable of measuring films as thin as 0.05 [mu]m, but particular care is required for establishing reliable measurements for most films in the range below 0.2 [mu]m. Films that have a thickness up to half the probe separation can be measured without the use of a thickness-related correction factor. It may give misleading results for films formed by silicon on insulator technologies because of charge or charge trapping in the insulator.
1.3 This test method can be used to measure the sheet resistance uniformity of bulk substrates. However, the thickness of the substrate must be known to be constant or must be measured at all positions where sheet resistance values are measured in order to calculate relative variations in resistance reliably.
Note 2-The thickness correction factor for layers that are thicker than 0.5 times the probe spacing is known to vary more rapidly than that for single-configuration four-probe measurements, but such a correction has not yet been published. Until such a correction is published, resistivity values determined by the dual-configuration method will not be accurate for these thicker specimens; however, if the wafer has uniform thickness, variations of resistivity can still be determined by this test method.
1.4 This test method can be used to measure sheet resistance values from below 10 m[omega] for metal films, to over 25000 [omega] for thin silicon films. However, for films at the upper end of this resistance range, and for films toward the low end of the thickness range, the interpretation of the sheet resistance values may not be straightforward due to various semiconductor effects (3, 4, 5).
Note 3-The principles of this test method are also applicable to other semiconductor materials, but the appropriate conditions and the expected precision have not been established.
1.5 This test method uses two different electrical configurations of the four-point probe at each measurement location. It does not require measurement of probe location on the wafer, or probe separations, or of wafer diameter (except to ...
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1.1 This guide covers the application of Certified Reference Materials (CRMs) for resistivity measurements on silicon wafers. Specifically, this guide covers the use of these CRMs for preparing resistivity reference wafers and for ensuring the quality of the instrumentation used for preparing them.
1.2 This guide has not been evaluated for application to electronic materials other than silicon.
1.3 The guide covers the selection of materials for resistivity reference wafers, procedures for preparing and calibrating resistivity reference wafers, and use of resistivity reference wafers in qualifying, calibrating, and controlling various types of resistivity instrumentation.
1.4 The guide provides criteria for selection of instruments for determining the resistivity of silicon resistivity reference materials, procedures for maintaining such instruments in statistical quality control, and training requirements for operators engaged in making and using resistivity reference wafers.
1.5 Appendixes are included that cover ( 1) suggested control charting procedures for organizations that do not already have such procedures in place, and (2) errors in resistivity determination that result from uncertainties in wafer diameter, wafer thickness, and probe-tip spacing.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers the measurement of carrier lifetime appropriate to carrier recombination processes in homogeneously doped, polished, - or -type silicon wafers with room-temperature resistivity greater than about 0.05 [omega][dot]cm. This test method may also be applied to the measurement of carrier recombination lifetime in as-cut, lapped, or etched wafers provided that the sensitivity of the conductivity detection system is adequate.
1.2 In this test method, the decay of the wafer conductivity following generation of excess carriers with a light pulse is determined by monitoring the microwave reflectivity of the wafer. Since no contact is made to the specimen, this test method is nondestructive. If wafer cleanness is maintained, wafers may be further processed following testing by this test method.
1.3 Depending on the level of photoexcitation, the carrier recombination lifetime determined by this test method may be the minority-carrier lifetime (low injection level) or a mixture of minority- and majority-carrier lifetimes (intermediate and high injection levels). In the latter case, the minority and majority carrier lifetimes may be separated under some conditions if a single recombination center that follows the Shockley-Read-Hall model is assumed (see Appendix X1).
1.4 This test method is appropriate for the measurement of carrier recombination lifetimes in the range from 0.25 [mu]s to >1 ms. The shortest measurable lifetime values are governed by the turn-off characteristics of the light source and by the sampling frequency of the decay signal analyzer while the longest values are determined by the geometry of the test specimen and the degree of passivation of the wafer surface. With suitable passivation procedures, such as thermal oxidation or immersion in a suitable solution, lifetimes as long as tens of milliseconds can be determined in polished wafers with thickness as specified in SEMI M1. Note 1-Carrier recombination lifetime of large bulk specimens can be determined by Method A or B of Test Methods F28. These test methods, which are also based on measurement of photoconductivity decay (PCD), require electrical contacts to the specimen. In addition, they assume large surface recombination on all surfaces and so the upper limit of measurable lifetime is governed by the size of the test specimen. Method B of Test Methods F28 stipulates that the test be carried out under conditions of low injection to ensure that the minority-carrier lifetime is determined. Minority-carrier lifetime can also be deduced from the carrier diffusion length as measured by the surface photovoltage (SPV) method in accordance with Method A or B of Test Methods F391. When carried out under low injection conditions, both the SPV method and the PCD method should yield the same values of minority-carrier lifetime (1) under certain conditions. First, it is required that carrier trapping not occur. Second, correct values of absorption coefficient and minority-carrier mobility must be used in analyzing the SPV measurements. Third, surface recombination effects must be eliminated (as in the present test method) or properly accounted for (as in Test Methods F28) in carrying out the PCD measurements. The generation lifetime, which is another transient characteristic of semiconductor materials, is typically orders of magnitude larger than the recombination lifetime. Although Test Method F1388 covers the measurement of the generation lifetime in silicon wafers, the recombination lifetime can also be deduced from capacitance-time measurements made at temperatures above room temperature ([>=]70°C) using the same MOS capacitor structure (2).
1.5 Interpretation of measurements to identify the cause or nature of impurity centers is beyond the scope of this test method. However, some aspects of deriving this information from carrier recombination lifetime m...
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1.1 These test methods cover the simultaneous determination of electrically active boron, phosphorus, arsenic, and aluminum content in low-dislocation mono-crystalline silicon.
1.2 These test methods can be used for samples that have majority dopant densities between approximately 1 X 1011 and 5 X 1015 atoms/cm3.
1.3 The concentrations obtained using these test methods are based on an empirically determined relationship of the logarithm of the concentration to the logarithm of specific luminescence line-intensity ratios.
1.4 The empirical relationship established assumes a constant sample excitation level for all measurements on a given instrument.
1.5 To accommodate differences in instrumentation, two methods are included in this proposal. "Test Method A" refers to procedures appropriate for dispersive infrared spectrophotometers operating under the high sample excitation conditions and "Test Method B" refers to procedures appropriate for Fourier transform instruments operating under low excitation conditions.
1.5.1 Typical calibration curves for each test method are provided. These curves are modified for each instrument using the analysis of standard samples as reference data. Once modified, the curves for a given instrument should produce sample dopant density values that agree with other similarly operated instruments using the same test method. Data obtained using Test Method A may not agree with data obtained using Test Method B, hence values must be reported with reference to the test method used.
1.6 Many laboratories use photoluminescence to analyze epitaxial layers. However this application encounters many variables and the underlying physics is not fully understood; hence these test methods do not attempt to outline standard practices regarding such analysis.
1.7 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers the determination of total trace boron contamination in the bulk of single crystal, heavily doped n-type silicon substrates using secondary ion mass spectrometry (SIMS).
1.2 This test method can be used for silicon in which the dopant concentrations are less than 0.2% (1 by 10 20 atoms/cm3) for antimony, arsenic or phosphorus. This test method is especially applicable for silicon where boron, the p-type dopant, is an unintentional contaminant at trace levels (∧lt;5 by 10 14 atoms/cm3).
1.3 This test method can be used for silicon in which the boron contamination is greater than two times the SIMS detection limits that is approximately between 5 by 10 12 atoms/cm3 and 5 by 10 13 atoms/cm3 depending upon the instrumentation type described herein.
1.4 In principle, different sample surfaces can be used, but the precision estimate was taken from data on polished etched surfaces.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This guide covers the procedures for producing a single set of consensus reference materials (ConRefs) in the absence of suitable certified reference materials from an established source.
1.2 This guide covers the steps to be taken to generate a set of ConRefs for a specific property or family of related properties required in semiconductor technology.
1.3 The procedure for generating the set of ConRefs is based on interlaboratory testing in accordance with Practice E691. It is assumed for the purposes of this guide that the test method evaluated by the interlaboratory study (ILS) is appropriate for determining the property values of the ConRef. This guide does not cover the selection of one of several possible test methods nor does it cover the case for which other reference materials must be used in the measurement of the properties of the ConRef.
1.4 This guide also describes procedures that may be used to generate consensus property values that may form the basis for the generation of multiple sets of CRMs or reference materials (RMs).
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1.1 This practice covers the size calibration of a scanning surface inspection system (SSIS) by observing the distribution of monodisperse polystyrene latex (PSL) spheres that have been pre-deposited in controlled fashion on the front surface of a clean, unpatterned, polished or epitaxial wafer of the same type that is to be inspected by the SSIS. Note 1-This practice was developed primarily for use in calibrating SSISs intended for inspecting monocrystalline wafers, in which case pre-deposited bare, monocrystalline silicon wafers must be used as calibration wafers. The practice may also be extended to the calibration of SSISs intended to inspect other materials, such as gallium arsenide or other compound semiconducting compounds, in which case, clean, unpatterned, polished wafers of the type to be inspected must be used as calibration wafers. It may also be possible to extend the technique to wafers with other surfaces, such as oxide or polycrystalline silicon films, but the conditions for which this extension of the practice might be valid have not been determined.
1.2 This practice includes procedures for single-point and multipoint calibrations. For single-point calibration, one wafer, pre-deposited with PSL spheres of a single nominal size corresponding to the latex sphere equivalent (LSE) of the localized light scatterers to be measured with the SSIS being calibrated, is used. In the latter, a series of wafers, each pre-deposited with PSL spheres of a single nominal size, is used; the range of sizes employed covers the range over which the SSIS is to be calibrated.
1.3 The procedure must be carried out on an SSIS that is located in a Class M2.5 (Class 10) or better environment as defined in Federal Standard 209E.
1.4 PSL spheres as large as 10 [mu]m can be used in this practice. The smallest size PSL sphere that can be used is the smallest that can be detected by the SSIS being calibrated on the wafer surfaces on which the spheres are deposited. Note 2-At the time of development of this practice, the smallest practical size is 0.08 [mu]m, but it is expected that smaller size spheres will be able to be used as the technology develops.
1.5 This practice does not cover procedures for deposition of the monodisperse PSL spheres. Pre-deposited wafers may be obtained commercially or prepared in accordance with good laboratory practice as summarized in Appendix A1 of SEMI Practice E14.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers determination of the absorption coefficient due to the interstitial oxygen content of commercial monocrystalline silicon wafers by means of Fourier transform infrared (FT-IR) spectroscopy. In this test method, the incident radiation is p-polarized and incident on the test specimen at the Brewster angle in order to minimize multiple reflections.
Note 1—In this test method, radiation in which the electric vector is parallel to the plane of incidence is defined as p-polarized radiation.
Note 2—Committee F01 has been advised that some aspects of this test method may be subject to a patent applied for by Toshiba Ceramics Corporation. The Committee takes no position with respect to the applicability or validity of such patents, but it requests users of this test method and other interested parties to supply any information available on non-patented alternatives for use in connection with this test method.
1.2 Since the interstitial oxygen concentration is proportional to the absorption coefficient of the 1107 cm1 absorption band, the interstitial oxygen content of the wafer can be derived directly using an independently determined calibration factor.
1.3 The test specimen is a single-side polished silicon wafer of the type specified in SEMI Specifications M1. The front surface of the wafer is mirror polished and the back surface may be as-cut, lapped, or etched (see 8.1.1.1).
1.4 This test method is applicable to silicon wafers with resistivity greater than 5 Ωcm at room temperature.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers the determination of the interstitial oxygen content of single crystal silicon by measurement of an infrared absorption band at room temperature. This test method requires the use of an oxygen-free reference specimen. It is recommended that a reference material, such as NIST SRM 2551, another certified reference material for oxygen content of silicon, or reference materials traceable to the CRMs, be used to calibrate the spectrophotometer in order to reduce bias.
1.2 This test method requires the use of a computerized spectrophotometer, preferably an FT-IR spectrophotometer. This method is incorporated into many modern FT-IR instruments.
1.3 The useful range of oxygen concentration measurable by this test method is from 1 X 1016 atoms/cm 3 to the maximum amount of interstitial oxygen soluble in silicon.
1.4 If the spectrophotometer is calibrated using 2-mm thick double-side polished CRMs, this test method is suitable for use only with 2-mm thick, double-side polished test specimens. It can be extended to the measurement of test specimens polished on one or both sides with thickness in the range 0.4 to 4 mm with the use of working reference materials traceable to the CRMs.
1.5 The oxygen concentration obtained using this test method assumes a linear relationship between the interstitial oxygen concentration and the absorption coefficient of the 1107 cm1 band associated with interstitial oxygen in silicon.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 These test methods provide means for examining the edge contour of circular wafers of silicon, gallium arsenide, and other electronic materials, and determining fit to limits of contour specified by a template that defines a permitted zone through which the contour must pass. Principal application of such a template is intended for, but not limited to, wafers that have been deliberately edge shaped.
1.2 Two test methods are described. One is destructive and is limited to inspection of discrete points on the periphery, including flats. The contour of deliberately edge-shaped wafers may not be uniform around the entire periphery, and thus the discrete location(s) may or may not be representative of the entire periphery. The other test method is nondestructive and suitable for inspection of all points on the wafers periphery except flats.
1.3 The nondestructive test method may also be applied to the examination of the edge contour of the outer periphery of substrates for rigid disks used for magnetic storage of data.
Note 1—Reference to wafers in the remainder of this standard shall be interpreted to include substrates for rigid disks unless the phrase "of electronic materials" is also included in the context.
1.4 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 These test methods cover complementary procedures for testing the oxygen precipitation characteristics of silicon wafers. It is assumed that the precipitation characteristics are related to the amount of interstitial oxygen lost during specified thermal cycles.
1.2 These test methods may be used to compare qualitatively the precipitation characteristics of two or more groups of wafers.
1.3 These test methods may be applied to any - or -type, any orientation Czochralski silicon wafers whose thickness, resistivity, and surface finish are such as to permit the oxygen concentration to be determined by infrared absorption and whose oxygen concentration is such as to produce measurable oxygen loss.
1.4 These test methods are not suitable for determining the width or characteristics of a "denuded zone," a region near the surface of a wafer that is essentially free of oxide precipitates.
1.5 Because these test methods are destructive, suitable sampling techniques must be employed.
1.6 The values stated in SI units are regarded as standard.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 8.
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1.1 This test method covers a nondestructive procedure to determine whether or not the dimensions of fiducial notches on silicon wafers fall within specified limits.
1.2 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.3 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers test site selection and data reduction procedures for radial variation of the interstitial oxygen concentration in silicon slices typically used in the manufacture of microelectronic semiconductor devices.
1.2 This test method is intended as both a referee and production test through selection of an appropriate test position plan.
1.3 The interstitial oxygen content may be measured in accordance with Test Methods F 1188 or F 1619, DIN 50438/1, JEIDA 61, or any other procedure agreed upon by the parties to the test.
Note 1—Test Method F 1366 is not based on infrared absorption measurement and it measures total oxygen content, not interstitial oxygen content. It is also a destructive technique. However, it can be used to determine the radial variation of the oxygen content if suitable modifications of the test procedure are made.
1.4 Acceptable thickness and surface finish for the test specimens are specified in the applicable test methods. This test method is suitable for use on chemically etched, single-side polished and double-side polished silicon wafers or slices with no surface defects that could adversely change infrared radiation transmission through the test specimen (subsequently called slice), provided that appropriate test methods for oxygen content are selected.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers measurement of the resistivity profile perpendicular to the surface of a silicon wafer of known orientation and type.
Note 1--This test method may also be applicable to other semiconductor materials, but feasibility and precision have been evaluated only for silicon and germanium.
1.2 This test method may be used on epitaxial films, substrates, diffused layers, or ion-implanted layers, or any combination of these.
1.3 This test method is comparative in that the resistivity profile of an unknown specimen is determined by comparing its measured spreading resistance value with those of calibration standards of known resistivity. These calibration standards must have the same surface preparation, conductivity type, and crystallographic orientation as the unknown specimen.
1.4 This test method is intended for use on silicon wafers in any resistivity range for which there exist suitable standards. Polished, lapped, or ground surfaces may be used.
1.5 This test method is destructive in that the specimen must be beveled.
1.6 Correction factors, which take into account the effects of boundaries or local resistivity variations with depth, are needed prior to using calibration data to calculate resistivity from the spreading resistance values.
Note 2--This test method extends Method F525 to depth profiling.
Note 3--This test method provides means for directly determining the resistivity profile of a silicon specimen normal to the specimen surface. Unlike Test Methods F84, F374, F1392, and F1393, it can provide lateral spatial resolution of resistivity on the order of a few micrometres, and an in-depth spatial resolution on the order of 10 nm (100 A). This test method can be used to profile through p-n junctions.
1.7 This test method is primarily a measurement for determining the resistivity profile in a silicon wafer. However, common practice is to convert the resistivity profile information to a density profile. For such purposes, a conversion between resistivity and majority carrier density is provided in Appendix X2.
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 9.
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1.1 This test method covers three procedures for determining the density, activation energy, and prefactor of the exponential expression for the emission rate of deep-level defect centers in semiconductor depletion regions by transient-capacitance techniques. Procedure A is the conventional, constant voltage, deep-level transient spectroscopy (DLTS) technique in which the temperature is slowly scanned and an exponential capacitance transient is assumed. Procedure B is the conventional DLTS (Procedure A) with corrections for nonexponential transients due to heavy trap doping and incomplete charging of the depletion region. Procedure C is a more precise referee technique that uses a series of isothermal transient measurements and corrects for the same sources of error as Procedure B.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This terminology covers terms and definition used in relation to semiconductor grade silicon crystal and wafers.
1.2 This terminology covers terms describing attributes of silicon wafers as specified in SEMI Specifications M1 and SEMI Format M18. These attributes include electrical, structural, chemical, and mechanical characteristics of polished and epitaxial wafers as well as surface defects and contamination.
1.3 This terminology is applicable for use in connection with research, developement, process control, procurement, and inspection of silicon material.
1.4 Originally the terms and definitions included in this standard were extracted from other ASTM Standards relating to silicon technology. The original source standards for such terms are identified by their designations immediately following the definition. All such standards are found in this volume of the Annual Book of ASTM Standards . More recently, new or revised terms and definitions have been balloted directly for inclusion in this standard; these terms have no designation following the definition.
1.5 Almost all of the terms listed are nouns; in other cases, the part of speech is given explicitly immediately following the term.
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1.1 This referee test method covers the determination of substitutional carbon concentration in single crystal silicon. Because carbon may also reside in interstitial lattice positions, when in concentrations near the solid solubility limit, the results of this test method may not be a measure of the total carbon concentration.
1.2 The useful range of carbon concentration measurable by this test method is from the maximum amount of substitutional carbon soluble in silicon down to about 0.1 parts per million atomic (ppma), that is, 5 X 10 15 cm -3 for measurements at room temperature, and down to about 0.01 ppma, that is, 0.5 X 10 15 cm -3 at cryogenic temperatures (below 80 K).
1.3 This test method utilizes the relationship between carbon concentration and the absorption coefficient of the infrared absorption band associated with substitutional carbon in silicon. At room temperatures (about 300 K), the absorption band peak is at 605 cm -1 or 16.53 [mu]m. At cryogenic temperatures (below 80 K), the absorption band peak is at 607.5 cm -1 or 16.46 [mu]m.
1.4 This test method is applicable to slices of silicon with resistivity higher than 3 [omega]-cm for -type and higher than 1 [omega]-cm for -type. Slices can be any crystallographic orientation and should be polished on both surfaces.
1.5 This test method is intended to be used with infrared spectrophotometers that are equipped to operate in the region from 2000 to 500 cm -1 (5 to 20 [mu]m).
1.6 This test method provides procedure and calculation sections for the cases where thickness values of test and reference specimens are both closely matched and not closely matched.
1.7 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers techniques for determination of the length of the flatted portion of a wafer periphery.
1.2 This test method is intended primarily for use on electronic materials in the form of nominally circular edge-contoured wafers with flat lengths up to 65 mm. The precision of this test method has been established directly only for silicon wafers, but it is not expected to be material dependent.
1.3 This test method is suitable for referee measurement purposes and may be used for routine acceptance measurements when specified limits require test precision greater than can be obtained with hand held scale and unaided eye.
1.4 This test method is independent of surface finish.
1.5 For application to wafers of diameter 3 in. or smaller, the values stated in inch-pound units are to be regarded as the standard; the values stated in acceptable metric units are for information only. For application to wafers of diameter larger than 3 in., the values stated in acceptable metric units are to be regarded as the standard whether or not they appear in parentheses; the values stated in inch-pound units are for information only.
1.6 This standard does not purport to address the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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This standard was transferred to SEMI (www.semi.org) May 2003
1.1 This practice describes a conversion between dopant density and resistivity for boron- and phosphorus-doped single crystal silicon at 23°C. The conversions are based primarily on the data of Thurber et al (1,2,3) taken on bulk single crystal silicon having dopant density values in the range from 3 X 10 cm to 1 X 10 cm for phosphorus-doped silicon and in the range from 10 cm to 1 X 10 cm for boron-doped silicon. The phosphorus data base was supplemented in the following manner:two bulk specimen data points of Esaki and Miyahara (4) and one diffused specimen data point of Fair and Tsai (5) were used to extend the data base above 10 cm , and an imaginary point was added at 10 cm to improve the quality of the conversion for low dopant density values.
1.2 The self consistency of the conversion (resistivity to dopant density and dopant density to resistivity) (see Appendix X1) is within 3% for boron from 0.0001 to 10 000 [omega][dot]cm, (10 to 10 cm ) and within 4.5% for phosphorus from 0.0002 to 4000 [omega][dot]cm (10 to 5 X 10 cm ). This error increases rapidly if the phosphorus conversions are used for densities above 5 X 10 cm .
1.3 These conversions are based upon boron and phosphorus data. They may be extended to other dopants in silicon that have similar activation energies; although the accuracy of conversions for other dopants has not been established, it is expected that the phosphorus data would be satisfactory for use with arsenic and antimony, except when approaching solid solubility. See 5.3.
1.4 These conversions are between resistivity and dopant density and should not be confused with conversions between resistivity and carrier density or with mobility relations. Note 1-The commonly used conversion between resistivity and dopant density compiled by Irvin (6) is compared with this conversion in Appendix X2. In this compilation, Irvin used the term "impurity concentration" instead of the term "dopant density."
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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This standard was transferred to SEMI (www.semi.org) May 2003
1.1 This test method covers a noncontacting, non-destructive procedure to determine the sori of clean, dry semiconductor wafers.
1.2 The test method is applicable to wafers 50 mm or larger in diameter, and 100 [mu]m (0.004 in.) approximately and larger in thickness, independent of thickness variation and surface finish, and of gravitationally-induced wafer distortion.
1.3 This test method employs a two-probe system that examines both external surfaces of the wafer simultaneously.
1.4 This test method measures sori of a wafer corrected for all mechanical forces applied during the test. Therefore, the procedure described gives the unconstrained value of sori. This test method includes a means of canceling gravity-induced deflection which could otherwise alter the shape of the wafer. The resulting parameter is described by Sori in SEMI Specification M1, Appendix A2 Shape Decision Tree (see Annex A1).
1.5 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
1.6 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
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This standard was transferred to SEMI (www.semi.org) May 2003
1.1 This practice covers the surface preparation of silicon samples prior to measurement of resistivity variations by the spreading resistance technique.
1.2 Separate procedures are given for preparation of large-area specimens for measurement of lateral resistivity variations and for preparation of bevel-sectioned specimens (usually small chips) for measurement of vertical variations of resistivity (depth profiling). Note 1-Benefits derived from diamond polishing are ( ) stability and reproducibility of spreading resistance values on large area or beveled specimens, and ( ) acuity of beveled surface geometry. The benefits of stability and reproducibility are likely to apply to both conductivity types and all resistivity values; however, they have been demonstrated extensively only for (111) -type above 1 [omega][dot]cm. Enhanced bevel acuity is independent of conductivity-type or resistivity value.
1.3 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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