IEC 63505:2025
(Main)Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs
Guidelines for measuring the threshold voltage (<em>V</em><sub>T</sub>) of SiC MOSFETs
IEC 63505:2025 gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope.
SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI).
General Information
- Status
- Published
- Publication Date
- 07-Apr-2025
- Technical Committee
- TC 47 - Semiconductor devices
- Drafting Committee
- WG 8 - TC 47/WG 8
- Current Stage
- PPUB - Publication issued
- Start Date
- 08-Apr-2025
- Completion Date
- 28-Mar-2025
Overview
IEC 63505:2025 - Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs provides practical, consensus guidance for measuring and conditioning the threshold voltage of N‑channel vertical-structure silicon carbide (SiC) power MOSFETs. The standard addresses measurement methods and pre‑test conditioning that reduce or eliminate VT hysteresis caused by transient traps at the SiC/SiO2 interface. The methods are applicable for positive bias temperature instability (PBTI) testing; negative BTI (NBTI) and VT changes caused by switching events are excluded from the scope.
Key topics and technical requirements
- VT hysteresis: SiC MOSFETs can show gate-sweep hysteresis from transient trap effects, complicating true VT-shift evaluation after stress (e.g., BTI).
- Conditioning pulse: A positive gate pulse (up to VGS_MAX) applied before measurement minimizes hysteresis; the pulse can make VT effectively “flat” over time.
- Test circuits and extraction methods:
- Conventional SMU-based transfer sweep (separate gate and drain): measure IDS while sweeping VGS upward and downward.
- Gate‑drain shorted (GDS) methods: extract VT from the X‑intercept of √IDS vs VGS or by forcing a target IDS for a spot measurement.
- Measurement details:
- Small VGS step for sweeps (recommended e.g., 0.1 V) to improve VT accuracy.
- Define a threshold current (Ith) for VT determination.
- Recommended timing intervals (from literature and expert consensus):
- For sweep test circuit: t_con = 1–100 ms; t_V < 10 ms × number of steps; t_float < 10 ms (keep as short as possible).
- For GDS/alternative methods: t_con = 1–100 ms; t_V < 100 ms (device dependent); t_float < 50 ms.
- Test conditions: Maintain consistent conditioning pulse width and device temperature to ensure repeatable VT values.
Applications - who uses this standard
- SiC power semiconductor manufacturers and process engineers (datasheet and process control)
- Reliability and test engineers performing PBTI stress and VT monitoring
- Device characterization labs and OEM power electronics teams validating on-resistance transitions and final tests
- Technology development teams optimizing gate oxide and interface treatments
Related standards and references
- JEDEC JEP183A - predecessor guidance referenced in IEC 63505
- IEC 60747‑8 - related device symbol conventions (document cites symbol usage)
- Use IEC Electropedia and ISO Online Browsing Platform for terminology
Keywords: IEC 63505:2025, SiC MOSFET, threshold voltage, VT measurement, VT hysteresis, conditioning pulse, PBTI, SMU, gate‑drain shorted (GDS), bias temperature instability (BTI).
Frequently Asked Questions
IEC 63505:2025 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Guidelines for measuring the threshold voltage (<em>V</em><sub>T</sub>) of SiC MOSFETs". This standard covers: IEC 63505:2025 gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope. SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI).
IEC 63505:2025 gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope. SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI).
IEC 63505:2025 is classified under the following ICS (International Classification for Standards) categories: 31.080.30 - Transistors. The ICS classification helps identify the subject area and facilitates finding related standards.
You can purchase IEC 63505:2025 directly from iTeh Standards. The document is available in PDF format and is delivered instantly after payment. Add the standard to your cart and complete the secure checkout process. iTeh Standards is an authorized distributor of IEC standards.
Standards Content (Sample)
IEC 63505 ®
Edition 1.0 2025-04
INTERNATIONAL
STANDARD
Guidelines for measuring the threshold voltage (V ) of SiC MOSFETs
T
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IEC 63505 ®
Edition 1.0 2025-04
INTERNATIONAL
STANDARD
Guidelines for measuring the threshold voltage (V ) of SiC MOSFETs
T
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.30 ISBN 978-2-8327-0325-0
– 2 – IEC 63505:2025 © IEC 2025
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references. 6
3 Terms, definitions, and letter symbols . 6
3.1 Terms and definitions . 6
3.2 Letter symbols . 6
4 Requirements . 7
5 Test circuits . 8
5.1 Test circuits . 8
5.2 How to define conditioning . 11
Bibliography . 12
Figure 1 – V hysteresis observed by upward and downward sweep measurement,
T
V = V , left graph shows the gate bias pattern and right graph shows the
DS GS
corresponding drain current response . 7
DOWN
Figure 2 – V extracted from a SiC MOSFET device at different current levels
T
after biasing the device in deep inversion for 100 ms . 8
Figure 3 – Conditioning before threshold voltage measurement . 8
Figure 4 – V test circuit (upper left picture), timing diagram (right graphs) and typical
T
transfer characteristic (lower graph) . 9
Figure 5 – Alternative V test circuit (upper left picture), timing diagram (right graphs)
T
and typical transfer characteristics (lower graphs) . 10
Figure 6 – Alternative test method (left pictures) and timing diagram (right graphs) . 10
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
GUIDELINES FOR MEASURING THE THRESHOLD VOLTAGE (V )
T
OF SIC MOSFETS
FOREWORD
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IEC 63505 has been prepared by IEC technical committee 47: Semiconductor devices. It is an
International Standard.
This standard is based upon JEP183 [1] with permission of the copyright holder, JEDEC Solid
State Technology Association, and was submitted as a Fast-Track document.
___________
Numbers in square brackets refer to the Bibliography.
– 4 – IEC 63505:2025 © IEC 2025
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2885/FDIS 47/2908/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
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