IEC 63601:2026

IEC 63601 ®
Edition 1.0 2026-02
INTERNATIONAL
STANDARD
Guideline for evaluating bias temperature instability of silicon carbide metal-
oxide-semiconductor devices for power electronic conversion

ICS 31.080.30  ISBN 978-2-8327-1019-7

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CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Considerations for bias-temperature instability (BTI) stress methods and shift
evaluation for SiC-based MOS devices . 11
4.1 General . 11
4.2 Mechanisms of V shift and hysteresis resulting from PBTI/NBTI stress . 12
T
4.3 Threshold voltage and hysteresis measurements . 12
4.3.1 Comments concerning threshold voltage (V ) measurements . 12
T
4.3.2 V measurement and conditioning . 15
T
HYST
4.3.3 Threshold hysteresis (V ) and fast transient effects . 16
T
4.4 Typical PBTI/NBTI stress considerations . 17
4.5 Lifetime prediction models and failure determination . 18
4.6 Overview of BTI methods . 20
5 General Measure Stress Measure (MSM) method . 21
6 Fast Drain Current (FDC) method . 23
7 Gate sweep MSM method . 24
8 Conditioning Method . 26
9 Hysteresis method (or double sense method) . 27
10 Triple sense method . 28
Annex A (informative) Supplemental sampling guidelines. 30
Annex B (informative) Examples demonstrating V shift during BTI measurements . 31
T
B.1 General . 31
B.2 Single V sense measurements . 31
T
B.3 Double V sense measurements (hysteresis method) . 33
T
B.4 Triple V sense measurements (V sense + hysteresis) . 35
T T
Annex C (informative) Examples demonstrating V shift during gate switching . 37
T
Annex D (informative) Lifetime models . 39
Annex E (informative) General introduction to threshold voltage (V ) stability and SiC-
T
based MOS devices . 41
Bibliography . 43

Figure 1 – Proposed sweep methods for NBTI and PBTI for MOSFETs . 14
Figure 2 – Proposed sweep methods for NBTI and PBTI for gated diode configuration . 14
Figure 3 – Circuit diagram for the V measurement using the gated-diode configuration . 15
T
Figure 4 – Sweep proposal and I vs V response for the fixed V method . 15
D GS GS
Figure 5 – Hysteresis measurement sequence, measuring V using the gated diode V
T T
sense method . 16
Figure 6 – Hysteresis measurement sequence using gate sweeps . 17
Figure 7 – The absolute value of NBTI V shift . 19
T
Figure 8 – The PBTI V shift as a function of time, fit to a power law for the longer time
T
shift data . 19
Figure 9 – MSM PBTI stress and measure waveforms . 22
Figure 10 – MSM NBTI stress and measure waveforms . 23
Figure 11 – Fast-drain current waveforms for PBTI stress . 23
Figure 12 – Fast-drain current waveforms for NBTI stress . 24
Figure 13 – Gate-sweep MSM method waveforms for PBTI . 25
Figure 14 – Gate-sweep MSM method waveforms for NBTI . 25
Figure 15 – Conditioning method waveforms for PBTI . 26
Figure 16 – Conditioning method waveforms for NBTI . 27
Figure 17 – Conditioning method waveforms for NBTI . 27
Figure 18 – BTI hysteresis method using the full hysteresis measurement as the V
T
sense step after each V stress period . 28
GS
Figure 19 – BTI triple sense method using a first V sense followed by a hysteresis
T
measurement (three V measurements per sense step) . 29
T
Figure B.1 – Example showing the measured V over time during PBTI using a single
T
V sense . 32
T
Figure B.2 – Example showing the measured V over time during NBTI using a single
T
V sense . 32
T
Figure B.3 – Example showing the effect of a conditioning pulse on the measured V
T
over time during NBTI using a single V sense. . 33
T
Figure B.4 – Example showing the two V versus time curves obtained during the PBTI
T
hysteresis method . 34
Figure B.5 – Example showing the two V versus time curves obtained during the NBTI
T
hysteresis method . 34
Figure B.6 – Example showing the three V versus time curves obtained during the
T
PBTI triple sense method. . 35
Figure B.7 – Example showing the three V versus time curves obtained during the
T
NBTI triple sense method . 36
Figure C.1 – V evolution over time . 38
T
Table 1 – BTI methods described in this document . 21

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Guideline for evaluating bias temperature instability of silicon carbide
metal-oxide-semiconductor devices for power electronic conversion

FOREWORD
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IEC 63601 has been prepared by IEC technical committee 47: Semiconductor devices. It is an
International Standard.
It is based upon JEDEC JEP184: Guideline for Evaluating Bias Temperature Instability of Silicon
Carbide Metal-Oxide Semiconductor Devices for Power Electronic Conversion. It is used with
permission of the copyright holder, JEDEC Solid State Technology Association. It was
submitted as a Fast Track document.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2986/FDIS 47/2994/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
The structure and editorial rules used in this publication reflect the practice of the organization
which submitted it.
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The committee has decided that the contents of this document will remain unchanged until the
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specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
INTRODUCTION
The objective of this document is to provide useful definitions and procedures for characterizing
the threshold voltage instability of SiC-based power electronic conversion semiconductor
(PECS) devices having a gate dielectric region biased to turn devices on and off. This typically
refers to MOS (Metal-Oxide-Semiconductor) devices such as field-effect transistors (MOSFETs,
Metal-Oxide-Semiconductor Field Effect Transistors)) and insulated-gate bipolar transistors
(IGBTs). For simplicity reasons, in the following paragraphs the terms MOSFET or MOS device
are used only, while the content is valid for IGBT’s as well. Monitoring of threshold-voltage
instability in MOS devices is commonly referred to by the term “bias-temperature instability”
(BTI), while the applied stress to check for instability is usually referred to as “bias-temperature-
stress” (BTS). The terms BTI, BTS, and threshold-voltage instability will be used throughout
this document.
1 Scope
The scope of this document covers SiC-based PECS devices having a gate dielectric region
biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and
IGBTs. In this document, only NMOS (N-type MOS) devices are discussed as these are
dominant for power device applications; however, the procedures apply to PMOS (P-type MOS)
devices as well.
This document does not define device failure criteria, acceptable use conditions or acceptable
lifetime targets. That is up to the device manufacturers and users. However, it provides stress
procedures such that the threshold voltage stability over time as affected by gate bias and
temperature can be demonstrated and evaluated.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60747-8:2010, Semiconductor devices - Discrete devices - Part 8: Field-effect transistors
IEC 63505, Guidelines for measuring the threshold voltage (V ) of SiC MOSFETs
T
3 Terms and definitions
3.1
metal-oxide-semiconductor field-effect transistor
MOSFET
insulated-gate field-effect transistor in which the insulating layer between the gate electrode
and the channel is oxide (or dielectric) material and the gate is metal or another highly
conductive material
[SOURCE: IEC 60050-521:2002, 521-04-55, modified – The words “(or dielectric)” have been
added between “oxide” and “material; the words “and the gate is metal or another highly
conductive material” have been added after the word “material”.]
3.2
silicon carbide
SiC
wide bandgap semiconducting material that serves as the active device semiconductor material,
for example the channel and drift region
Note 1 to entry: Typically the 4H hexagonal polytype is preferred, denoted 4H-SiC, in the (0001) wafer orientation
(other polytypes sometimes used are 6H-SiC, or 3C-SiC)
3.3
power electronic conversion semiconductor devices
PECS devices
power devices used for power conversion to different voltage or current levels, or as inverters
between alternating and direct current power (or vice versa)
3.4
gate oxide
oxide (or dielectric) region under the gate electrode in the MOS portion of the MOS device
3.5
oxide thickness
T
ox
gate oxide (or dielectric) thickness, measured electrically, optically, or physically
3.6
oxide field
E
ox
oxide field (V/cm), V /T
ox ox
3.7
oxide voltage
V
ox
voltage drop across gate oxide (V)
3.8
gate to source voltage
V
GS
voltage drop from gate to source (V)
3.9
drain to source voltage
V
DS
voltage drop from drain to source (V)
3.10
drain current
I
D
drain current (A) measured with a bias on the drain
3.11
gate-source voltage maximum
V
GSmax
maximum gate-source voltage recommended for a device, for any time period during operation
3.12
gate-source voltage for stress
V
GSST
gate source voltage used for stress
3.13
stress time
t
S
total stress time applied in BTI testing
3.14
stress temperature
T
s
temperature used for BTI testing
3.15
bias temperature instability
BTI
susceptibility of the threshold voltage of an MOS device to change over time under bias and
temperature stress
3.16
negative BTI
NBTI
BTI due to a negative gate bias stress, at a fixed stress temperature
3.17
positive BTI
PBTI
BTI due to positive gate bias stress, at a fixed stress temperature
3.18
bias-temperature stress
BTS
stressing of a device by simultaneous exposure to gate bias and elevated temperature
Note 1 to entry: Often used in place of the acronym BTI; the difference (if any) is that BTI refers more specifically
to the effect of stress on V , whereas BTS is more of a descriptor of the stress condition on the device.
th
3.19
threshold voltage
V
T
gate-source voltage V value (at some specified drain
GS
voltage V ) at which the device conducts forward current of a specified current value
DS
Note 1 to entry: A drain-current-defined threshold is used in this document, with the selected current at threshold
being a very small fraction of the rated device current.
3.20
threshold current
I
DST
drain current at which V is defined
T
3.21
threshold voltage
V
T(GS)
V measurement performed by sweeping the gate bias with
T
a constant and relatively low drain bias (~ 100 mV min, up to a few Volts typically) until a certain
I current value is reached
D
Note 1 to entry: In JESD 77-B, the symbol for the threshold voltage for enhancement FET is defined as V . In
GS(th)
IEC 60747-8, the symbol for the threshold voltage of FET is defined as V or V or V . In this document,
GST GS(th) GS(TO)
V is used as “threshold voltage of DUT”.
T
3.22
threshold voltage
V
T(GDS)
Threshold voltage of DUT measured by test circuit where gate and
drain are shorted according to IEC 63505, V measurement performed by sweeping the gate
T
and drain together (V = V ) until reaching a chosen constant I value
GS DS D
Note 1 to entry: The gated-diode configuration allows for fast and reproducible point measurements of the V and
T
guarantees a constant electron density in the channel during V readout.
T
3.23
threshold voltage measurement
UP
V
T
threshold voltage of DUT taken by upward sweep according
to IEC 63505, V measurement performed immediately following a negative gate bias stress
T
during NBTI, or following a negative V conditioning pulse (as in a hysteresis measurement),
GS
or if performed by sweeping the gate bias starting from a negative gate voltage and sweeping
up until I is reached
T
UP
Note 1 to entry: In general, V will represent the low V side of the hysteresis in V . To minimize recoverable
T T T
fast charge-trapping effects and achieve repeatable results, it is recommended to stabilize the traps by holding at
the negative V for a sufficient duration; 100 ms is a typical recommended value for SiC.
GS
3.24
threshold voltage measurement
DOWN
V
T
threshold voltage of DUT taken by downward sweep according
to IEC 63505, V measurement performed immediately following a positive gate bias stress
T
during PBTI, or following a positive V conditioning pulse (as in a hysteresis measurement),
GS
or if performed by sweeping the gate bias starting from a positive gate voltage and sweeping
down until I is reached
T
DOWN
Note 1 to entry: In general, V will represent the high V side of the hysteresis in V . To minimize recoverable
T T T
fast charge-trapping effects and achieve repeatable results, it is recommended to stabilize the traps by holding at
the positive V for a sufficient duration; 100 ms is a typical recommended value for SiC.
GS
3.25
threshold voltage
V
Tt#
V measured over time during the BTI stress
T
Note 1 to entry: A time-related subscript can be used when referring to a particular stress time.
Note 2 to entry: For improved extrapolation of V over time, the initial measured V during BTI should be after a
T T
brief (~ 100 ms) initial stress and/or conditioning, such that V (or V ) occurs after the initial brief stress.
Ti Tt0
Note 3 to entry: The initial pre-stress V and the final post-stress V may be defined using different subscripts,
T T
such as V and V , respectively.
Tpre Tpost
3.26
threshold voltage shift
shift
∆V
T
change in the measured V value from an initial to a final condition, here particularly focused
T
on the V shift during BTI stress
T
Note 1 to entry: This shift is described as the ongoing shift over time (V - V ), which by the end of the stress
Tt# Ti
would be the final V minus the initial V . This shift value could be due to:
Tf Ti
trans
a) transient charging effects (∆V ) which are fully recoverable,
T
HYST
b) transient effects which have a permanent component (∆V ), or
T
drift
c) permanent (non-transient) interface effects (∆V ). More generally, V shift is the change in V between any
T T T
two measured values, and can arise from a change in gate bias, or the continued application of the same gate
bias.
3.27
threshold voltage drift
drift
∆V
T
shift
BTI changes in V (∆V ) which are relatively permanent, after transient V recovery effects
T T T
are removed
Note 1 to entry: For example, if a V is measured without a change in transient effects, there would be a shift in
Tshift
drift
the voltage location of the threshold voltage due only to a ∆V effect.
T
3.28
threshold voltage transient shift
trans
∆V
T
shift
portion of the BTI threshold shift (∆V ) that quickly recovers after removal of gate stress
T
Note 1 to entry: This is typically larger or beyond what a short hysteresis measurement would reveal, due to time
at bias effects during BTI that result in charging on a time scale that a short hysteresis measurement does not
capture.
3.29
threshold voltage hysteresis
HYST
V
T
DOWN
difference in threshold voltage measured after a positive gate bias stress (V ) and that
T
UP
measured after a negative gate-bias stress (V ) of equal stress time
T
HYST DOWN UP
V = V – V
T T T
Note 1 to entry: For normal devices, with at least some active interfacial traps (and little or no mobile ions), this
hysteresis value will be positive. For what is here considered intrinsic device hysteresis, the timing for the stress and
sense portions of a hysteresis measurement called for are on the order of 100 ms. Faster or slower measurements
can be useful to reveal more complete details of the transient effects.
3.30
change in threshold voltage hysteresis
HYST
∆V
T
permanent (repeatable) hysteresis effects observed when performing a standard 2-sequence
hysteresis measurement
HYST HYST HYST
∆V = V – V
T T (f) T (i)
Note 1 to entry: The difference between final (post-BTS) and initial (pre-BTS) hysteresis values would comprise a
change in hysteresis. Because there is a stress time dependence of the magnitude of this value.
3.31
conditioning
applying a gate bias to induce a certain charge state immediately prior to a V measurement
T
Note 1 to entry: To make a fair comparison of changes in V due to a BTS, the same V conditions (conditioning)
T GS
should be used before each measurement.
3.32
relaxation
charge redistribution over time after gate bias is removed, which typically allows the V to shift
T
back towards values before stress was applied
3.33
recovery
change of the V value after BTI towards the previous value due to a removal of bias (similar
T
to relaxation), or due to the application of a different fixed bias
3.34
drain-source on-state resistance
r
DS(on)
resistance of the device (drain-source) in the on-state with the rated V applied, and at a
GS
specified (typically the rated) on-state current
3.35
off-state drain current
I
DSS
drain leakage from source with device in the off-state (at V = 0 V or the rated off-state V
GS GS
bias (such as the rated
value), in the static mode (non-switching), at a specified high V
DS
blocking voltage)
4 Considerations for bias-temperature instability (BTI) stress methods and
shift evaluation for SiC-based MOS devices
4.1 General
BTI stress procedures would ideally cover the operational limits of gate bias, temperature, and
time, such that a ‘safe-operating-area’ (SOA) can be understood by the device user in an
application. While it is very difficult to cover all conditions (especially regarding time), the goal
is to cover appropriate stress conditions that will enable V shift projections to long use times;
T
or at least to demonstrate the device threshold voltage behaviour under constant bias gate
stress.
In general, BTI V stability stress should be an evaluation of V stability over time at different
T T
levels of gate bias and device temperature, ideally without allowing the effects of V recovery
T
to mask any application-relevant device instability. The measured threshold shift during BTI can
drift trans
be composed of long-term V drift (∆V ), transient V changes (∆V ), and hysteresis
T T T T
HYST HYST
behavior (V ) or changes in hysteresis (∆V ); these will be discussed in detail below.
T T
Constant bias stress under both PBTI and NBTI conditions should be performed to allow V
T
shift behavior to be determined under both positive and negative gate bias conditions (device
on-state and off-state situations).
There are a variety of stress and measurement techniques that have been described in the
literature; some appropriate approaches will be described in this document. Some differences
shift
in the ∆V will be observed depending on the V sense approach used, as will be discussed.
T T
Thus, the BTI approach used shall always be described with a BTI V shift dataset.
T
In summary, the goal of BTI stress is to determine the shift of the threshold voltage as a function
of the stress time (t ), stress voltage (V ) and stress temperature (T ), to demonstrate
s GSST S
threshold characteristics under constant gate bias stress (representing a situation that can
readily be compared between devices). A final goal would be to determine general safe
and the off-state blocking leakage
operating limits (SOA) before the on-state resistance r
DS(on)
I fall outside of data sheet or application specific operation conditions; however, this does
DSS
not represent actual applications well because the devices don’t typically operate under unipolar
gate stress. However, BTI stress results nevertheless represent a useful standard approach to
demonstrate V stability. This document describes appropriate measurement approaches, and
T
appropriate ways to interpret the measurement results.
4.2 Mechanisms of V shift and hysteresis resulting from PBTI/NBTI stress
T
The threshold voltage and the shift in V depends on the charge state of existing interfacial
T
traps (typically interface and near-interface (border traps)), the effects of new traps created by
the stress, and how these change over time. Typically trap filling and/or trap generation occurs
during stress, and de-trapping occurs when stress is removed, resulting in an observed V
T
hysteresis when the device experiences an opposite polarity bias (switching) sequence.
Interface traps and near-interface oxide traps (border traps) are intrinsically present at or near
an interface between an oxide and semiconductor due to property differences between any two
materials that are not epitaxial and lattice-matched. Processing can reduce the density of these
defects, but some are always present. These intrinsically present defects will shift threshold in
the direction of the applied V stress during BTI stress. Extrinsic contamination near the
GS
interface region usually makes the V shift much worse. These can cause additional shift in the
T
stress bias direction, or even a shift opposite to the applied bias if the impurity is a mobile ion
species or forms a polarizable molecule. The discussion throughout this document is focused
on the effect of intrinsically present traps that are not due to extrinsic impurities. However,
regardless of the origin of V shift during BTI stress, the stress methodology remains the same.
T
The effect of the BTI phenomena is that when V changes, other device parameters such as
T
r and I can shift relative to their values when the device was manufactured. The
DS(on) DSS
mechanisms and effects are similar in SiC-based and Si-based devices, but the effects can be
more pronounced and have a different time dependence in SiC-based devices. The issues are
complicated due to: A) the wide bandgap of SiC (resulting in different trap densities and energy
levels), B) differences in the interface chemistry/properties of the various SiC crystal faces (for
example, the planar MOSFET device channel is typically on the Si-face (0001) of SiC while a
trench device can have an MOS interface on the perpendicular a-face {11-20} family of planes),
C) the chemical difference of SiC versus Si at the interface with SiO , D) the higher
temperatures used for oxide processing in SiC MOSFETs, and E) the different interface
passivation elements utilized for SiC MOS devices (usually nitrogen, not hydrogen).
The large concentration of fast-acting trap states results in the parametric shifts recovering
partially or completely when the bias is removed or reversed, such that post-stress V
T
measurements at ambient temperature can show little of the shift that was recorded at high
temperature during the stress. However, this recovery does not necessarily indicate that the
effects of the stress are entirely removed; rather, the recovery can mask the effects of the BTI
stress (the effects of BTI can return quickly under device operating conditions). Therefore,
special stress procedures are required to condition the interface such that transient effects are
observed. It is recommended that both permanent and transient effects are measured in the
BTI stress if possible. The long-term V shift during BTI and the V hysteresis before and after
T T
stress both need to be monitored to get a complete understanding of the effects of BTI stress,
and recovery effects.
4.3 Threshold voltage and hysteresis measurements
4.3.1 Comments concerning threshold voltage (V ) measurements
T
IEC 63505 provides guidelines for V measurements for SiC-based MOS devices. Guidelines
T
from IEC 63505 shall be followed for datasheet reporting of the V values for devices. What is
T
discussed here regarding measurement of the changes in V during the BTI stress might not
T
always follow those prescriptions due to system measurement limitations during BTI and the
stress procedure used, but V measurements pre- and post- BTI stress should follow those
T
guidelines as appropriate.
HYST
For SiC MOS devices the relatively large values of hysteresis in the V value (V )
T T
complicates the measurement of V , as the value measured depends on the gate bias
T
conditions before the V measurement. In general, an acceptable practice is to condition with
T
a short gate bias pulse, then measure the V using methods to be described. Details of various
T
conditioning approaches will be described in Clause 9 of this document. The V measurement
T
measurements during the BTI stress.
discussions included herein relate principally to V
T
For the case of BTI measurements, the goal is not to specifically determine a specific V value,
T
but rather to effectively measure the shift in device characteristics over time under gate bias
shift
and temperature stress. Thus, the threshold shift (∆V ) is the most important characteristic
T
to extract from the stress. However, this does require that the method for determining the V
T
value be consistent throughout the stress procedure. In the different stress procedures
described herein, different approaches are used to determine V , based on the ease of
T
measurement, and the speed at which the instruments can perform the measurements. The V
T
measurement methods in the following stress procedures are not necessarily described as ways
, but rather are a means of determining device characteristic shifts.
to report device V
T
For BTI stress, a constant-current V criteria is appropriate (as described in JESD241 [12] ), in
T
the weakly inverted region of the I -V curve, or near the onset of the linear region. A linear
D GS
V extrapolation is not useful for V measurements during BTI stress of SiC MOS devices and
T T
is not recommended. The current level defining V (I ) can be chosen as some fraction of the
T T
-4
device rated current (for example, I /I ≤ 1 × 10 ). Alternatively, it can be chosen based
T D(rated)
on the measurement equipment limitations, ensuring a current high enough to be measured
accurately (for example the uA range). Although for CMOS devices the current value used for
V can be defined in relation to the channel width over channel length (W/L), the method of
T
ensuring that the current level is well below the rated current (≥ 4 orders of magnitude lower)
accomplishes the same objective. The most straightforward approach is simply to choose the
current level for V shift evaluation during BTI from the defined V datasheet I value, typically
T T T
in the milliamp range (mA) for devices rated at tens amps or higher. To best understand the
effect of BTI shift on blocking capability, I current values lower than the datasheet values could
T
be used, such as V measured at currents in the uA level.
T
Typical approaches to measure V during BTI stress are:
T
1) fix V at a constant low value (~ 100 mV) and sweep V (V ) from the bias voltage
DS GS T(GS)
polarity towards the opposite polarity (to limit recovery) until reaching the I value as shown
T
in Figure 1 a);
2) bias gate (V ) and drain (V ) together while the source is at ground potential to reach
GS DS
the I value, termed a gated-diode method (V ) as shown in Figure 2 a) with circuit
T T(GDS)
shown in Figure 3; or
3) measure I using a constant V and constant V value in the weakly inverted region as
D DS GS
shown in Figure 4 a). The process of calculating V from the measured I at constant V
T D GS
is demonstrated by the I -V curves shown in Figure 4 b). Therefore, when using this
D GS
approach, I -V curves before and after stress are required for the V determination, and
D GS T
the V value will have some uncertainty if the I -V curve shape changes.
T D GS
___________
Numbers in square brackets refer to the Bibliography.
Any of these are acceptable approaches for V measurement during BTI, but the approach used
T
should be clearly indicated and kept the same throughout. If the measurement is done in a
current-controlled manner, the voltage at the threshold current value will be measured directly.
If a voltage-controlled gate sweep or gate bias is used, then the threshold value will need to be
interpolated between gate voltage data points, so the voltage steps should be kept sufficiently
small in a sweep.
During NBTI the gate polarity would be reversed. The conditioning pulse and VGS sweep are generally
the opposite polarity for NBTI, but a positive
conditioning can be applied for NBTI; see Figure B.5.
a) V sweep method for V determination b) Same approach for PBTI with a fixed V
GS T GS
during PBTI conditioning pulse immediately before

Figure 1 – Proposed sweep methods for NBTI and PBTI for MOSFETs

Same for PBTI and NBTI The conditioning pulse could be the same or opposite
polarity for NBTI (will give different results; see
Figure B.5.
a) Gated-diode method for V determination b) Same approach for PBTI with a fixed V
T GS
during BTI conditioning pulse immediately before

Figure 2 – Proposed sweep methods for NBTI and PBTI for gated diode configuration
Figure 3 – Circuit diagram for the V measurement using the gated-diode configuration
T
a) Constant V method for V determination during the b) Diagram showing how the changing
GS T
sensed I at constant V corresponds to V
fast drain current BTI method, shown for PBTI, the dotted D GS T
line shows the V stress changes for NBTI at the I value
GS T
Figure 4 – Sweep proposal and I vs V response for the fixed V method
D GS GS
4.3.2 V measurement and conditioning
T
Because SiC MOSFETs experience an intrinsic variation in V depending on the gate biasing
T
history of the device (and the speed of the measurement), more consistent information can be
obtained by performing a standardized conditioning procedure to stabilize the V readout. This
T
is linked with the V sense step as shown in Figure 1 b) and Figure 2 b). Without conditioning,
T
e.g., if the V is measured directly after an electrically undefined condition, the SiC/SiO
T 2
interface can be in a non-steady-state charge state at the time of the V readout leading to
T
possibly misleading results regarding the V shift evaluation. Different conditioning approaches
T
can be used, if they are kept consistent throughout the BTI stress procedure. The V
GS
conditioning can be:
a) a set V value such as a datasheet use or maximum values,
GS
b) the PBTI or NBTI V stress value used for that stress, or
GS
c) the V sweep start voltage used for the V sense if it is sufficiently far from the V value.
GS T T
At the start of the BTI stress it is recommended to perform an initial conditioning step (either
of the 3 methods just mentioned) so that the initial V will serve as an appropriate starting
T
V value for the BTI shift determination over time. The stress procedures described here
T
use all these approaches mentioned. Any of these methods are generally satisfactory, if the
process used is kept unchanged throughout the BTI stress. It should be noted that for NBTI
stress a positive or a negative conditioning pulse can be used, but the results will differ
between these approaches (see Figure B.5). Thus, stress procedures need to be explained
with each BTI dataset.
HYST
4.3.3 Threshold hysteresis (V ) and fast transient effects
T
shift
For a more complete understanding of the device BTI V characteristics measured during
T
BTI, it is useful to separate short-term transient shifts, observed either during the BTI stress
trans
(fast recovering transients (∆V ), or observed during switching the gate bias polarity during
T
HYST
V sensing (hysteresis, V ), from more permanent shift in threshold voltage (termed drift,
T T
drift trans
∆V ) that has essentially no time dependence. Fast recovering transients (∆V ) and the
T T
hysteresis in V are intrinsic features of SiC MOSFETs (these are present in any MOSFET, but
T
typically of larger magnitude in SiC devices). What is termed hysteresis here is reversible and
remains unchanged over time (a device on the shelf for any amount of time will show this V
T
hysteresis if switched). The hysteresis is a device characteristic that should be measured before
HYST
and after BTI stress; changes in the hysteresis (∆V ) would indicate that the BTI stress
T
has degraded the device.
...