IEC 63602:2026

IEC 63602 ®
Edition 1.0 2026-02
INTERNATIONAL
STANDARD
Guidelines for representing switching losses of SIC MOSFETs in datasheets

ICS 31.080.30  ISBN 978-2-8327-1046-3

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CONTENTS
FOREWORD . 2
INTRODUCTION . 4
1 Scope . 5
2 Normative references . 5
3 Terms, definitions and letter symbols . 5
3.1 Terms and definitions . 5
3.2 Letter symbols . 5
4 Description of switching losses in SiC MOSFETs . 6
5 Representation guide . 11
Bibliography . 15

Figure 1 – Schematic display of the macroscopic device capacitances exemplarily for a
MOSFET . 6
Figure 2 – Schematic display of a half bridge structure utilizing MOSFETs on high side
system (HS) and low side system (LS) . 8
Figure 3 – Schematic display of transient waveforms in a half-bridge topology for high
side system (HS) and low side system (LS is the active device) . 9
Figure 4 – Exemplary switching curve for a SiC MOSFET during reverse recovery,
showing increasing impact of parasitic turn-on of the passive switch on the high-side
turn-on losses (upper left – turn off voltage -5 V, upper right turn off voltage -2 V, lower
right turn off voltage 0 V, lower left extracted switching energies and currents related
to the values at -5 V) . 10
Figure 5 – Sketch of a characterization setup . 12
Figure 6 – Exemplary and schematic drawings . 12
Figure 7 – Exemplary and schematic drawing . 13

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Guidelines for representing switching losses
of SIC MOSFETs in datasheets
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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IEC 63602 has been prepared by IEC technical committee 47: Semiconductor devices. It is
an International Standard.
It is based upon JEDEC JEP187: Guidelines for Representing Switching Losses of SiC
MOSFETs in Datasheets. It is used with permission of the copyright holder, JEDEC Solid State
Technology Association. It was submitted as a Fast Track document.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2987/FDIS 47/2995/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
The structure and editorial rules used in this publication reflect the practice of the organization
which submitted it.
This document was developed in accordance with ISO/IEC Directives, Part 1 and ISO/IEC
Directives, IEC Supplement, available at www.iec.ch/members_experts/refdocs. The main
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stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
INTRODUCTION
This document is intended for use in the SiC power semiconductor and related power electronic
industries and provides guidelines for representation of switching losses and related
measurement conditions on SiC MOSFET device datasheets.
Switching losses are key parameters for evaluating power device performance, for
benchmarking devices of different manufacturers and deciding on the suitability of a device in
an application. Measurement and/or setup parameters can have a significant influence on the
measured switching losses. Without clear definition of the methodology used, it is not possible
to compare devices properly or, in some cases, even decide on its suitability for the target
purpose.
The purpose of this document is to point out the factors that can influence switching losses for
silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and provide
guidelines for a clean representation in datasheets.

1 Scope
This document specifies how to correctly display essential parameters of SiC-based PECS
devices having a gate dielectric region biased to turn devices on and off. This typically refers
to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are
discussed as these are dominant for power device applications; however, the procedures apply
to PMOS devices as well. In contrast to silicon power MOSFETs certain aspects of SiC power
MOSFETs require a dedicated approach in order to represent device parameters correctly in
the datasheet. Details are explained in the following paragraphs, among others the most
important topics are:
– substantially higher switching speeds ad high V ;
DS
– strong impact of test setup (see Clause 5);
– impact of body diode as a function of the applied negative gate bias ant the limitations
arising for the V values depending on the actual device.
G(off)
This document does not define device failure criteria, acceptable use conditions or acceptable
lifetime targets. That is up to the device manufacturers and users. However, it provides stress
procedures such that the threshold voltage stability over time as affected by gate bias and
temperature can be demonstrated and evaluated.
2 Normative references
There are no normative references in this document.
3 Terms, definitions and letter symbols
3.1 Terms and definitions
No terms and definitions are listed in this document.
Symbols used in this document refer partially to definitions in IEC 60747-2 and IEC 60747-8.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
– IEC Electropedia: available at https://www.electropedia.org/
– ISO Online browsing platform: available at https://www.iso.org/obp
3.2 Letter symbols
The following letter symbols are used in this document:
DUT Device Under Test
FWD Free-wheeling diode
PECS Power Electronic Conversion Semiconductor
E
Turn-on switching energy losses
ON
C
Gate-source capacitance
GS
C
Gate-drain capacitance
GD
C
Drain-source capacitance
DS
C
Input capacitance
ISS
C
Output capacitance
OSS
C
Reverse-transfer capacitance
RSS
V
Gate-source voltage applied to turn off the DUT
GS,OFF
V
Minimum value of V
GS,OFF,MIN
GS,OFF
V
Maximum value of V
GS,OFF,MAX
GS,OFF
V
Typical value of V
GS,OFF,TYP
GS,OFF
V
Recommended turn-off gate voltage in the datasheet
G,OFF,CHAR
V
Minimum turn-off gate voltage rating specified in the datasheet
GS,min
V
Gate-source voltage applied to turn off the passive switch
G,OFF(PASS)
Q
Reverse recovery charge
RR
Q
Diode capacitive charge
C
R
Gate resistance
G
R
Typical gate resistance used for datasheet characterization tests
G,TYP
R
Actual gate resistance used for datasheet characterization tests
G,char
V
Threshold voltage
GS(th)
dV/dt
Slew rate of drain-source voltage (V ) during DUT switching
DS
4 Description of switching losses in SiC MOSFETs
Switching losses for power transistors are typically measured under an inductive load in a
double pulse circuit. In this measurement, during turn-on of the device under test (DUT), the
free-wheeling diode (FWD) undergoes reverse recovery, and the reverse recovery current of
the diode flows through the DUT and contributes to its turn-on energy loss (E ). As such, the
ON
of the
reverse recovery behaviour of the FWD can have a significant influence on the E
ON
DUT [1] . Therefore, the selection of the FWD and its operating conditions should be carefully
considered for measuring E of SiC MOSFETs.
ON
Focusing on device design, every power semiconductor switch has inherent capacitances that
can be partly described as a capacitive equivalent network, as depicted in Figure 1.

Figure 1 – Schematic display of the macroscopic device
capacitances exemplarily for a MOSFET
___________
Num
...