WG 12 - TC 91/WG 12

IEC PAS 63720:2026 defines standardized routing parameter tables applicable to the design of rigid circuit board with mechanically or laser drilled vias.
These parameter tables are based on the concept of "Routing Classes" initially introduced in the French standard NF-93713 (1971-1989, cancelled: 2019). They are linked to the pitch of electronic components (e.g., BGA, QFN, connector, etc.) and thus allow a better coupling with component and circuit board manufacturers.
They can be easily integrated into EDA tools to facilitate the work of designers, while ensuring a common standard of communication between customers and manufacturers.
Routing classes should not be confused with IPC performance classes, which are used in the context of circuit board acceptance (IPC-A-600) as well as qualification and performance (IPC-6012) standards. Additional information on circuit board design is provided by IPC-2221 (Generic Standard on Printed Board Design), IPC-2222 (Sectional Design Standard for Rigid Organic Printed Boards) and IPC-2226 (Sectional Design Standard for High Density Interconnect (HDI) Printed Boards).
This document is based on French AFNOR Spec 2212 and was submitted as a PAS document.

IEC PAS 63702:2026 describes the classification of additive manufacturing and 3D-printing processes for electronics.

IEC 61188-6-3:2024 specifies the requirements for lands and land pattern on circuit boards for the mounting of components with leads by soldering based on the solder joint requirements of IEC 61191-1 and IEC 61191-3.
This part of IEC 61188 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through hole mounted components. These requirements are based on the solder joint requirements of IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.
This first edition partially cancels and replaces the IEC 61188-5 series of International Standards.
The significant technical changes with respect to the previous edition are listed in the Introduction and further detailed information and calculations can be found in Annex A.

IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

IEC 61188-6-2:2021 describes the requirements of design and use for soldering surfaces of land pattern on circuit boards. This document includes land pattern for surface mounted components. These requirements are based on the solder joint requirements of IEC 61191‑2:2017.

IEC TR 61188-8:2021(E) describes the configuration of part shape data of semiconductor devices and electrical components registered in the CAD library. This document mainly describes the configuration of 2D and 3D parts shape data.

IEC 61188-6-4:2019 specifies generic requirements for dimensional drawings of SMD from the viewpoint of land pattern design.
The purpose of this document is to prevent land pattern design issues caused by lack of information and/or misuse of the information from SMD outline drawing as well as to improve the utilization of IEC 61188 series. This document is applicable to the SMD of semiconductor devices and electrical components.

IEC 61188-7:2017 establishes a consistent technique for the description of electronic component orientation, and their land pattern geometries. This facilitates and encourages a common data capture and transfer methodology amongst and between global trading partners.
This edition includes the following significant technical changes with respect to the previous edition:
a) Figure 1 has been corrected;
b) the term “rectangle” has generally been replaced by “polygon”;
c) level B has been indicated as preferred level for new libraries.

IEC 61188-7:2009 establishes a consistent technique for the description of electronic component orientation, and their land pattern geometries. This facilitates and encourages a common data capture and transfer methodology amongst and between global trading partners.

IEC 61188-5-8:2007 provides information on land pattern geometries used for the surface attachment of electronic components with area array terminations in the form of solder balls, solder columns or protective coated lands. The intent of the information presented herein is to provide the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder joint, and also allow for inspection, testing and reworking of those solder joints.
This publication is to be read in conjunction with IEC 61188-5-1:2002.

IEC 61188-5-3:2007 provides information on land pattern geometries used for the surface attachment of electronic components with gull-wing leads on two sides. The intent of the information presented herein is to provide the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and reworking of those solder joints. Each clause contains a specific set of criteria such that the information presented is consistent, providing information on the component, the component dimensions, the solder joint design, and the land pattern dimensions.
This publication is to be read in conjunction with IEC 61188-5-1 :2002.

IEC 61188-5-5:2007 provides information on land pattern geometries used for the surface attachment of electronic components with gull-wing leads on four sides. The intent of the information presented herein is to provide the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and reworking of those solder joints.
This publication is to be read in conjunction with IEC 61188-5-1 :2002.

IEC 61188-5-4:2007 provides the component and land pattern dimensions for small outline integrated circuits with "J" leads on two sides (SOJ components) used in the reflow soldering process. Basic construction of the SOJ device is also covered. Clause 4 lists the tolerances and target solder joint dimensions used to arrive at the land pattern dimensions.

Provides information on land pattern geometries used for the surface attachment of discrete electronic components. Provides the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and rework of resulting solder joints.

Provides information on land pattern geometries used for the surface attachment of electronic components with J leads on four sides. Provides the appropriate size, shape and tolerances of surface mount land patterns so as to ensure sufficient area for the appropriate solder fillet, and also allows for inspection, testing and reworking of resulting solder joints.

The aim in packaging is to transfer a signal from one device to one or more other devices through a conductor. High-speed designs are defined as designs in which the interconnecting properties affect circuit performance and require unique considerations.

Describes those factors which control the flatness of rigid printed boards and their assemblies. This standard incorporates advice regarding design, base material, unassembled printed boards, and printed board assemblies.

Provides information on land pattern geometries used for the surface attachment of electronic components. The intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface-mount land patterns to insure sufficient area for the appropriate solder fillet, and also to allow for inspection, testing, and rework of those solder joints.