IEC 62326-20:2016

IEC 62326-20 ®
Edition 1.0 2016-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Printed boards –
Part 20: Printed circuit boards for high-brightness LEDs

Cartes imprimées –
Partie 20: Cartes de circuits imprimés destinées aux LED à haute luminosité

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IEC 62326-20 ®
Edition 1.0 2016-02
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Printed boards –
Part 20: Printed circuit boards for high-brightness LEDs

Cartes imprimées –
Partie 20: Cartes de circuits imprimés destinées aux LED à haute luminosité

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180 ISBN 978-2-8322-3152-4

– 2 – IEC 62326-20:2016 © IEC 2016
CONTENTS
FOREWORD . 6
1 Scope . 8
2 Normative references. 8
3 Terms, definitions and abbreviations . 8
3.1 Terms and definitions . 8
3.2 Abbreviations . 8
4 Classification and class of the printed circuit board for high-brightness LEDs . 9
5 Design rules and allowance . 10
5.1 Panel and board sizes . 10
5.1.1 Board size . 10
5.1.2 Allowance of dimensions . 11
5.1.3 Perforation and slit . 11
5.1.4 V-cut . 12
5.2 Total board thickness . 13
5.3 Holes . 14
5.3.1 Insertion holes and vias . 14
5.3.2 Datum hole . 16
5.3.3 Assembly hole (a through-hole without wall plating) . 16
5.4 Conductor . 17
5.4.1 Width of conductor pattern and its allowance . 17
5.4.2 Distance between conductors and its allowance . 17
5.4.3 Thickness of the insulating layer . 18
5.5 Printed contact . 18
5.5.1 Allowance of the distance between the centers of two adjacent printed
contacts . 18
5.5.2 Allowance of the terminal width of printed contacts . 19
5.5.3 Shift of the center of printed contacts on front and back sides of a board . 19
5.6 Land pattern . 20
5.6.1 Allowance of the distance between the centers of two lands . 20
5.6.2 Allowance of the width of a land . 20
5.6.3 Land diameter and its allowance for BGA/CSP . 21
5.7 Fiducial mark and mark for component positioning . 22
5.7.1 Typical form and size of the fiducial mark . 22
5.7.2 Dimensional allowance of fiducial mark and component positioning mark . 23
5.7.3 Position allowance of the component positioning mark . 23
5.8 Interlayer connection – Copper plating . 23
6 Quality . 24
6.1 Gap between conductor and the wall of a component insertion hole or a via . 24
6.2 Positional deviation between conductor layers of a multilayer board . 24
6.3 Minimum land width . 24
6.4 Surface treatment . 25
6.4.1 Gold plating for printed contact . 25
6.4.2 Other surface treatment . 26
6.5 Defects of solder resist . 26
6.6 Symbol mark . 28
6.6.1 General . 28

6.6.2 Conductor surface . 28
6.6.3 Between conductors . 28
6.6.4 Defects within insulating layers . 29
6.6.5 Routing and drilling . 30
6.6.6 Conductor pattern . 30
6.7 Land . 30
6.8 Land of a land pattern . 31
6.9 Defects in a land for BGA/CSP mounting . 32
6.10 Printed contact . 32
7 Performance and test methods . 34
7.1 Resistance of conductors . 34
7.2 Current proof of conductor and plated through hole . 35
7.3 Observation of component mountings and vias . 36
7.3.1 Observation with standard conditions . 36
7.3.2 Observation after thermal shock test . 38
8 Marking, packaging and storage . 39
8.1 Marking on a product . 39
8.2 Marking on the package . 39
8.3 Packaging and storage . 40
8.3.1 Packaging . 40
8.3.2 Storage . 40
Annex A (informative) Classification and class of the PCB for high-brightness LEDs . 41
Bibliography . 46

Figure 1 – Example of a classification and its application . 10
Figure 2 – Board arrangement in a panel .
...