IEC 62889:2024

IEC 62889 ®
Edition 2.0 2024-02
REDLINE VERSION
INTERNATIONAL
STANDARD
colour
inside
Digital video interface – Gigabit video interface for multimedia systems

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IEC 62889 ®
Edition 2.0 2024-02
REDLINE VERSION
INTERNATIONAL
STANDARD
colour
inside
Digital video interface – Gigabit video interface for multimedia systems
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 33.160.40, 33.160.60, 35.200 ISBN 978-2-8322-8271-7

– 2 – IEC 62889:2024 RLV © IEC 2024
CONTENTS
FOREWORD . 5
INTRODUCTION . 2
1 Scope . 8
2 Normative references . 8
3 Terms, definitions and abbreviated terms . 8
3.1 Terms and definitions . 8
3.2 Abbreviated terms . 11
4 Architecture . 8
5 Electrical characteristics . 12
5.1 General . 12
5.2 AC electrical specifications . 12
6 Front-end. 14
6.1.1 General . 14
6.1.2 TX Front-end . 15
6.1.3 RX Front-end . 15
6.1.4 Configuration block diagram . 15
6.1.5 Data mapping . 15
7 Transition state link . 17
8 Protocol . 18
8.1 Downstream encoder . 18
8.1.1 General . 18
8.1.2 GHDS and GLDS concatenation . 18
8.1.3 Scrambler . 18
8.1.4 5B/6B conversion . 19
8.2 Downstream decoder . 19
8.3 Upstream encoder . 20
8.3.1 GLUS concatenation . 20
8.3.2 Scrambler . 20
8.3.3 5B/6B conversion . 20
8.3.4 Upstream decoder . 20
9 Transmission system and transmission line of electrical characteristics . 21
Annex A (informative) GVIF2 multiple contents transmission . 22
Annex B (normative) GVIF standard specification . 24
B.1 Architecture . 24
B.2 Electrical characteristics . 25
B.2.1 DC electrical specifications . 25
B.2.2 AC electrical specifications . 26
B.3 Front-end . 27
B.3.1 General . 27
B.3.2 TX front-end . 27
B.3.3 RX front-end . 28
B.4 Transition state link . 28
B.5 Protocol . 29
B.5.1 General . 29
B.5.2 Encoder . 29
B.5.3 Decoder . 32

B.6 Transmission system and transmission line of electrical characteristics . 32
Annex C (informative) GVIF Multiple link application . 34
C.1 Single-link application example . 34
C.1.1 Block diagram for single-link transmission . 34
C.1.2 Data mapping of single-link transmission . 35
C.2 Multiple-link application example. 35
C.2.1 Block diagram for 2-pair parallel transmission . 35
C.2.2 Data mapping of 2-pair transmission . 36
Bibliography . 37

Figure 1 – Architecture of the GVIF2 . 12
Figure 2 – Level definition of GVIF2 . 13
Figure 3 – GVIF2 downstream eye mask (at TP1) . 13
Figure 4 – GVIF2 upstream eye mask (at TP2) . 14
Figure 5 – Front-end block diagram of GVIF2. 14
Figure 6 – GVIF2 configuration block diagram Data mapping . 15
Figure 7 – GVIF2 RGB888 data mapping . 16
Figure 8 – GVIF2 mapping for general content data(optional) . 16
Figure 9 – Transaction state diagram of GVIF2 . 17
Figure 10 – REF and WSYNC signals of GVIF2 downstream. 18
Figure 11 – WSYNC signal of upstream . 18
Figure 12 – Downstream encoding . 19
Figure 13 – Downstream decoding . 20
Figure 14 – GLUS word structure . 20
Figure 15 – Test points of GVIF2 . 21
Figure 16 – S21 template for GVIF2 transmission line . 21
Figure A.1 – GVIF2 transmission for single content . 22
Figure A.2 – GVIF2 multiplex transmission for multiple contents . 23
Figure B.1 – Architecture of the GVIF . 24
Figure B.2 – VOD and VOS diagrams . 25
Figure B.3 – Transmitter eye mask specifications (TP1) . 26
Figure B.4 – Front-end block diagram . 27
Figure B.5 – Transition state link . 29
Figure B.6 – Encoder output diagram . 30
Figure B.7 – C-format word . 31
Figure B.8 – H-format word . 32
Figure B.9 – Transmission system . 33
Figure B.10 – Transmission line tolerance impedance . 33
Figure B.11 – Transmission loss . 33
Figure C.1 – Differential single-link block diagram . 34
Figure C.2 – Pixel configuration . 35
Figure C.3 – Multiple-link application block diagram . 35
Figure C.4 – Pixel configuration when using 2-pairs . 36

– 4 – IEC 62889:2024 RLV © IEC 2024
Table 1 – AC electrical specification of GVIF2 . 13
Table 2 – 5B/6B conversion . 19
Table A.1 – GVIF2 data rate of transmission and number of the DATA SLOT . 22
Table B.1 – DC electrical specifications of the transmitter . 25
Table B.2 – DC electrical specifications of the receiver . 26
Table B.3 – AC electrical specifications of the transmitter . 26
Table B.4 – AC electrical specifications of the receiver . 27
Table B.5 – 4B/5B conversion . 31
Table B.6 – VSYNC, HSYNC, DE, CNTL/AUX, SDA, TDA transition and the
corresponding header . 32

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DIGITAL VIDEO INTERFACE –
GIGABIT VIDEO INTERFACE FOR MULTIMEDIA SYSTEMS

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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This redline version of the official IEC Standard allows the user to identify the changes
made to the previous edition IEC 62889:2015. A vertical bar appears in the margin
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– 6 – IEC 62889:2024 RLV © IEC 2024
IEC 62889 has been prepared by Technical Area 4: Digital system interfaces and protocols, of
IEC Technical Committee 100: Audio, video and multimedia systems and equipment. It is an
International Standard.
JEITA CP-6101B served as a basis for the elaboration of this document.
This second edition cancels and replaces the first edition published in 2015. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) Addition of a new technology interface, GVIF2.
The text of this International Standard is based on the following documents:
Draft Report on voting
100/3912/CDV 100/4040/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

INTRODUCTION
This International Standard is based on JEITA CP-6101B: Digital monitor interface GVIF, which
was originally specified by the Japan Electronics and Information Technology Industries
Association (JEITA).
The Gigabit Video InterFace (GVIF) is a serial point-to-point interface supporting uncompressed
digital video links that was designed to address the needs of automotive navigation and
entertainment systems, etc., to transport baseband digital video information. GVIF applies low-
voltage differential signalling (LVDS) technology and makes use of a thin cable consisting of a
single shielded twisted pair of conductors that exhibits high noise immunity and low EMI, and
is optimized for small size and low weight. GVIF supports display resolutions ranging from
WQVGA through WUXGA with a maximum of 24 bits per pixel colour video data, and can
transmit a baseband video signal over cable lengths over 10 m. Optionally, GVIF supports audio
data transmission and user data transmission.
Gigabit Video InterFace 2(GVIF2) is a baseband transmission method for digital video
information that applies serial data transmission technology. In the downstream transmission
from GVIF2 TX to GVIF2 RX, the high-bandwidth data for video information (GHDS) and the
device control signal (GLDS) are transmitted by using the time-division multiplexing method. In
the upstream transmission from GVIF2 RX to GVIF2 TX, the control signal GLUS is transmitted.
The upstream transmission and downstream transmission occur in full duplex. Optionally,
GVIF2 also supports audio data transmission and user data transmission.
Also optionally, when paired with high-bandwidth data digital content protection (HDCP), the
GVIF's standard functions and features address all of the requirements for delivering content-
protected video from a source to a video display monitor.
This document describes the GVIF family that consists of GVIF2 in the main body and Annex A,
and GVIF in Annex B and Annex C.
GVIF2 has the following features:
• transmission by a differential shielded twisted-pair cable or coaxial cable,
• to enable multiple video and audio content transmission using time-division multiplexing,
• possibility to use audio transmission, bi-direction user communication, and HDCP (high-
bandwidth digital content protection) technology (optional),
• availability for daisy chain transmission (optional).
The Association of Radio Industries and Businesses (ARIB) refers to GVIF and GVIF2 in its
standard ARIB STD-B21 as being authorized digital video output interfaces.

– 8 – IEC 62889:2024 RLV © IEC 2024
DIGITAL VIDEO INTERFACE –
GIGABIT VIDEO INTERFACE FOR MULTIMEDIA SYSTEMS

1 Scope
This document describes a two serial digital interfaces, Gigabit Video InterFace (GVIF) and
Gigabit Video InterFace2 (GVIF2), for the interconnection of digital video equipment. GVIF and
GVIF2 are primarily intended to carry high-speed digital video data for general usage and are
well suited for multimedia entertainment systems in a vehicle.
This document specifies the physical layer of the interface, including transmission line
characteristics and electrical characteristics of transmitters and receivers. Mechanical and
physical specifications of connectors are not included.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 62315-1:2003, DTV profiles for uncompressed digital video interfaces – Part 1: General
ITU-R BT.601-5, Studio encoding parameters of digital television for standard 4:3 and wide-
screen 16:9 aspect ratios
ITU-R BT.656-5, Interface for digital component video signals in 525-line and 625-line television
systems operating at the 4:2:2 level of Recommendation ITU-R BT.601
3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
• IEC Electropedia: available at https://www.electropedia.org/
• ISO Online browsing platform: available at https://www.iso.org/obp
3.1.1
DE
display enable signal given in IEC 62315-1
3.1.2
HSYNC
display horizontal synchronous signal given in IEC 62315-1
3.1.3
VSYNC
display vertical synchronous signal given in IEC 62315-1

3.1.4
RGB
display red, green, blue colour data input (TX) or output (RX) given in ITU-R BT.601-5 and ITU-
R BT.656-5
3.1.5
YU(Cb)V(Cr)
display Y, U (Cb), V (Cr) pixel data input (TX) or output (RX) given in ITU-R BT.601-5 and
ITU-R BT.656-5
3.1.5
CNTL/AUX
downstream user-defined signal or audio enable signal
3.1.6
P[23:0]
digital signal data such as 24-bit colour video data, for example RGB or YU (Cb) V (Cr) data
input (TX) or output (RX)
3.1.7
GHDS
GVIF2 High bandwidth DownStream
high-bandwidth downstream content data of the GVIF2 format
3.1.8
GLDS
GVIF2 Low bandwidth DownStream
low-bandwidth downstream control signal data of the GVIF2 format
3.1.9
GLUS
GVIF2 Low bandwidth UpStream
low-bandwidth upstream control signal data of the GVIF2 format
3.1.10
GVIF RX
circuit that receives the serial signal from a shielded-pair transmission line, decodes it and
outputs to convert converts it into the a parallel video signal
3.1.11
GVIF TX
circuit that receives the parallel video signal, and the control signals, and encodes them into
serial data to send a signal by driving a shielded-pair transmission line
3.1.12
GVIF2 RX
circuit that receives the serial signal from a shielded twisted-pair cable or coaxial cable,
decodes it and converts it into video and audio/control signals
3.1.13
GVIF2 TX
circuit that receives the video and audio/control signals, encodes them into serial data and
sends a signal by driving a shielded twisted-pair cable or coaxial cable
3.1.14
LOS
loss of signal detection signal, asserted when the differential input signal at the receiver cannot
receive be received
– 10 – IEC 62889:2024 RLV © IEC 2024
3.1.15
RX front-end
front-end block of receiver side
3.1.16
SDA
serial data down-stream signal
3.1.17
SDATA
GVIF2 serial data signal on coaxial cable transmission
3.1.18
SDATAP
down-stream positive-phase side signal of the differential serial data
3.1.19
SDATAN
down-stream negative-phase side signal of the differential serial data
3.1.20
REF
reference signal
3.1.21
REFRQP
current source positive signal for reference clock request from RX side
3.1.22
REFRQN
current source negative signal for reference clock request from RX side as well as REFRQP
3.1.23
SFTCLK
pixel clock
pixel clock for capture of the parallel video data per pixel
3.1.24
TDA
transmit data down-stream user-defined signal
3.1.25
TX front-end
front-end block of transmitter side
3.1.26
UDA
user data
up-stream user defined ancillary data signal
3.1.27
IRQ
up-stream common-mode reference request current for REFRQP/N
3.1.28
VOS
common-mode voltage amplitude of reference request

3.1.29
VOD
differential voltage amplitude for SDATAP/N
3.1.30
VDD
power supply on the transmitter side
3.1.31
V_SDATAP
single-ended voltage of SDATAP
3.1.32
V_SDATAN
single-ended voltage of SDATAN
3.1.33
TP1
transmitter end point for test point of a downstream eye mask specification
3.1.34
TP2
test point of an upstream eye mask specification
3.1.35
normalized differential voltage
voltage of transmitter output point
3.1.36
UI
normalized time unit interval of transmitter output point
3.1.37
WSYNC
word synchronized signal
3.2 Abbreviated terms
AC alternating current
DC direct current
EMI electro-magnetic interference
GVIF Gigabit Video InterFace
HDCP high-bandwidth digital content protection
LSB least significant bit
LVDS low voltage differential signalling
MSB most significant bit
PRBS pseudo random binary sequence
4 Architecture
The GVIF2 has a higher capability multimedia interface and is considered as the next generation
of GVIF, which is described in Annex B and Annex C.
The GVIF2 transmission line is a shielded twisted-pair cable with the differential characteristic
impedance Z0_diff or a coaxial cable with the characteristic impedance Z0_coax, and is

– 12 – IEC 62889:2024 RLV © IEC 2024
connected to GVIF2 RX and GVIF2 TX, with an AC coupling capacitor, and high-frequency
terminated resistor (see Figure 1). The signal path of the transmission line of GVIF2 is DC
isolated from both GVIF2 TX and GVIF2 RX. The shield of the transmission line of GVIF2 is
connected to the GND of the TX circuit and of the RX circuit.

Reproduced, with modifications, from JEITA CP-6101B, Figure 3-4, with permission from JEITA.
Figure 1 – Architecture of the GVIF2
5 Electrical characteristics
5.1 General
AC specifications described in below shall be satisfied. GVIF2 does not specify DC
specifications because the transmission architecture of GVIF2 is a complete AC coupling.
5.2 AC electrical specifications
The AC electrical specifications of the transmitter and receiver side are given in Table 1. The
definition of voltage levels are shown in Figure 2, and Figure 3 and Figure 4 show a downstream
eye mask specification at TP1 and an upstream eye mask specification at TP2 for GVIF2.

Table 1 – AC electrical specification of GVIF2
Downstream bit rate Upstream bit rate
Fdownstream_1 Fdownstream_2 Fdownstream_3 Fupstream
Gbit/s Gbit/s Gbit/s Mbit/s
Minimum 2,16 3,24 4,32 9,0
Maximum 2,4 3,6 4,8 10,0
Fupstream = Fdownstream_1/240
or Fupstream = Fdownstream_2/360
or Fupstream = Fdownstream_3/480
Reproduced, with modifications, from JEITA CP-6101B, Table 4-6, with permission from JEITA.

Reproduced from JEITA CP-6101B, Figure 4-3, with permission from JEITA.
Figure 2 – Level definition of GVIF2

Reproduced from JEITA CP-6101B, Figure 4-4, with permission from JEITA.
Figure 3 – GVIF2 downstream eye mask (at TP1)

– 14 – IEC 62889:2024 RLV © IEC 2024

Reproduced from JEITA CP-6101B, Figure 4-5, with permission from JEITA.
Figure 4 – GVIF2 upstream eye mask (at TP2)
6 Front-end
6.1.1 General
The front-end block diagram of GVIF2 is shown in Figure 5.

Reproduced from JEITA CP-6101B, Figure 5-2, with permission from JEITA.
Figure 5 – Front-end block diagram of GVIF2

6.1.2 TX Front-end
The GVIF2 TX front end consists of AC coupling capacitors, termination resistors, a downstream
driver, an upstream receiver, and connectors. The termination resistors, as the load of the
differential current from the downstream driver, generate the downstream signal voltage, and
become the high-frequency termination of the transmission line. The upstream receiver
reproduces the data extracted by the low-pass filter (LPF) from the upstream signal transmitted
by the RX.
6.1.3 RX Front-end
The GVIF2 RX front end consists of AC coupling capacitors, termination resistors, a
downstream receiver and an upstream driver. The downstream receiver reproduces the data
from the downstream signal which is transmitted from the TX and extracted by the high-pass
filter (HPF), which consists of the AC coupling capacitors and the termination resistors. The
upstream driver drives the upstream signal to the transmission line via the LPF. The upstream
signal is in frequency synchronization with the downstream signal, and the transmitted rate is
10 Mbit/s at maximum, which is proportional to the downstream rate.
6.1.4 Configuration block diagram
Downstream signal is GHDS and GLDS encoded in the downstream code, and the transmission
rate shall be selected from 2,4 Gbit/s, 3,6 Gbit/s, or 4,8 Gbit/s according to the bandwidth
required for GHDS.
GHDS shall be set by a time-division multiplexing in DATA SLOT units.
GHDS may use multiple video (and audio) contents transmission (optional, see Annex A).
Upstream signal shall be GLUS-encoded in upstream code.
Upstream and downstream shall be transmitted simultaneously (full duplex) by frequency
division.
The GVIF2 configuration block diagram data mapping is shown in Figure 6.

Reproduced from JEITA CP-6101B, Figure 3-2, with permission from JEITA.
Figure 6 – GVIF2 configuration block diagram Data mapping
6.1.5 Data mapping
6.1.5.1 RGB888 data mapping for GHDS
RGB888 data and synchronization signals VSYNC/HSYNC/DE shall be mapped into GHDS as
shown in Figure 7.
– 16 – IEC 62889:2024 RLV © IEC 2024

Reproduced from JEITA CP-6101B, Figure 8-3, with permission from JEITA.
Figure 7 – GVIF2 RGB888 data mapping
6.1.5.2 Mapping of content for other formats (optional)
MAINDATA, MAINCTRL, SUBDATA can be mapped into GHDS following the agreement of
coordination between GVIF2 TX and GVIF2 RX, as shown in Figure 8. It is recommended that
video pixel data be mapped into MAINDATA, video synchronization signals be mapped into
MAINCTRL, and audio signals (optional) be mapped into SUBDATA.

Reproduced from JEITA CP-6101B, Figure 8-4, with permission from JEITA.
Figure 8 – GVIF2 mapping for general content data(optional)
Bi-directional communication signals between GVIF2 TX and GVIF2 RX, such as UART, can be
mapped into GLDS and GLUS (optional).
Certification data for HDMI (HDCP) is recommended to be mapped into SUBDATA, GLDS,
GLUS, and a part of GHDS (optional).

7 Transition state link
The transition state diagram of GVIF2 TX and GVIF2 RX is shown in Figure 9.

Reproduced from JEITA CP-6101B, Figure C-1, with permission from JEITA.
Figure 9 – Transaction state diagram of GVIF2
In the GVIF2 TX connected to the GVIF2 RX, there are several states including a state without
down-stream signal (Idle), states transmitting a REF signal (Send REF, Wait Upstream,
Receiver Training), a state transmitting a SYNC signal (Send WSYNC), and a normal
downstream transmission state. While it shall transit from Idle to Send REF when the TX circuit
is activated, and shall transit from Wait Upstream to Receiver Training when the upstream signal
is detected, the other transitions shall occur unconditionally in the specified time. If the
upstream signal is not detected in the normal downstream transmission state or an error is
detected in the upstream signal, it shall transit to Idle.
In the GVIF2 RX connected to the GVIF2 TX, there are several states, including a state without
upstream signal (Idle, Wait Downstream, Receiver Training), states transmitting a SYNC signal
(Send WSYNC, Align Word), and a normal upstream transmission state. While it shall transit
from Idle to Waite Downstream when the RX circuit is activated, and shall transit from Wait
Downstream to Receiver Training when the down-stream signal is detected, the other
transitions shall occur unconditionally in the specified time. If the downstream signal is not
detected in the normal upstream transmission state, or an error is detected in the down-stream
signal, it shall transit to Idle.
The downstream REF and WSYNC signals output from the GVIF2 TX shall be the encoded
GHDS and GLDS (see Figure 10).

– 18 – IEC 62889:2024 RLV © IEC 2024

Reproduced from JEITA CP-6101B, Figure C-2, with permission from JEITA.
Figure 10 – REF and WSYNC signals of GVIF2 downstream
The upstream WSYNC signal output from GVIF2-RX shall be the encoded GLUS in Figure 11.

Reproduced from JEITA CP-6101B, Figure C-3, with permission from JEITA.
Figure 11 – WSYNC signal of upstream
8 Protocol
8.1 Downstream encoder
8.1.1 General
The downstream encoder shall perform operations of GHDS and GLDS concatenation,
scrambling, and the 5B/6B conversion shown in Figure 12.
8.1.2 GHDS and GLDS concatenation
The 25-bit word shall be generated with 24-bit GHDS on the MSB side and 1-bit GLDS on the
LSB side.
8.1.3 Scrambler
The part of word column which is converted to D code shall be scrambled by PRBS31
(pseudorandom binary sequence 31).

8.1.4 5B/6B conversion
The 25-bit word shall be divided into 5 bits and each 5-bit data shall be converted to the 6-bit
D code or K code in accordance with Table 2. The generated 30-bit downstream data shall be
converted to serial data and shall be transmitted to the RX leading with the MSB.
Table 2 – 5B/6B conversion
Input RD = −1 RD = +1 Input RD = −1 RD = +1
Code EDCBA abcdei Code EDCBA abcdei
D.00 00000 100111 011000 D.16 10000 011011 100100
D.01 00001 011101 100010 D.17 10001 100011
D.02 00010 101101 010010 D.18 10010 010011
D.03 00011 110001 D.19 10011 110010
D.04 00100 110101 001010 D.20 10100 001011
D.05 00101 101001 D.21 10101 101010
D.06 00110 011001 D.22 10110 011010
D.07 00111 111000 000111 D.23 10111 111010 000101
D.08 01000 111001 000110 D.24 11000 110011 001100
D.09 01001 100101 D.25 11001 100110
D.10 01010 010101 D.26 11010 010110
D.11 01011 110100 D.27 11011 110110 001001
D.12 01100 001101 D.28 11100 001110
D.13 01101 101100 D.29 11101 101110 010001
D.14 01110 011100 D.30 11110 011110 100001
D.15 01111 010111 101000 D.31 11111 101011 010100
K.28 11100 001111 110000
Reproduced from JEITA CP-6101B, Table D.1-1, with permission from JEITA.

Reproduced from JEITA CP-6101B, Figure D.1-1, with permission from JEITA.
Figure 12 – Downstream encoding
8.2 Downstream decoder
The decoder shall perform reverse operation of the downstream encoder, that is 6-bit to 5-bit
reverse conversion, descrambling, and GHDS/GLDS decomposition, as shown in Figure 13.

– 20 – IEC 62889:2024 RLV © IEC 2024

Reproduced from JEITA CP-6101B, Figure D.1-2, with permission from JEITA.
Figure 13 – Downstream decoding
8.3 Upstream encoder
8.3.1 GLUS concatenation
GLUS data includes 4-bit length GLUS0, updated 8 times, 1-bit length GLUS1 and GLUS2,
updated twice, and 1-bit length GLUS3, GLUS4, GLUS5 and CHK (checksum), updated once,
for every 4,8 µs. The GLUS data shall be compiled as shown in the Figure 14 to generate a 40-
bit GLUS word.
Reproduced from JEITA CP-6101B, Figure D.1-3, with permission from JEITA.
Figure 14 – GLUS word structure
8.3.2 Scrambler
The part of word column which is converted to D code shall be scrambled by PRBS7
(pseudorandom binary sequence 7).
8.3.3 5B/6B conversion
The 40-bit word is divided into 5 bits and each 5-bit data is converted into the 6-bit D code, in
accordance with Table 2. The generated 48-bit length upstream data is converted to serial data
and shall be transmitted to GVIF2 TX, with a leading MSB.
8.3.4 Upstream decoder
The decoder shall perform the reverse operation of the upstream encoder, which is 6-bit to 5-bit
reverse conversion, descrambling, and decomposition into GLUS 0 to 5.

9 Transmission system and transmission line of electrical characteristics
The transmission line characteristics of GVIF2 are defined by the TP1 and TP2 (test points) in
Figure 15.
Reproduced from JEITA CP-6101B, Figure 9-4, with permission from JEITA.
Figure 15 – Test points of GVIF2
The shielded twisted-pair cable and coaxial cable (TP1 to TP2) should meet the S21 template
in Figure 16.
Reproduced from JEITA CP-6101B, Figure 9-5, with permission from JEITA.
Figure 16 – S21 template for GVIF2 transmission line

– 22 – IEC 62889:2024 RLV © IEC 2024
Annex A
(informative)
GVIF2 multiple contents transmission
The GVIF2 downstream signal is in the unit of DATA FRAME, and the DATA FRAME has the
number of DATA SLOTs specified in Table A.1. The DATA SLOT is one word (24 bits) of GHDS,
in which video (and audio: optional) contents are mapped.
Data of different contents can be mapped to each DATA SLOT. In GVIF2 TX, each content is
assigned the required number (fixed number) of DATA SLOTs to each DATA FRAME according
to its content data bandwidth. Content data is packed into a DATA SLOT through data FIFO,
but if the data FIFO is empty, the assigned DATA SLOT is padded with NULL SLOT. In GVIF2
RX, the content to be used for display is extracted from the assigned DATA SLOT and stored
in the data FIFO shown in Figure A.1 and Figure A.2.
By stacking TX and RX of GVIF2 in multiple stages, it is possible to form a daisy chain that
simultaneously transmits multiple contents with a shielded twisted-pair cable or a single coaxial
cable (optional).
Table A.1 – GVIF2 data rate of transmission and number of the DATA SLOT
Downstream bit rate DATA SLOT/DATA FRAME
2,4 Gbit/s 8
3,6 Gbit/s 12
4,8 Gbit/s 16
Reproduced from JEITA CP-6101B, Table 3-1, with permission
from JEITA.
Reproduced from JEITA CP-6101B, Figure 3-5, with permission from JEITA.
Figure A.1 – GVIF2 transmission for single content

Reproduced from JEITA CP-6101B, Figure 3-6, with permission from JEITA.
Figure A.2 – GVIF2 multiplex transmission for multiple contents

– 24 – IEC 62889:2024 RLV © IEC 2024
Annex B
(normative)
GVIF standard specification
B.1 Architecture
Figure B.1 illustrates the architecture of the GVIF. The fundamental operation of the GVIF is a
simultaneous bi-directional data transmission technology, in which the low-voltage differential
signal is transmitted down from the transmitter side to the receiver side, and the common-mode
voltage signal is transmitted up from the receiver side to the transmitter side through a shielded
twisted differential pair cable.
The shielded twisted-pair transmission line has the characteristic impedance Z (see
Figure B.1), the line is terminated to VDD by RT of (50 ± 15) Ω on the transmitter side, and is
terminated carrying differential data in RL of (100 ± 5) Ω on the receiver side.

where
RT are the pull-up terminated load resistors on the transmitter side (50 ± 15) Ω;
Z is the characteristic impedance of the shielded twisted-pair transmission line;
RL is the terminated resistor between differential data lines on the receiver side (100 ± 5) Ω;
C are AC coupling capacitors.
SDATAP/SDATAN are the downstream positive and negative phases side signals carrying differential serial data.
REFRQP (UDAP)/REFRQN (UDAN) is the upstream REFREQ common-mode current signal or UDA com
...