IEC 60749-5:2017

IEC 60749-5 ®
Edition 2.0 2017-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –
Part 5: Steady-state temperature humidity bias life test

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques
et climatiques –
Partie 5: Essai continu de durée de vie sous température et humidité avec
polarisation
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IEC 60749-5 ®
Edition 2.0 2017-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –

Part 5: Steady-state temperature humidity bias life test

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques

et climatiques –
Partie 5: Essai continu de durée de vie sous température et humidité avec

polarisation
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-7379-1

– 2 – IEC 60749-5:2017 © IEC 2017
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 General . 5
5 Equipment . 6
5.1 Equipment summary . 6
5.2 Temperature and relative humidity . 6
5.3 Devices under stress . 6
5.4 Minimizing release of contamination . 6
5.5 Ionic contamination . 6
5.6 Deionized water . 6
6 Test conditions . 6
6.1 Test conditions summary . 6
6.2 Temperature, relative humidity and duration . 6
6.3 Biasing guidelines . 7
6.4 Biasing choice and reporting . 7
7 Procedures . 8
7.1 Mounting . 8
7.2 Ramp-up . 8
7.3 Ramp-down . 8
7.4 Test clock . 8
7.5 Bias . 8
7.6 Read-out . 8
7.7 Handling . 9
8 Failure criteria . 9
9 Safety . 9
10 Summary . 9

Table 1 – Temperature, relative humidity and duration . 6
Table 2 – Criteria for choosing continuous or cyclical bias . 8

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 5: Steady-state temperature humidity bias life test

FOREWORD
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International Standard IEC 60749-5 has been prepared by IEC technical committee 47:
Semiconductor devices.
This second edition cancels and replaces the first edition published in 2003. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) correction of an error in an equation;
b) inclusion of notes for guidance;
c) clarification of the applicability of test conditions.

– 4 – IEC 60749-5:2017 © IEC 2017
This bilingual version (2019-09) corresponds to the monolingual English version, published in
2017-04.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47/2367/FDIS 47/2383/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
The French version of this standard has not been voted upon.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 60749 series, published under the general title Semiconductor
devices – Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 5: Steady-state temperature humidity bias life test

1 Scope
This part of IEC 60749 provides a steady-state temperature and humidity bias life test for the
purpose of evaluating the reliability of non-hermetic packaged solid-state devices in humid
environments.
This test method is considered destructive.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 60749-4, Semiconductor devices – Mechanical and climatic test methods – Part 4: Damp
heat, steady-state, highly accelerated stress test (HAST)
3 Terms and definitions
No terms and definitions are listed in this document.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
4 General
This test employs conditions of temperature, humidity and bias which accelerate the
penetration of moisture through the external protective material (encapsulant or seal) or along
the interface between the external protective material and the metallic conductors which pass
through it.
Where both this steady-state, humidity bias test and the damp heat, highly accelerated stress
test (HAST) of IEC 60749-4 are performed, the results of this 85 °C/85 % RH steady-state test
will take priority over the results of the HAST test, which is an accelerated test designed to
activate the same failure mechanisms.

– 6 – IEC 60749-5:2017 © IEC 2017
5 Equipment
5.1 Equipment summary
The test requires a temperature-humidity test chamber capable of maintaining a specified
temperature and relative humidity continuously, while providing electrical connections to the
devices under test in a specified biasing configuration.
5.2 Temperature and relative humidity
The chamber shall be capable of providing controlled conditions of temperature and relative
humidity during ramp-up to, and ramp-down from the specified test conditions.
Care should be taken to ensure that the test chamber dry bulb temperature exceeds the wet
bulb temperature at all times.
5.3 Devices under stress
Devices under stress shall be physically located to minimize temperature gradients.
5.4 Minimizing release of contamination
Care shall be exercised in the choice of board and socket materials, to minimize release of
contamination, and to minimize degradation due to corrosion and other mechanisms.
5.5 Ionic contamination
The test apparatus (card cage, test boards, sockets, wiring, storage containers, etc.) shall be
controlled to avoid ionic contamination of the test devices.
5.6 Deionized water
Deionized water with a minimum resistivity of 1 × 10 Ωm at room temperature shall be used.
6 Test conditions
6.1 Test conditions summary
Test conditions consist of a temperature, relative humidity, and duration used in conjunction
with an electrical bias configuration specific to the device.
6.2 Temperature, relative humidity and duration
Unless otherwise required by the detail specification, the temperature, relative humidity and
test duration as shown in Table 1 shall be applied.
Table 1 – Temperature, relative humidity and duration
b c
Temperature Relative Temperature Vapour Duration
a b
(dry bulb) humidity (wet bulb) pressure
°C % °C kPa h
−24
85 ± 2 85 ± 5 81,0 49,1 1 000
+168
a
Tolerances apply to the entire useable test area.
b
For information only.
c
The test conditions are to be applied continuously, except during any interim readouts, when the devices
should be returned to stress within the time specified in 7.6.

6.3 Biasing guidelines
Apply bias according to the following guidelines:
a) Minimize power dissipation.
b) Alternate pin bias as much as possible.
c) Distribute potential differences across chip metallization as much as possible.
d) Maximize voltage within operating range.
NOTE The priority of the above guidelines depends on the mechanism and specific device characteristics.
e) Either of two kinds of bias can be used to satisfy these guidelines, whichever is more
severe:
1) Continuous bias
The DC bias shall be applied continuously. Continuous bias is more severe than cycled
bias when the virtual junction temperature is <10 °C higher than the chamber ambient
temperature or, if the virtual junction temperature is not known when the heat
dissipation of the device under test (DUT) is less than 200 mW. If the heat dissipation
of the DUT exceeds 200 mW, then the virtual junction temperature should be
calculated. If the virtual junction temperature exceeds the chamber ambient
temperature by more than 5 °C then the virtual junction temperature rise above the
chamber ambient should be included in reports of test results since acceleration of
failure mechanisms will be affected.
NOTE 2 Based on the power dissipation and the thermal resistance or impedance that corresponds to the
mode of operation, the virtual junction temperature can be calculated from the formula T = T + (P x R )
j case th
or T = T + (P x R )
j amb th
where
T is the virtual junction temperature;
j
P is the power dissipation;
R is the thermal resistance.
th
2) Cycled bias
The DC voltage applied to the devices under test shall be periodically interrupted with
an appropriate frequency and duty cycle. If the biasing configuration results in a
temperature rise above the chamber ambient, ∆T , exceeding 10 °C, then cycled bias,
ja
when optimized for a specific device type, will be more severe than continuous bias.
Heating as a result of power dissipation tends to drive moisture away from the die and
thereby hinders moisture-related failure mechanisms. Cycled bias permits moisture
collection on the die during the off periods when device power dissipation does not
occur. Cycling the DUT bias with 1 h on and 1 h off is optimal for most plastic-
encapsulated microcircuits. The virtual junction temperature, as calculated on the
basis of the known thermal impedance and dissipation, should be quoted with the
results whenever it exceeds the chamber ambient by 5 °C or more.
6.4 Biasing choice and reporting
Criteria for choosing continuous or cyclical bias, and whether or not to report the amount by
which the virtual junction temperature exceeds the chamber ambient temperature, are
summarized in Table 2.
____________
The virtual junction temperature is the theoretical temperature which is based on a simplified representation of
the thermal and electrical behaviour of the semiconductor device.

– 8 – IEC 60749-5:2017 © IEC 2017
Table 2 – Criteria for choosing continuous or cyclical bias
Continuous or cyclical
Include value of ∆T
ja
∆T
ja
bias
in test report?
∆T < 5 °C or power per DUT < 200 mW Continuous No
ja
(∆T ≥ 5 °C or power per DUT ≥ 200 mW),
ja
Continuous Yes
and ∆T < 10 °C
ja
a
Cyclical Yes
∆T ≥ 10 °C
ja
a
Cycling the DUT bias with one hour on and one hour off is optimal for most plastic-encapsulated
microcircuits.
7 Procedures
7.1 Mounting
The test devices shall be mounted in such a way as to expose them to a specified condition of
temperature and humidity as given in Table 1 with a specified electrical biasing condition.
Exposure of devices to excessively hot conditions, dry ambient conditions or conditions that
result in condensation on devices and electrical fixtures shall be avoided, particularly during
ramp-up and ramp-down.
7.2 Ramp-up
The time to reach stable temperature and relative humidity conditions should be less than 3 h.
Condensation shall be avoided by ensuring that the test chamber (dry bulb) temperature
exceeds the wet-bulb temperature at all times.
7.3 Ramp-down
Ramp-down should not exceed 3 h. Condensation shall be avoided by ensuring that the test
chamber (dry bulb) temperature exceeds the wet-bulb temperature at all times.
NOTE For a DUT with a cavity in the package, condensation can occur due to the length of the ramp down time.
7.4 Test clock
The test clock starts when the temperature and relative humidity reach the set points, and
stops at the beginning of ramp-down.
7.5 Bias
Bias application during ramp-up and ramp-down is optional. Bias should be verified after
devices are loaded, prior to the start of the test clock. Bias should also be verified after the
test clock stops, but before devices are removed from the chamber.
7.6 Read-out
An electrical test shall be performed not later than 48 h after the end of ramp-down.
For intermediate read-outs, devices should be returned to stress within 96 h of the end of
ramp-down. Moisture loss can be reduced by placing the device in a moisture barrier bag
sealed in ambient air without vacuum or desiccant. When devices are placed in sealed bags,
the “test window clock” runs at one-third of the rate of devices exposed to laboratory ambient
conditions. Thus the test window can be extended to as much as 144 h, and the time to return
...