IEC 60749-26:2018

IEC 60749-26 ®
Edition 4.0 2018-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –
Part 26: Electrostatic discharge (ESD) sensitivity testing – Human body model
(HBM)
Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –
Partie 26: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle du
corps humain (HBM)
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IEC 60749-26 ®
Edition 4.0 2018-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –

Part 26: Electrostatic discharge (ESD) sensitivity testing – Human body model

(HBM)
Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –

Partie 26: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle du

corps humain (HBM)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-5256-7

– 2 – IEC 60749-26:2018 © IEC 2018
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Apparatus and required equipment . 10
4.1 Waveform verification equipment . 10
4.2 Oscilloscope . 11
4.3 Additional requirements for digital oscilloscopes . 11
4.4 Current transducer (inductive current probe) . 11
4.5 Evaluation loads . 11
4.6 Human body model simulator . 12
4.7 HBM test equipment parasitic properties . 12
5 Stress test equipment qualification and routine verification . 12
5.1 Overview of required HBM tester evaluations . 12
5.2 Measurement procedures . 13
5.2.1 Reference pin pair determination . 13
5.2.2 Waveform capture with current probe . 13
5.2.3 Determination of waveform parameters . 14
5.2.4 High voltage discharge path test . 17
5.3 HBM tester qualification . 17
5.3.1 HBM ESD tester qualification requirements . 17
5.3.2 HBM tester qualification procedure . 17
5.4 Test fixture board qualification for socketed testers . 18
5.5 Routine waveform check requirements . 19
5.5.1 Standard routine waveform check description . 19
5.5.2 Waveform check frequency . 19
5.5.3 Alternate routine waveform capture procedure . 20
5.6 High voltage discharge path check . 20
5.6.1 Relay testers . 20
5.6.2 Non-relay testers . 20
5.7 Tester waveform records. 20
5.7.1 Tester and test fixture board qualification records . 20
5.7.2 Periodic waveform check records . 20
5.8 Safety . 21
5.8.1 Initial set-up . 21
5.8.2 Training . 21
5.8.3 Personnel safety . 21
6 Classification procedure . 21
6.1 Devices for classification . 21
6.2 Parametric and functional testing . 21
6.3 Device stressing . 21
6.4 Pin categorization . 22
6.4.1 General . 22
6.4.2 No connect pins . 22
6.4.3 Supply pins . 23
6.4.4 Non-supply pins . 23

6.5 Pin groupings . 24
6.5.1 Supply pin groups . 24
6.5.2 Shorted non-supply pin groups . 24
6.6 Pin stress combinations . 24
6.6.1 Pin stress combination categorization . 24
6.6.2 Non-supply and supply to supply combinations (1, 2, … N) . 26
6.6.3 Non-supply to non-supply combinations . 27
6.7 HBM stressing with a low-parasitic simulator . 28
6.7.1 Low-parasitic HBM simulator . 28
6.7.2 Requirements for low parasitics . 28
6.8 Testing after stressing . 28
7 Failure criteria . 28
8 Component classification . 28
Annex A (informative) HBM test method flow chart . 30
Annex B (informative) HBM test equipment parasitic properties . 33
B.1 Optional trailing pulse detection equipment / apparatus . 33
B.2 Optional pre-pulse voltage rise test equipment . 34
B.3 Open-relay tester capacitance parasitics . 36
B.4 Test to determine if an HBM simulator is a low-parasitic simulator . 36
Annex C (informative) Example of testing a product using Table 2, Table 3, or Table 2
with a two-pin HBM tester . 38
C.1 General . 38
C.2 Procedure A (following Table 2): . 39
C.3 Alternative procedure B (following Table 3): . 40
C.4 Alternative procedure C (following Table 2): . 41
Annex D (informative) Examples of coupled non-supply pin pairs . 43
Annex E (normative) Cloned non-supply (I/O) pin sampling test method . 44
E.1 Purpose and overview . 44
E.2 Pin sampling overview and statistical details . 44
E.3 IC product selections . 45
E.4 Randomly selecting and testing cloned I/O pins . 46
E.5 Determining if sampling can be used with the supplied Excel spreadsheet . 46
E.5.1 Using the supplied Excel spreadsheet . 46
E.5.2 Without using the Excel spreadsheet . 46
E.6 HBM testing with a sample of cloned I/O pins . 46
E.7 Examples of testing with sampled cloned I/Os . 47
Bibliography . 50

Figure 1 – Simplified HBM simulator circuit with loads . 12
Figure 2 – Current waveform through shorting wires . 15
Figure 3 – Current waveform through a 500 Ω resistor . 16
Figure 4 – Peak current short circuit ringing waveform . 17
Figure A.1 – HBM test method flow chart (1 of 3) . 30
Figure B.1 – Diagram of trailing pulse measurement setup. 33
Figure B.2 – Positive stress at 4 000 V . 34
Figure B.3 – Negative stress at 4 000 V . 34

– 4 – IEC 60749-26:2018 © IEC 2018
Figure B.4 – Illustration of measuring voltage before HBM pulse with a Zener diode or
a device . 35
Figure B.5 – Example of voltage rise before the HBM current pulse across a 9,4 V
Zener diode . 35
Figure B.6 – Diagram of a 10-pin shorting test device showing current probe . 37
Figure C.1 – Example to demonstrate the idea of the partitioned test . 38
Figure E.1 – SPL, V1, VM, and z with the Bell shape distribution pin failure curve . 45
Figure E.2 – I/O sampling test method flow chart . 49

Table 1 – Waveform specification . 19
Table 2 – Preferred pin combinations sets . 25
Table 3 – Alternative pin combinations sets . 26
Table 4 – HBM ESD component classification levels . 29
Table C.1 – Product testing in accordance with Table 2 . 40
Table C.2 – Product testing in accordance with Table 3 . 41
Table C.3 – Alternative product testing in accordance with Table 2 . 42

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 26: Electrostatic discharge (ESD) sensitivity testing –
Human body model (HBM)
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
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Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60749-26 has been prepared by IEC technical committee 47:
Semiconductor devices in collaboration with technical committee 101: Electrostatics.
This fourth edition cancels and replaces the third edition published in 2013. This edition
constitutes a technical revision. This standard is based upon ANSI/ESDA/JEDEC JS-001-
2014. It is used with permission of the copyright holders, ESD Association and JEDEC Solid
state Technology Association.
This edition includes the following significant technical changes with respect to the previous
edition:
a) a new subclause relating to HBM stressing with a low parasitic simulator is added,
together with a test to determine if an HBM simulator is a low parasitic simulator;

– 6 – IEC 60749-26:2018 © IEC 2018
b) a new subclause is added for cloned non-supply pins and a new annex is added for
testing cloned non-supply pins.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47/2438/FDIS 47/2454/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 60749 series, published under the general title Semiconductor
devices – Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 26: Electrostatic discharge (ESD) sensitivity testing –
Human body model (HBM)
1 Scope
This part of IEC 60749 establishes the procedure for testing, evaluating, and classifying
components and microcircuits according to their susceptibility (sensitivity) to damage or
degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD).
The purpose of this document is to establish a test method that will replicate HBM failures and
provide reliable, repeatable HBM ESD test results from tester to tester, regardless of
component type. Repeatable data will allow accurate classifications and comparisons of HBM
ESD sensitivity levels.
ESD testing of semiconductor devices is selected from this test method, the machine model
(MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series.
Unless otherwise specified, this test method is the one selected.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
associated non-supply pin
non-supply pin (typically an I/O pin) associated with a supply pin group
Note 1 to entry A non-supply pin is considered to be associated with a supply pin group if either:
a) the current from the supply pin group (i.e., VDDIO) is required for the function of the electrical circuit(s)
(I/O driver) that connect(s) (high/low impedance) to that non-supply pin;
b) a parasitic path exists between non-supply and supply pin group (e.g., open-drain type non-supply pin to a
VCC supply pin group that connects to a nearby N-well guard ring).

– 8 – IEC 60749-26:2018 © IEC 2018
3.2
cloned non-supply (I/O) pin
set of input, output or bidirectional pins using the same I/O cell and electrical schematic and
sharing the same associated supply pin group(s) including ESD power clamp(s)
3.3
component
item such as a resistor, diode, transistor, integrated circuit or hybrid circuit
3.4
component failure
condition in which a tested component does not meet one or more specified static or dynamic
data sheet parameters
3.5
coupled non-supply pin pair
two pins that have an intended direct current path (such as a pass gate or resistors, such as
differential amplifier inputs, or low voltage differential signalling (LVDS) pins), including
analogue and digital differential pairs and other special function pairs (e.g., D+/D-,
XTALin/XTALout, RFin/RFout, TxP/TxN, RxP/RxN, CCP_DP/CCN_DN, etc.)
3.6
data sheet parameters
static and dynamic component performance data supplied by the component manufacturer or
supplier
3.7
withstand voltage
highest voltage level that does not cause device failure
Note 1 to entry: The device passes all tested lower voltages (see failure window).
3.8
failure window
intermediate range of stress voltages that can induce failure in a particular device type, when
the device type can pass some stress voltages both higher and lower than this range
Note 1 to entry: A component with a failure window can pass a 500 V test, fail a 1 000 V test and pass a 2 000 V
test. The withstand voltage of such a device is 500 V.
3.9
human body model electrostatic discharge
HBM ESD
ESD event meeting the waveform criteria specified in this document, approximating the
discharge from the fingertip of a typical human being to a grounded device
3.10
HBM ESD tester
HBM simulator
equipment that applies an HBM ESD to a component
3.11
I
ps
peak current value determined by the current at time t on the linear extrapolation of the
max
exponential current decay curve, based on the current waveform data over a 40 nanosecond

period beginning at t
max
SEE: Figure 2 a).
3.12
I
psmax
highest current value measured including the overshoot or ringing components due to internal
test simulator RLC parasitics
SEE: Figure 2 a).
3.13
no connect pin
package interconnection that is not electrically connected to a die
EXAMPLE: Pin, bump, ball interconnection.
Note 1 to entry: There are some pins which are labelled as no connect, which are actually connected to the die
and should not be classified as a no connect pin.
3.14
non-socketed tester
HBM simulator that makes contact to the device under test (DUT) pins (or balls, lands, bumps
or die pads) with test probes rather than placing the DUT in a socket
3.15
non-supply pin
pin that is not categorized as a supply pin or no connect
Note 1 to entry This includes pins such as input, output, offset adjusts, compensation, clocks, controls, address,
data, Vref pins and VPP pins on EPROM memory. Most non-supply pins transmit or receive information such as
digital or analogue signals, timing, clock signals, and voltage or current reference levels.
3.16
package plane
low impedance metal layer built into an IC package connecting a group of bumps or pins
(typically power or ground)
Note 1 to entry: There may be multiple package planes (sometimes referred to as islands) for each power and
ground group.
3.17
pre-pulse voltage
voltage occurring at the device under test (DUT) just prior to the generation of the HBM
current pulse
SEE: Clause B.2.
3.18
pulse generation circuit
dual polarity pulse source circuit network that produces a human body discharge current
waveform
Note 1 to entry The circuit network includes a pulse generator with its test equipment internal path up to the
contact pad of the test fixture. This circuit is also referred to as dual polarity pulse source.
3.19
ringing
high frequency oscillation superimposed on a waveform
3.20
shorted non-supply pin
any non-supply pin (typically an I/O pin) that is metallically connected (typically < 3 Ω) on the
chip or within the package to another non-supply pin (or set of non-supply pins)

– 10 – IEC 60749-26:2018 © IEC 2018
3.21
socketed tester
HBM simulator that makes contact to DUT pins (or balls, lands, bumps or die pads) using a
DUT socket mounted on a test fixture board
3.22
spurious current pulse
small HBM shaped pulse that follows the main current pulse, and is typically defined as a
percentage of I
psmax
3.23
step-stress hardening
ability of a component subjected to increasing ESD voltage stresses to withstand higher
stress levels than a similar component not previously stressed
EXAMPLE: A component can fail at 1 000 V if subjected to a single stress, but fail at 3 000 V if stressed
incrementally from 250 V.
3.24
supply pin
any pin that provides current to a circuit
Note 1 to entry: Supply pins typically transmit no information (such as digital or analogue signals, timing, clock
signals, and voltage or current reference levels). For the purpose of ESD testing, power and ground pins are
treated as supply pins.
3.25
test fixture board
specialized circuit board, with one or more component sockets, which connects the DUT(s) to
the HBM simulator
3.26
t
max
time when I is at its maximum value (I )
ps psmax
SEE: Figure 2 a).
3.27
trailing current pulse
current pulse that occurs after the HBM current pulse has decayed
Note 1 to entry: A trailing current pulse is a relatively constant current often lasting for hundreds of microseconds.
SEE: Clause B.1.
3.28
two-pin HBM tester
low parasitic HBM simulator that tests DUTs in pin pairs where floating pins are not connected
to the simulator thereby eliminating DUT-tester interactions from parasitic tester loading of
floating pins
4 Apparatus and required equipment
4.1 Waveform verification equipment
All equipment used to evaluate the tester shall be calibrated in accordance with the
manufacturer's recommendation. This includes the oscilloscope, current transducer and high
voltage resistor load. Maximum time between calibrations shall be one year. Calibration shall
be traceable to national or international standards.

Equipment capable of verifying the pulse waveforms defined in this standard test method
includes, but is not limited to, an oscilloscope, evaluation loads and a current transducer.
4.2 Oscilloscope
A digital oscilloscope is recommended but analogue oscilloscopes are also permitted. In order
to ensure accurate current waveform capture, the oscilloscope shall meet the following
requirements:
a) minimum sensitivity of 100 mA per major division when used in conjunction with the
current transducer specified in 4.4;
b) minimum bandwidth of 350 MHz;
c) for analogue scopes, minimum writing rate of one major division per nanosecond.
4.3 Additional requirements for digital oscilloscopes
Where a digital oscilloscope is used, the following additional requirements apply:
a) recommended channels: 2 or more;
b) minimum sampling rate: 10 samples per second;
c) minimum vertical resolution: 8-bit;
d) minimum vertical accuracy: ± 2,5 %;
e) minimum time base accuracy: 0,01 %;
f) minimum record length: 10 points.
4.4 Current transducer (inductive current probe)
a) minimum bandwidth of 200 MHz;
b) peak pulse capability of 12 A;
c) rise time of less than 1 ns;
d) capable of accepting a solid conductor as specified in 4.5;
e) provides an output voltage per signal current as required in 4.2
(this is usually between 1 mV/mA and 5 mV/mA.);
f) low-frequency 3 dB point below 10 kHz (e.g., Tektronix CT-2 ) for measurement of decay
constant t (see 5.2.3.2, Table 1, and note below).
d
NOTE Results using a current probe with a low-frequency 3 dB point of 25 kHz (e.g., Tektronix CT-1 ) to
measure decay constant t are acceptable if t is found to be between 130 ns and 165 ns.
d d
4.5 Evaluation loads
Two evaluation loads are necessary to verify the tester functionality:
2 2
a) Load 1: A solid 18 AWG to 24 AWG (non-US standard wire size 0,25 mm to 0,75 mm
cross-section) tinned copper shorting wire as short as practicable to span the distance
between the two farthest pins in the socket while passing through the current probe or
long enough to pass through the current probe and contacted by the probes of the non-
socketed tester.
b) Load 2: A (500 ± 5) Ω, minimum 4 000 V voltage rating.
___________
Tektronix CT-1 and CT-2 are the trade names of products supplied by Tektronix, Inc.
This information is given for the convenience of users of this document and does not constitute an endorsement
by IEC of the products named. Equivalent products may be used if they can be shown to lead to the same
results.
– 12 – IEC 60749-26:2018 © IEC 2018
4.6 Human body model simulator
A simplified schematic of the HBM simulator or tester is given in Figure 1. The performance of
the tester is influenced by parasitic capacitance and inductance. Thus, construction of a tester
using this schematic does not guarantee that it will provide the HBM pulse required for this
document. The waveform capture procedures and requirements described in Clause 5
determine the acceptability of the equipment for use.
Dual polarity
pulse source
Terminal
S1
R1 ≥ 1 MΩ R2 ∼ 1 500 Ω
A
Dual
polarity HV
C1 ∼ 100 pF
supply
Terminal
B
Current
probes
IEC
Figure 1 – Simplified HBM simulator circuit with loads
The charge removal circuit shown in Figure 1 ensures a slow discharge of the device, thus
avoiding the possibility of a charged device model discharge. A simple example is a 10 kΩ or
larger resistor (possibly in series with a switch) in parallel with the test fixture board. This
resistor may also be useful to control parasitic pre-pulse voltages (See Annex B). The dual
polarity pulse generator (source) shall be designed to avoid recharge transients and double
pulses. It should be noted that reversal of terminals A and B to achieve dual polarity
performance is not permitted. Stacking of DUT socket adapters (piggybacking or insertion of
secondary sockets into the main test socket) is allowed only if the secondary socket waveform
meets the requirements of this document defined in Table 1.
NOTE 1 The current transducers (probes) are specified in 4.4.
NOTE 2 The shorting wire (short) and 500 Ω resistor (R4) are evaluation loads specified in 4.5.
NOTE 3 Component values are nominal.
4.7 HBM test equipment parasitic properties
Some HBM simulators have been found to falsely classify HBM sensitivity levels due to
parasitic artifacts or uncontrolled voltages unintentionally built into the HBM simulators.
Methods for determining if these effects are present and optional mitigation techniques are
described in Annex B. Two-pin HBM testers and non-socketed testers may have smaller
parasitic capacitances and may reduce the effects of tester parasitics by contacting only the
pins being stressed.
5 Stress test equipment qualification and routine verification
5.1 Overview of required HBM tester evaluations
The HBM tester and test fixture boards shall be qualified, re-qualified, and periodically verified
as described in Clause 5. The safety precautions described in 5.8 shall be followed at all
times.
Charge
removal
circuit
Test
fixture
board
Short
R4 =
500 Ω
DUT
5.2 Measurement procedures
5.2.1 Reference pin pair determination
The two pins of each socket on a test fixture board which make up the reference pin pair are:
a) the socket pin with the shortest wiring path of the test fixture to the pulse generation
circuit (terminal B) and
b) the socket pin with the longest wiring path of the test fixture from the pulse generation
circuit (terminal A) to the ESD stress socket (See Figure 1).
This information is typically provided by the equipment or test fixture board manufacturer. If
more than one pulse generation circuit is connected to a socket then there will be more than
one reference pin pair.
It is strongly recommended that on non-positive clamp fixtures, feed-through test point pads
be added on these paths to allow connection of either the shorting wire or 500 Ω load resistor
during waveform verification measurements. These test points should be added as close as
possible to the socket(s), and if the test fixture board uses more than one pulse generator,
multiple feed-through test points should be added for each pulse generator’s longest and
shortest paths.
NOTE A positive clamp test socket is a zero insertion force (ZIF) socket with a clamping mechanism. It allows the
shorting wire to be easily clamped into the socket. Examples are dual in-line package (DIP) and pin grid array
(PGA) ZIF sockets.
5.2.2 Waveform capture with current probe
5.2.2.1 General
To capture a current waveform between two socket pins (usually the reference pin pair), use
the shorting wire (see 4.5, Load 1) for the short circuit measurement or the 500 Ω resistor
(see 4.5, Load 2) for the 500 Ω current measurement and the inductive current probe
(see 4.4).
5.2.2.2 Short circuit current waveform
Attach the shorting wire between the pins to be measured. Place the current probe around the
shorting wire, as close to terminal B as practical, observing the polarity shown in Figure 1.
Apply an ESD stress at the voltage and polarity needed to execute the qualification,
re-qualification or periodic verification being conducted.
a) For positive clamp sockets, insert the shorting wire between the socket pins connected to
terminals A and B and hold in place by closing the clamp.
b) For non-positive clamp sockets, attach the shorting wire between the socket pins
connected to terminals A and B. If it is not possible to make contact within the socket,
connect the shorting wire between the reference pin pair test points or socket mounting
holes, if available. The design of the socket is important as some socket types may
include contact springs (coils) in their design. These springs can add more parasitic
inductance to the signal path and may affect the HBM waveform. Selecting sockets that
minimize the use of springs (coils) is recommended, but if this is not possible, then
keeping their length as short as possible is recommended.
c) For non-socketed testers, place the shorting wire with the inductive current probe on an
insulating surface and place the simulator terminal A and terminal B probes on the ends of
the wires.
5.2.2.3 500 Ω load current waveform
Place the current probe around the 500 Ω resistor’s lead, observing the polarity as shown in
Figure 1. Attach the 500 Ω resistor between the pins to be measured. The current probe shall
be placed around the wire between the resistor and terminal B. Apply an ESD stress at the

– 14 – IEC 60749-26:2018 © IEC 2018
voltage and polarity needed to execute the qualification, re-qualification or periodic
verification being conducted.
a) For socketed testers, follow procedures according to socket type as described in 5.2.2.2.
b) For non-socketed testers, place the test load and current probe on an insulating surface
and connect the tester’s probes to the ends of the test load.
5.2.3 Determination of waveform parameters
5.2.3.1 Use of waveforms
The captured waveforms are used to determine the parameter values listed in Table 1.
5.2.3.2 Short circuit waveform
Typical short circuit waveforms are shown in Figures 2 a), 2 b) and 4. The parameters I
ps
(peak current), t (pulse rise time), t (pulse decay time) and I (ringing) are determined from
r d R
these waveforms. Ringing may prevent the simple determination of I . A graphical technique
ps
for determining I and I is described in 5.2.3.4 and Figure 4.
ps R
5.2.3.3 500 Ω load waveform
A typical 500 Ω load waveform is shown in Figure 3. The parameters I (peak current with
pr
500 Ω load) and t (pulse rise time with 500 Ω load) are determined from this waveform.
rr
I
psmax
I
ps
90 % I
ps
10 % I
ps
Time (ns)
t
r 40 ns
5 ns per division
t
max
IEC
a) Current waveform through a shorting wire (I )
psmax
I
ps
36,8 % I
ps
Time  (ns)
t
d
100 ns per division
t
max
IEC
b) Current waveform through a shorting wire (t )
d
Figure 2 – Current waveform through shorting wires
Current (A)
Current (A)
– 16 – IEC 60749-26:2018 © IEC 2018
I
pr
90 % I
pr
10 % I
pr
0 Time (ns)
t
rr
5 ns per division
IEC
Figure 3 – Current waveform through a 500 Ω resistor
5.2.3.4 Graphical determination of I and I (see Figure 4)
ps R
5.2.3.4.1 A line is drawn (manually or using numerical methods such as least squares)
through the HBM ringing waveform from t to t + 40 ns to interpolate the v
...