IEC 63003:2015

IEC 63003 ®
Edition 1.0 2015-12
™
IEEE Std 1505.1
INTERNATIONAL
STANDARD
colour
inside
Standard for the common test interface pin map configuration for high-density,
single-tier electronics test requirements utilizing IEEE Std 1505™

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IEC 63003 ®
Edition 1.0 2015-12
IEEE Std 1505.1™
INTERNATIONAL
STANDARD
colour
inside
Standard for the common test interface pin map configuration for high-density,

single-tier electronics test requirements utilizing IEEE Std 1505™

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040 ISBN 978-2-8322-2941-5

IEEE Std 1505.1-2008
Contents
1. Overview . 1
1.1 Scope . 1
1.2 Purpose . 2
1.3 Statement of the problem . 2
2. Normative references . 3
3. Definitions, acronyms, and abbreviations . 4
3.1 Definitions . 4
3.2 Specification terms . 4
3.3 Acronyms and abbreviations . 4
4. Common test interface requirements . 8
4.1 Introduction . 8
4.2 CTI open system requirements . 8
4.3 CTI cost requirements. 9
4.4 Vertical integration test support requirements . 9
4.5 CTI configuration/interoperability requirements .10
4.6 Maintainability/end-user support requirements .10
4.7 Scaleable architecture requirements .10
4.8 Physical framework requirements .12
4.9 Reliability requirements.17
4.10 CTI connector footprint/parametric requirements .18
4.11 CTI pin map requirements .22
4.12 CTI pin map input/output configuration .33
Annex A (normative) Common test interface signal definitions for pin map.34
A.1 Analog instruments (AI) .34
A.2 Bus .36
A.3 Digital .37
A.4 Instrument control .37
A.5 Power loads .37
A.6 Power supplies .38
A.7 Sense and control, DCPS, and loads .38
A.8 Switch .39
A.9 System .40
Annex B (informative) Bibliography.159
Annex C (informative) IEEE List of Participants.162


vii
IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
STANDARD FOR THE COMMON TEST INTERFACE PIN MAP
CONFIGURATION FOR HIGH-DENSITY, SINGLE-TIER
ELECTRONICS TEST REQUIREMENTS UTILIZING IEEE Std 1505™

FOREWORD
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Published by IEC under license from IEEE. © 2008 IEEE. All rights reserved.

IEEE Std 1505.1-2008
International Standard IEC 63003/IEEE Std 1505.1-2008 has been processed through IEC
technical committee 91: Electronics assembly technology, under the IEC/IEEE Dual Logo
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The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
IEEE Std 1505.1-2008 91/1274/FDIS 91/1298/RVD
Full information on the voting for the approval of this standard can be found in the report on
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Published by IEC under license from IEEE. © 2008 IEEE. All rights reserved.

IEEE Std 1505.1-2008
IEEE Std 1505.1™-2008
IEEE Standard for the Common
Test Interface Pin Map Configuration
for High-Density, Single-Tier
Electronics Test Requirements
™
Utilizing IEEE Std 1505
Sponsor
IEEE Instrumentation and Measurement Society
and
IEEE Standards Coordinating Committee 20 on
Test and Diagnosis for Electronic Systems

Approved 26 September 2008
IEEE-SA Standards Board
Approved as a Full-Use Standard on 14 June 2013
IEEE-SA Standards Board
i
IEEE Std 1505.1-2008
Abstract: This standard represents an extension to the IEEE 1505 receiver fixture interface (RFI)
standard specification. Particular emphasis is placed on defining within the IEEE 1505 RFI
standard a more specific set of performance requirements that employ a common scalable: (a)
pin map configuration; (b) specific connector modules; (c) respective contacts; (d) recommended
switching implementation; and (e) legacy automatic test equipment (ATE) transitional devices.
This is intentionally done to standardize the footprint and assure mechanical and electrical
interoperability between past and future automatic test systems (ATS).
TM
Keywords: ATE, ATS, fixture, ICD, IEEE 1505.1 , interface, ITA, mass termination, receiver,
scalable, TPS, UUT
•
IEEE Std 1505.1-2008
IEEE Introduction
This introduction is not part of IEEE Std 1505.1-2008, IEEE Standard for the Common Test Interface Pin Map
™
Configuration for High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505 .
This standard stems from the history of ATE implementations having unique input/output (I/O) pin out
definitions. This uniqueness has prevented the interoperability of test program sets (TPSs) among different
ATEs within the same organizations. Even if the same RFI was used by the target ATE, the signals I/O
could not be guaranteed to be at the same pin location. This is due to there being no suitable standard pin
out definition for general purpose electronic testing applications.
a
IEEE Std 1505-2006 has addressed part of the interoperability problem by defining the common
mechanical interface for the ATE. This project takes the TPS interoperability problem one step further
toward completion by standardizing the electrical signal I/O pin map for general purpose electronic testing
applications.
Particular emphasis is placed on defining within the IEEE 1505 RFI standard a more specific set of
performance requirements that employ a common scalable: (a) framework; (b) pin map configuration; (c)
specific connector modules; (d) respective contacts; (e) recommended switching implementation; and (f)
legacy ATE transitional devices. This is intentionally done to standardize the footprint and assure
mechanical and electrical interoperability between past and future ATS. The suggested mechanical and
electrical requirements necessary to implement a specific IEEE 1505 RFI product in support of a common
test interface (CTI) across all U.S. Department of Defense (DoD) defense agencies, related aerospace
industry, and a variety of non-U.S. government agencies such as the U.K. Ministry of Defense (MoD) is
provided.
The DoD is a major buyer and user of ATE; however, existing acquisition guidance desires the use of
commercial standards and/or best practices for these systems. Suitable standards currently do not exist in
the commercial marketplace; therefore, this standard will provide such specification.
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a
Information on references can be found in Clause 2.

IEEE Std 1505.1-2008
Updating of IEEE documents
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v
1 IEEE Std 1505.1-2008
Standard for the Common
Test Interface Pin Map Configuration
for High-Density, Single-Tier
Electronics Test Requirements
™
Utilizing IEEE Std 1505
IMPORTANT NOTICE: IEEE Standards documents are not intended to ensure safety, health, or
environmental protection, or ensure against interference with or from other devices or networks.
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http://standards.ieee.org/IPR/disclaimers.html.


1. Overview
1.1 Scope
™ 1
The scope of this standard is the definition of a pin map utilizing the IEEE 1505 receiver fixture
interface (RFI). The pin map defined within this standard shall apply to military and aerospace automatic
test equipment (ATE) testing applications.
Information on references can be found in Clause 2.

IEEE Std 1505.1-2008 2
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

1.2 Purpose
Standardization of a common input/output (I/O) will enable the interoperability of IEEE 1505 compliant
interface fixtures [also known as interface test adapters (ITA), interface devices (IDs), or interconnecting
devices (ICDs)] on multiple ATE systems utilizing the IEEE 1505 RFI.
1.3 Statement of the problem
1.3.1 U.S. Government guidance
From 1980 to 1992, the U.S. Department of Defense (DoD) investment in field, depot, and factory
automatic test systems (ATS) exceeded $35 billion with an additional $15 billion for associated support.
Most of this test capability was acquired as part of individual weapon system procurements. This led to a
proliferation of different custom equipment types with unique interfaces. Recent policy decisions have
changed the direction of the purchase of test equipment towards a standards based approach with both
hardware and software critical interface requirements.
The U.S. DoD Instruction 5000.2-R1 ATS Policy states: “ATS capabilities shall be defined through critical
hardware and software elements” (see [B2] ). This policy however, did not define these critical elements.
The Critical Interfaces Project was created to define critical ATS elements.
1.3.2 Critical Interfaces Project
The Factory-to-Field Integration of Defense Test Systems Project (commonly referred to as the Critical
Interfaces Project) was started in the latter part of 1995. The Critical Interfaces Working Group (CIWG)
within the Joint-Service ATS Research and Development Integrated Product Team (ARI) was established
to perform the project. The ATS Executive Agent Office (EAO) has provided project management and
coordination among the Air Force, Army, Marine Corps, and Navy participants. In addition, many industry
representatives have participated. The CIWG published their findings in the Automatic Test System
Critical Interfaces Report [B1] and this report served as the basis for the development of the RFI
architecture and subsequent specification.
The objective of the Critical Interfaces Project was to demonstrate the feasibility of reducing the cost to re-
host test program sets (TPSs) and increase the interoperability of TPS software among the military services
by using standardized interfaces.
Interfaces that offer the potential to achieve this objective are deemed critical. Potential savings will be
quantified through demonstration. The Automatic Test System Critical Interfaces Report [B1] is maintained
by the ATS EAO and provides guidance to DoD ATE acquisition programs. This document also addressed
the requirements of DoD Regulation 5000.2-R1 [B2] and assisted in migrating the DoD designated tester
families towards a common solution. The Hardware Interfaces (HI) Subcommittee of the IEEE Standards
Coordinating Committee on Test and Diagnosis for Electronic Systems (SCC20) applied the
recommendations of the report as it related to the RFI, to the extent that the current RFI standard is in full
compliance with the report.
1.3.3 CTIWG guidance recommendations
During the Common Test Interface Working Group (CTIWG) October 2003 meeting, the DoD provided
the following recommendations as guidance for the Working Group’s success:

The numbers in brackets correspond to those of the bibliography in Annex B.
3 IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

a) Identify a modular/scaleable interface
b) Allow use of different size ID/fixture on the same general purpose interface (GPI)
c) Ensure TPS hardware compatibility as interface grows
d) Provide legacy system support
e) Provide a transition path to support legacy TPS hardware
f) Adhere to an open architecture system
g) Built to one specification
h) Multiple sources
i) Non-proprietary design and components
j) Ensure capabilities that provision for growth and special requirements
k) Provide room for future expansion and TPS requirements
l) Support and Promote the use of commercial-off-the-shelf (COTS) interconnect components
m) Use industry standard connector technology
1.3.4 CTIWG legacy test program set support
In support of these recommendations, the CTI architecture shall assure past legacy and future TPS plug and
play compatibility between defense agencies and defense-aerospace suppliers. Areas addressed by the
CTIWG include:
a) Pin mapping
b) Scalability
c) TPS legacy support
d) Connector parametric (dc to light)
e) Reliability and maintainability
f) Physical
g) Switching
h) Design-to-cost factors
2. Normative references
The following referenced documents are indispensable for the application of this document (i.e., they must
be understood and used, so each referenced document is cited in text and its relationship to this document is
explained). For dated references, only the edition cited applies. For undated referenced, the latest edition of
the referenced document (including any amendments or corrigenda) applies.
3, 4
IEEE Std 1505-2006, IEEE Standard for Receiver Fixture Interface.

IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854,
USA (http://standards.ieee.org/).
The IEEE standards or products referred to in Clause 2 are trademarks owned by the Institute of Electrical and Electronics Engineers,
Incorporated.
IEEE Std 1505.1-2008 4
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

3. Definitions, acronyms, and abbreviations
3.1 Definitions
For the purposes of this document, the following terms and definitions apply. The Authoritative Dictionary
of IEEE Standards Terms [B5] should be referenced for terms not defined in this clause.
3.1.1 pin map: The data table and explanatory text that provides the assignment of electrical characteristics
or instrument I/O to specific pins.
3.2 Specification terms
The specification terms used throughout this standard are described as follows.
Rule: Rules shall be followed to ensure compatibility to the standard. A rule is characterized by the use of
the words shall and shall not. These words are not used for any other purpose other than stating rules.
Recommendation: Recommendations consist of advice to applicants that will affect the usability of the
final device. Discussions of particular hardware to enhance throughput would fall under a recommendation.
These should be followed to avoid problems and to obtain optimum performance.
Suggestion: A suggestion contains advice that is helpful but not vital. The reader is encouraged to consider
the advice before discarding it. Suggestions are included to help the novice designer with problematic areas
of the design.
Permission: Permissions are included to clarify the areas of the specification that are not specifically
prohibited. Permissions reassure the reader that a certain approach is acceptable and will cause no
problems. The word may is reserved for indicating permissions.
Observation: Observations spell out implications of rules and bring attention to things that might
otherwise be overlooked. They also give the rationale behind certain rules, so that the reader understands
why the rule must be followed.
3.3 Acronyms and abbreviations
ACPS alternating current power supply
ADC analog-to-digital converter
AI analog instrument
AM amplitude modulation
ATE automatic test equipment
ATS automatic test system
AWG arbitrary waveform generator, American wire gauge
5 IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

CAL calibration
CAN controller-area network
CASS Consolidated Automated Support System
CH channel
CIWG Critical Interfaces Working Group
CLK clock
COTS commercial-off-the-shelf
CSW coax switch
CTI common test interface
DAC digital-to-analog converter
DAS display analyzer-simulator
DCPS direct current power supply
DMM digital multi-meter
DoD U.S. Department of Defense
DTC design-to-cost
ECL emmitter-coupled logic
ESTS Electronic Systems Test Set
ETE end to end
EXT external
freq frequency
FTIC frequency time interval counter
GND ground
GPI general purpose interface
HPL high-power load
IAIS improved avionics intermediate shop
ICD interconnecting device
US Navy Tester, AN/USM-636 (V).
US Air Force Tester, AN/GSM-397 (V).
IEEE Std 1505.1-2008 6
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

ID interface device
IFTE Integrated Family of Test Equipment
Instr instrument
I/O input/output
ITA interface test adapter
JTAG Joint Testability Action Group
LCC life-cycle costs
LFC low-frequency calibrator
® 8
LM-STAR Lockheed Martin Star
LPL low-power load
LXI LAN extensions for instrumentation
max maximum
min minimum
MOD modulation
MoD Ministry of Defense (UK)
MOD SRC modulation source
MRK marker
MTA microwave transition analyzer
MTBF mean time between failures
MUX multiplexer
NOM nominal
OCD open-collector driver
ORD Operational Requirements Document
PAM phase-angle modulation
PCI Peripheral Component Interface

US Army Tester, AN/USM-632 (V)3.
LM-STAR is a registered trademark of Lockheed Martin Corporation. This information is given for the convenience of users of this
standard and does not constitute an endorsement by the IEEE of these products. Equivalent products may be used if they can be shown
to lead to the same results.
7 IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

PECL positive emmitter-coupled logic
PGEN pulse generator
PH phase
PM pulse (or phase) modulation, power meter
Prog programmable
PS power supply
PSW power switch
PXI PCI Extensions for Instrumentation (compact PCI format)
RAF Royal Air Force
ResLoad resistive load
RF radio frequency
RFI receiver fixture interface
RSIA raster stroke image acquisition
SAMe sistema automatico de mantenimiento estandar
Spec An spectrum analyzer
STA system trigger assembly
Std Standard
Sync synchronizer
TETS Third Echelon Test System
TPS test program set
Trig trigger
TSP twisted shielded pair
TTL transistor-transistor logic
UBIC universal bus interface controller
USB Universal Serial Bus
UUT unit under test
VGA Versatile Graphics Adapter

US Marine Tester, AN/USM-657 (V)1, (V)2, (V)3.
IEEE Std 1505.1-2008 8
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

VME versa-module extended
VXI VME extended for instrumentation
4. Common test interface requirements
4.1 Introduction
The following subclauses and illustrations describe the requirements for this standard, IEEE Std 1505.1-
2008, to support military/aerospace test requirements. This information is supplemental and not stand-alone
and shall coexist with that presented in the IEEE Std 1505 RFI specifications, Clause 1 through Clause 6.
The IEEE 1505.1 standard for the use of IEEE 1505 RFI to support military/aerospace test requirements
represents a higher order subset of cost/physical/signal performance requirements to meet specific industry
and defense agency goals of a common test interface (CTI). These high order requirements expand on the
previously defined RFI: (a) framework; (b) connector modules and respective contacts; to meet objectives
for: (c) a common scalable pin map configuration; (d) switching; and (e) legacy ATS transitional device for
Third Echelon Test System (TETS), Consolidated Automated Support System (CASS), Integrated Family
of Test Equipment (IFTE), and others as deemed necessary by the cognizant agencies. This is intentionally
done to standardize the footprint and assure mechanical and electrical interoperability between past and
future ATS.
4.2 CTI open system requirements
4.2.1 Government “open system” policy
On 29 November 1994, the Honorable Paul G. Kaminski, Under Secretary of Defense for Acquisition and
Technology, directed acquisition executives in the DoD to use “open systems” specifications and standards
(electrical, mechanical, thermal, etc.), for acquisition of all weapon systems electronics to the greatest
extent practical. The Open Systems Joint Task Force (OS-JTF) was formed in September 1994 to:
“Sponsor and accelerate the adoption of open systems in weapons systems and subsystems electronics to
reduce life-cycle costs (LCC) and facilitate effective weapon system intra- and interoperability.”
4.2.2 CTI “open” architecture
Rule 4.2.2: An open standard CTI architecture shall identify components, the relationship between
components, and the rules for the architecture’s composition.
Recommendation 4.2.2: Typical guidelines for addressing the CTI architecture should include:
a) Define and describe a system architecture that is traceable to the Operational Requirements
Document (ORD).
b) A preferred architecture is modular, hierarchical and layered, and is based on open standards at
its interfaces.
c) Selection of an architecture shall be a cooperative process between government and industry.
d) Specify key performance attributes of system building blocks including internal interface
standards.
9 IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

e) Where a new system is contemplated, consensus among potential contractors and their key
suppliers on application of widely accepted standards is desirable.
f) Identify aspects of the program that might limit the use of an open systems approach.
g) Determine the level at which the architecture will be defined for the system.
h) Architecture approach resulting from a system engineering process shall be linked to a business
case analysis.
i) Decisions about architecture shall be linked to performance, LCC, schedule, and risk.
j) Identify opportunities for reuse of hardware and software configuration items and dependence
upon interfaces.
4.3 CTI cost requirements
Recommendation 4.3a: Fundamental to the implementation of the CTI recommended practice should be
the paramount need to address design-to-costs (DTC) and LCC attributed to test interface and TPS
requirements.
Recommendation 4.3b: CTI should improve the test acquisition process by creating a competitive multi-
vendor environment that provisions common module components that can be procured as COTS, at pricing
that benefits from industry economics-of-scale production/quality processes, and improved time-to-market
availability.
Recommendation 4.3c: CTI should meet advanced functional and technological needs through shared
industry R&D, multi-functional/virtual modules that can be replicated, distributed, and reconfigured to
meet a broad set of applications without customization. Extend legacy system life through technology
insertion of plug and play enhancements based upon standardized infrastructure, and related cost-avoidance
of ATS obsolescence.
Recommendation 4.3d: CTI should minimize configuration variations and related software customization
and adjustments between unique test assets, integration methods, and signal routing schemes.
Recommendation 4.3e: CTI should promote cooperative design, design reuse, shared design data models,
automation in software development, rehostability and portability of TPSs, implementation of lessons
learned, and enhance long-term support between vendors, integrators and users. Standards also promote
common fabrication processes, signal routing schemes, canned solutions that could reduce TPS engineering
integration time and cost.
4.4 Vertical integration test support requirements
Recommendation 4.4: The implementation of the CTI/RFI standard as common vertical integrated test
support through the product cycle and various maintenance levels assures the greatest benefits of common
system implementation and cost savings. Specific benefits include the shared development/manufacturing
of ATS and TPS assets, enhanced TPS verification and refinements, and transitional improvements in
lessons learned, hands-on training and asset management.
IEEE Std 1505.1-2008 10
IEEE Std 1505.1-2008
IEEE Standard for the Common Test Interface Pin Map Configuration for
High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505™

4.5 CTI configuration/interoperability requirements
Rule 4.5: CTI pin map requirements, as defined by general pin map requirements in Annex A, and
subsequent detailed CTI pin map input/output (I/O) configuration, shall be implemented to assure test
interface interoperability between agencies and ATS configurations.
Recommendation 4.5: A common CTI pin map configuration has been recommended across government
multi-agencies, to stimulate greater use of common assets, which reduces proliferation and support
duplication. By satisfying interoperability requirements between government agencies TPS development,
deployment and asset duplication can be eliminated and related weapon system support enhanced.
4.6 Maintainability/end-user support requirements
Rule 4.6: The general pin map requirements in Annex A, and subsequent detailed CTI pin map I/O
configuration, as part of this IEEE 1505.1 CTI document, shall be maintained/upgraded through IEEE
standards revision processes.
Recommendation 4.6: The CTI implementation within industry and the government, utilizing standard
product configurations, multi-vendor interchangeable parts, calibration, and maintenance support is
recommended.
Observation 4.6: Applying common CTI products to ATS and CTI fixture deployment would dramatically
reduce duplicative requirements for unique system development, validation, production, deployment,
config
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