IEC 62525:2007

IEC 62525
Edition 1.0 2007-11
™
IEEE 1450
INTERNATIONAL
STANDARD
Standard Test Interface Language (STIL) for Digital Test Vector Data

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IEC 62525
Edition 1.0 2007-11
™
IEEE 1450
INTERNATIONAL
STANDARD
Standard Test Interface Language (STIL) for Digital Test Vector Data

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XG
ICS 25.040;19.080 ISBN 2-8318-9337-2

– 2 – IEC 62525:2007(E)
IEEE 1450-1999(E)
CONTENTS
FOREWORD .6
IEEE Introduction .9
1. Overview.10
1.1 Scope.12
1.2 Purpose.13
2. References.13
3. Definitions, acronyms, and abbreviations.13
3.1 Definitions.13
3.2 Acronyms and abbreviations.16
4. Structure of this standard . 16
5. STIL orientation and capabilities tutorial (informative).17
5.1 Hello Tester.17
5.2 Basic LS245. 22
5.3 STIL timing expressions/”Spec” information. 26
5.4 Structural test (scan) . 31
5.5 Advanced scan . 35
5.6 IEEE Std 1149.1-1990 scan . 41
5.7 Multiple data elements per test cycle. 46
5.8 Pattern reuse/direct access test. 50
5.9 Event data/non-cyclized STIL information . 54
6. STIL syntax description. 64
6.1 Case sensitivity . 64
6.2 Whitespace. 64
6.3 Reserved words. 64
6.4 Reserved characters . 66
6.5 Comments . 67
6.6 Token length . 67
6.7 Character strings . 67
6.8 User-defined name characteristics . 68
6.9 Domain names . 68
6.10 Signal and group name characteristics.69
6.11 Timing name constructs. 69
6.12 Number characteristics. 69
6.13 Timing expressions and units (time_expr). 70
6.14 Signal expressions (sigref_expr). 72
6.15 WaveformChar characteristics. 73
6.16 STIL name spaces and name resolution. 74
7. Statement structure and organization of STIL information . 76
7.1 Top-level statements and required ordering . 68
7.2 Optional top-level statements . 70
7.3 STIL files . 70
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

IEEE 1450-1999(E)
8. STIL statement. 79
8.1 STIL syntax. 79
8.2 STIL example. 79
9. Header block . 80
9.1 Header block syntax. 80
9.2 Header example . 80
10. Include statement . 80
10.1 Include statement syntax. 81
10.2 Include example. 81
10.3 File path resolution with absolute path notation. 81
10.4 File path resolution with relative path notation . 81
11. UserKeywords statement . 82
11.1 UserKeywords statement syntax. 82
11.2 UserKeywords example. 82
12. UserFunctions statement. 82
12.1 UserFunctions statement syntax . 83
12.2 UserFunctions example. 83
13. Ann statement . 83
13.1 Annotations statement syntax . 83
13.2 Annotations example . 83
14. Signals block. 83
14.1 Signals block syntax . 84
14.2 Signals block example . 86
15. SignalGroups block. 86
15.1 SignalGroups block syntax . 86
15.2 SignalGroups block example . 87
15.3 Default attribute values. 87
15.4 Translation of based data into WaveformChar characters. 88
16. PatternExec block . 89
16.1 PatternExec block syntax. 90
16.2 PatternExec block example. 90
17. PatternBurst block. 90
17.1 PatternBurst block syntax . 91
17.2 PatternBurst block example . 92
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

– 4 – IEC 62525:2007(E)
IEEE 1450-1999(E)
18. Timing block and WaveformTable block. 92
18.1 Timing and WaveformTable syntax . 93
18.2 Waveform event definitions. 96
18.3 Timing and WaveformTable example . 98
18.4 Rules for timed event ordering and waveform creation. 99
18.5 Rules for waveform inheritance. 102
19. Spec and Selector blocks .103
19.1 Spec and Selector block syntax.103
19.2 Spec and Selector block example .105
20. ScanStructures block.106
20.1 ScanStructures block syntax .107
20.2 ScanStructures block example .108
21. STIL Pattern data . 109
21.1 Cyclized data. 109
21.2 Multiple-bit cyclized data . 110
21.3 Non-cyclized data . 111
21.4 Scan data . 111
21.5 Pattern labels. 112
22. STIL Pattern statements. 112
22.1 Vector (V) statement. 112
22.2 WaveformTable (W) statement. 113
22.3 Condition (C) statement. 113
22.4 Call statement. 114
22.5 Macro statement. 114
22.6 Loop statement. 115
22.7 MatchLoop statement. 115
22.8 Goto statement . 116
22.9 BreakPoint statements. 116
22.10 IDDQTestPoint statement. 116
22.11 Stop statement. 117
22.12 ScanChain statement. 117
23. Pattern block . 117
23.1 Pattern block syntax. 117
23.2 Pattern initialization. 118
23.3 Pattern examples . 118
24. Procedures and MacroDefs blocks. 118
24.1 Procedures block. 119
24.2 Procedures example . 120
24.3 MacroDefs block. 120
24.4 Scan testing . 120
24.5 Procedure and Macro Data substitution. 121
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

IEEE 1450-1999(E)
Annex A (informative) Glossary . 125
Annex B (informative) STIL data model. 126
Annex C (informative) GNU GZIP reference . 131
Annex D (informative) Binary STIL data format. 132
Annex E (informative) LS245 design description . 136
Annex F (informative) STIL FAQs and language design decisions. 138
Annex G (informative) List of participants. 142
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

– 6 – IEC 62525:2007(E)
IEEE 1450-1999(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
STANDARD TEST INTERFACE LANGUAGE (STIL)
FOR DIGITAL TEST VECTOR DATA
FOREWORD
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International Standard IEC/IEEE 62525 has been processed through Technical Committee 93:
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The text of this standard is based on the following documents:
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1450(1999) 93/247/FDIS 93/258/RVD
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IEEE 1450-1999(E)
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– 8 – IEC 62525:2007(E)
IEEE 1450-1999(E)
IEEE StandardTest Interface
Language (STIL) for DigitalTest
Vector Data
Sponsor
Test Technology Standards Committee
of the
IEEE Computer Society
Approved 18 March 1999
IEEE-SA Standards Board
Abstract: Standard Test Interface Language (STIL) provides an interface between digital test gen-
eration tools and test equipment. A test description language is defined that: (a) facilitates the trans-
fer of digital test vector data from CAE to ATE environments; (b) specifies pattern, format, and
timing information sufficient to define the application of digital test vectors to a DUT; and (c) sup-
ports the volume of test vector data generated from structured tests.
Keywords: automatic test pattern generator (ATPG), built-in self-test (BIST), computer-aided en-
gineering (CAE), cyclize, device under test (DUT), digital test vectors, event, functional vectors, pat-
tern, scan vectors, signal, structural vectors, timed event, waveform, waveshape
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

IEEE 1450-1999(E)
IEEE Introduction
Standard Test Interface Language (STIL) was initially developed by an ad-hoc consortium of test equipment
vendors, computer-aided engineering (CAE) and computer-aided design (CAD) vendors, and integrated cir-
cuit (IC) manufacturers, to address the lack of a common solution for transferring digital test data from the
generation environment to the test equipment.
The need for a common interchange format for large volumes of digital test data was identified as an overrid-
ing priority for the work; as such, the scope of the work was constrained to those aspects of the test environ-
ment that contribute significantly to the volume issue, or are necessary to support the comprehension of that
data. Binary representations of data were a key consideration in these efforts, resulting in a proposal to incor-
porate the compression of files as part of this standard.
Limiting the scope of any standards project is a difficult thing to do, especially for a room full of engineers.
However, issues that did not impact the scope as identified were dropped from consideration in this version
of the standard. Subclause 1.1 covers, specifically, the capabilities that are not intended to be part of this first
standard.
Early work in this consortium consisted of identifying the requirements necessary to address this problem
and reviewing existing options and languages in the industry. All options proposed fell short of addressing
the requirements, and the consortium started to define a new language. This work was executed with heavy
leverage from some existing languages and environments, and STIL owes much to the groundwork estab-
lished by these other languages.
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

– 10 – IEC 62525:2007(E)
IEEE 1450-1999(E)
STANDARD TEST INTERFACE LANGUAGE (STIL)
FOR DIGITAL TEST VECTOR DATA
1. Overview
Standard Test Interface Language (STIL) is a standard language that provides an interface between digital
test generation tools and test equipment. STIL may be directly generated as an output language of a test gen-
eration tool, or it may be used as an intermediate format for subsequent processing. Figure 1 shows STIL
usage in a “pipe” format. This is meant solely as a visual analogy to emphasize the high-volume/high-
throughput requirements. It is not meant to represent physical structures or implementation requirements.
STIL is a representation of information needed to define digital test operations in manufacturing tests. STIL
is not intended to define how the tester implements that information. While the purpose of STIL is to pass
test data into the test environment, the overall STIL language is inherently more flexible than any particular
tester. Constructs may be used in a STIL file that exceed the capability of a particular tester. In some circum-
stances, a translator for a particular type of test equipment may be capable of restructuring the data to sup-
port that capability on the tester; in other circumstances, separate tools may operate on that data to provide
that restructuring. In all circumstances, it is desirable to provide the capability to check the data against the
constraints of a tester. This capability is referred to as Tester Rules Checking and is the domain of tools that
operate on STIL data. As such, Tester Rules Checking operations are outside the scope of this standard.
Figure 2 shows how STIL fits into the data flow between computer-aided engineering (CAE)/simulation and
the test environment. In this figure, STIL is shown as both the input and output of “STIL Manipulation
Tools.” STIL represents patterns as a series of cyclized waveforms that are executed sequentially. The wave-
form representation can be as simple as a “print-on-change” set of events, or a complex set of parameterized
events. Hence, tools may be required to manipulate the data according to the requirements of a particular
class of device, simulation, or tester. The output of that manipulation is still represented in STIL.
Another issue presented in Figure 2 is the need for data from the tester to be transmitted back to the
CAE/simulation environment for the purpose of correlating simulation data to tester data. Although this is
recognized as an important aspect of testing digital devices, it does not represent the data volume that the
patterns themselves do, and is not specifically supported in this version of the standard.
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

IEEE 1450-1999(E)
Tester
Editors
Adjust
perl,
Formatter Tool
Test Tran
CAE
S T I L
Test Tran
CAE
Test Tran
Figure 1—A conduit for transporting data from CAE to ATE
ATPG
Rules,
Simulators
Instructions
STIL
Manipulation
STIL
Tools
Rules,
Target tester
Instructions
translator /
compiler
Diagnostic Vector &
xrefs for Support
debug memory
(Sim->Pat) loads
Datalog from
tester
Figure 2—STIL usage model
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

– 12 – IEC 62525:2007(E)
IEEE 1450-1999(E)
1.1 Scope
This standard defines a test description language that:
a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to auto-
mated test equipment (ATE) environments;
b) Specifies pattern, format, and timing information sufficient to define the application of digital test
vectors to a device under test (DUT);
c) Supports the volume of test vector data generated from structured tests such as scan/automatic test
pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional
test specifications for IC designs and their assemblies, in a format optimized for application in ATE
environments.
In setting the scope for any standard, some issues are defined to not be pertinent to the initial project. The
following is a partial list of issues that were dropped from the scope of this initial project:
— Levels: A key aspect of a digital test program is the ability to establish voltage and current parame-
ters (levels) for signals under test. Level handling is not explicitly defined in the current standard, as
this information is both compact (not presenting a transportation issue) and commonly established
independently of digital test data, requiring different support mechanisms outside the current scope
of this standard. Termination values may affect levels.
— Diagnostic/fault-tracing information: The goal of this standard is to optimally present data that needs
to be moved onto ATE. While diagnostic data, fault identification data, and macro/design element
correspondence data can fall into this category (and is often fairly large), this standard is also
focused on integrated circuit and assemblies test, and most debug/failure analysis occurs separately
from the ATE for these structures. Note that return of failure information (for off-ATE analysis) is
also not part of the standard as currently defined.
— Datalogging mechanisms, formatting, and control usually are not defined as part of this current
standard.
— Parametric tests are not defined as an integral part of this standard, except for optional pattern labels
that identify potential locations for parametric tests, such as I tests or alternating current (AC)
DDQ
timing tests.
— Program flow: Test sequencing and ordering are not defined as part of the current standard except as
necessary to define collections of digital patterns meant to execute as a unit.
— Binning constructs are not part of the current standard.
— Analog or mixed-signal test: While this is an area of concern for many participants, at this point
transfer of analog test data does not contribute to the same transportation issue seen with digital data.
— Algorithmic pattern constructs (such as sequences commonly used for memory test) are not currently
defined as part of the standard.
— Parallel test/multisite test constructs are not an integral part of the current environment.
— User input and user control/options are not part of the current standard.
— Characterization tools, such as shmoo plots, are not defined as part of the current standard.
Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

IEEE 1450-1999(E)
1.2 Purpose
This standard addresses a need in the integrated circuit (IC) test industry to define a standard mechanism for
transferring the large volumes of digital test data from the generation environment through to test. The
environment today contains unique output formats of existing CAE tools, individual test environments of IC
manufacturers, and proprietary IC ATE input interfaces. As each of these three arenas solves individual prob-
lems, together they have created a morass of interfaces, translators, and software environments that provide
no opportunity to leverage common goals and result in much wasted efforts re-engineering solutions. As
device density increases, the magnitude of test data threatens to shift the test bottleneck from the generation
process to the processes necessary solely to maintain and transport this data. These two factors threaten to
eliminate any productive work performed in this area unless a viable standard is defined.
With a common standard for CAE and IC ATE environments, the generation, movement, and processing of
this test data is greatly facilitated. This standard also allows for immediate access to test equipment support-
ing this standard, which benefits both ATE and IC vendors reviewing this equipment.
This standard also serves as a catalyst for the development of a set of standard third party interface tools to
both test and design aspects of IC device generation.
2. References
This standard shall be used in conjunction with the following standards. If the following publications are
superseded by an approved revision, the revision shall apply.
IEEE Std 100-1996, The IEEE Standard Dictionary of Electrical and Electronics Terms, Sixth Edition.
IEEE Std 260.1-1993, American National Standard Letter Symbols for Units of Measurement (SI Units,
Customary Inch-Pound Units, and Certain Other Units).
ISO 2955:1983, Information processing—Representation of SI and other units in systems with limited char-
acter sets.
ISO/IEC 9899:1999, Programming languages—C.
3. Definitions, acronyms, and abbreviations
3.1 Definitions
For the purposes of this standard, the following terms and definitions apply. Additional terminology specific
to this standard is found in Annex A. IEEE Std 100-1996, The IEEE Standard Dictionary of Electrical and
Electronics Terms, Sixth Edition, should be referenced for terms not defined in this document.
The use of this term in this standard is meant only as a point of reference and not to indicate an explicit limitation or restriction of
focus.
IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway,
NJ 08855-1331, USA (http://www.standards.ieee.org/).
ISO publications are available from the ISO Central Secretariat, Case Postale 56, 1 rue de Varembé, CH-1211, Genève 20, Switzer-
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IEC publications are available from the Sales Department of the International Electrotechnical Commission, Case Postale 131, 3, rue
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Published by IEC under licence from IEEE. © 1999 IEEE. All rights reserved.

– 14 – IEC 62525:2007(E)
IEEE 1450-1999(E)
3.1.1 automatic test pattern generator (ATPG): Any tool that generates test information for a device
based on structural analysis of the device.
3.1.2 breakpoint: A position within a pattern set where the pattern may be segmented into multiple indepen-
dent bursts while still achieving predictable behavior of the device.
3.1.3 built-in self-test (BIST): A test paradigm that incorporates circuitry in the device for executing and
resolving test information about the device.
3.1.4 burst: Tester execution of a pattern or set of patterns. Generally controlled by “start” and “stop” defini-
tions.
3.1.5 computer-aided engineering (CAE): A computer-based set of tools to assist in the design and devel-
opment of integrated circuits.
3.1.6 cyclize: To drive a tester, data must be provided in uniform, consistent, repeatable collections. These
collections are termed “cycles” or “tester cycles.” The process of constructing these collections, generally
from simulation environments, is called “cyclizing.”
3.1.7 device: A reference to an integrated circuit or other design structure.
3.1.8 device under test (DUT): The device to be placed in a test fixture and tested.
3.1.9 float-state:
...