IEC 61523-4:2015

IEC 61523-4 ®
Edition 1.0 2015-03
IEEE Std 1801™-2013
INTERNATIONAL
STANDARD
Design and Verification of Low-Power Integrated Circuits

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IEC 61523-4 ®
Edition 1.0 2015-03
IEEE Std 1801™-2013
INTERNATIONAL
STANDARD
Design and Verification of Low-Power Integrated Circuits

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040; 35.060 ISBN 978-2-8322-2266-9

IEC 61523-4
i IEEE Std 1801-2013
Contents
1. Overview. 1
1.1 Scope. 1
1.2 Purpose. 1
1.3 Key characteristics of the Unified Power Format. 1
1.4 Use of color in this standard . 3
1.5 Contents of this standard. 3
2. Normative references. 4
3. Definitions, acronyms, and abbreviations. 4
3.1 Definitions . 4
3.2 Acronyms and abbreviations . 9
4. UPF concepts . 11
4.1 Design structure . 11
4.2 Design representation . 11
4.3 Power architecture . 14
4.4 Power distribution. 17
4.5 Power management. 23
4.6 Power states . 26
4.7 Simstates . 29
4.8 Successive refinement. 30
4.9 Tool flow. 31
4.10 File structure . 32
5. Language basics. 33
5.1 UPF is Tcl . 33
5.2 Conventions used. 33
5.3 Lexical elements . 34
5.4 Boolean expressions . 37
5.5 Object declaration . 39
5.6 Attributes of objects. 40
5.7 Power state name spaces. 43
5.8 Precedence . 44
5.9 Generic UPF command semantics. 45
5.10 effective_element_list semantics . 45
5.11 Command refinement . 48
5.12 Error handling . 49
5.13 Units. 50
6. Power intent commands. 51
6.1 Categories . 51
6.2 add_domain_elements [deprecated] . 51
..... 52
6.3 add_port_state [legacy] .
6.4 add_power_state . 52
6.5 add_pst_state [legacy] . 57
6.6 apply_power_model. 58
6.7 associate_supply_set . 59
xi
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.
IEC 61523-4
IEEE Std 1801-2013 ii
6.8 begin_power_model . 60
6.9 bind_checker . 61
6.10 connect_logic_net . 63
6.11 connect_supply_net . 64
6.12 connect_supply_set . 65
6.13 create_composite_domain . 67
6.14 create_hdl2upf_vct . 68
6.15 create_logic_net . 69
6.16 create_logic_port . 70
6.17 create_power_domain . 71
6.18 create_power_switch . 74
6.19 create_pst [legacy] . 80
6.20 create_supply_net . 80
6.21 create_supply_port . 83
6.22 create_supply_set . 84
6.23 create_upf2hdl_vct . 85
6.24 describe_state_transition . 86
6.25 end_power_model. 87
6.26 find_objects . 88
6.27 load_simstate_behavior . 90
6.28 load_upf . 91
6.29 load_upf_protected . 92
6.30 map_isolation_cell [deprecated] . 93
6.31 map_level_shifter_cell [deprecated]. 93
6.32 map_power_switch . 93
6.33 map_retention_cell . 94
6.34 merge_power_domains [deprecated]. 97
6.35 name_format . 98
6.36 save_upf . 99
6.37 set_design_attributes . 100
6.38 set_design_top . 101
6.39 set_domain_supply_net [legacy] . 101
6.40 set_equivalent . 102
6.41 set_isolation . 104
6.42 set_isolation_control [deprecated]. 110
6.43 set_level_shifter . 111
6.44 set_partial_on_translation . 116
6.45 set_pin_related_supply [deprecated] . 116
6.46 set_port_attributes . 117
6.47 set_power_switch [deprecated]. 121
6.48 set_repeater . 121
6.49 set_retention . 124
6.50 set_retention_control [deprecated] . 128
6.51 set_retention_elements . 128
6.52 set_scope . 129
6.53 set_simstate_behavior . 130
6.54 upf_version . 131
6.55 use_interface_cell . 132
7. Power management cell commands. 135
7.1 Introduction. 135
7.2 define_always_on_cell. 136
7.3 define_diode_clamp. 137
xii
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.
IEC 61523-4
iii IEEE Std 1801-2013
7.4 define_isolation_cell. 138
7.5 define_level_shifter_cell. 141
7.6 define_power_switch_cell .145
7.7 define_retention_cell . 147
8. UPF processing . 150
8.1 Overview. 150
8.2 Data requirements . 150
8.3 Processing phases . 150
8.4 Error checking. 153
9. Simulation semantics . 154
9.1 Supply network creation . 154
9.2 Supply network simulation .155
9.3 Power state simulation . 157
9.4 Simstate simulation. 159
9.5 Transitioning from one simstate state to another. 161
9.6 Simulation of retention . 162
9.7 Simulation of isolation. 168
9.8 Simulation of level-shifting . 168
9.9 Simulation of repeater. 168
Annex A (informative) Bibliography . 169
Annex B (normative) HDL package UPF. 170
Annex C (normative) Queries. 182
Annex D (informative) Replacing deprecated and legacy commands and options. 219
Annex E (informative) Low-power design methodology. 227
Annex F (normative) Value conversion tables . 252
Annex G (normative) Supporting hard IP. 255
Annex H (normative) UPF power-management commands semantics and Liberty mappings. 258
Annex I (informative) Power-management cell modeling examples . 273
Annex J (informative) Switching Activity Interchange Format . 303
Annex K(informative) IEEE List of Participants.333
xiii
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IEC 61523-4
IEEE Std 1801-2013 iv
xiv
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.
IEC 61523-4
v IEEE Std 1801-2013
DESIGN AND
VERIFICATION OF
LOW-POWER INTEGRATED CIRCUITS
FOREWORD
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IEC 61523-4
IEEE Std 1801-2013 vi
International Standard IEC 61523-4/IEEE Std 1801-2013 has been processed through IEC
technical committee 91: Electronics assembly technology, under the IEC/IEEE Dual Logo
Agreement.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1801 (2013) 91/1209/FDIS 91/1228/RVD
Full information on the voting for the approval of this standard can be found in the report on
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Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.

IEC 61523-4
vii IEEE Std 1801-2013
IEEE Std 1801™-2013
(Revision of
IEEE Std 1801-2009)
IEEE Standard for Design and
Verification of
Low-Power Integrated Circuits
Sponsor
Design Automation Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 6 March 2013
IEEE-SA Standards Board
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.

IEC 61523-4
IEEE Std 1801-2013 viii
Grateful acknowledgment is made to the following for permission to use source material:
Accellera Systems Initiative
Unified Power Format (UPF) Standard, Version 1.0
Cadence Design Systems, Inc.
Library Cell Modeling Guide Using CPF
Hierarchical Power Intent Modeling Guide Using CPF
Silicon Integration Initiative, Inc.
Si2 Common Power Format Specification, Version 2.0
Abstract: A method is provided for specifying power intent for an electronic design, for use in
verification of the structure and behavior of the design in the context of a given power management
architecture, and for driving implementation of that power management architecture. The method
supports incremental refinement of power intent specifications required for IP-based design flows.
Keywords: corruption semantics, IEEE 1801™, interface specification, IP reuse, isolation, level-
shifting, power-aware design, power domains, power intent, power modes, power states,
progressive design refinement, retention, retention strategies
Verilog is a registered trademark of Cadence Design Systems, Inc.
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.

IEC 61523-4
ix IEEE Std 1801-2013
IEEE Introduction
This introduction is not part of IEEE Std 1801-2013, IEEE Standard for Design and Verification of Low-Power
Integrated Circuits.
The purpose of this standard is to provide portable low-power design specifications that can be used with a
variety of commercial products throughout an electronic system design, analysis, verification, and
implementation flow.
When the electronic design automation (EDA) industry began creating standards for use in specifying,
simulating, and implementing functional specifications of digital electronic circuits in the 1980s, the
primary design constraint was the transistor area necessary to implement the required functionality in the
prevailing process technology at that time. Power considerations were simple and easily assumed for the
design as power consumption was not a major consideration and most chips operated on a single voltage for
all functionality. Therefore, hardware description languages (HDLs) such as VHDL (IEC 61691-1-1/
a
IEEE Std 1076™) and SystemVerilog (IEEE Std 1800™) provided a rich set of capabilities necessary for
capturing the functional specification of electronic systems, but no capabilities for capturing the power
architecture (how each element of the system is to be powered).
As the process technology for manufacturing electronic circuits continued to advance, power (as a design
constraint) continually increased in importance. Even above the 90 nm process node size, dynamic power
consumption became an important design constraint as the functional size of designs increased power
consumption at the same time battery-operated mobile systems, such as cell phones and laptop computers,
became a significant driver of the electronics industry. Techniques for reducing dynamic power
consumption—the amount of power consumed to transition a node from a 0 to 1 state or vice versa—
became commonplace. Although these techniques affected the design methodology, the changes were
relatively easy to accommodate within the existing HDL-based design flow, as these techniques were
primarily focused on managing the clocking for the design (more clock domains operating at different
frequencies and gating of clocks when logic in a clock domain is not needed for the active operational
mode). Multi-voltage power-management methods were also developed. These methods did not directly
impact the functionality of the design, requiring only level-shifters between different voltage domains.
Multi-voltage power domains could be verified in existing design flows with additional, straight-forward
extensions to the methodology.
With process technologies below 100 nm, static power consumption has become a prominent and, in many
cases, dominant design constraint. Due to the physics of the smaller process nodes, power is leaked from
transistors even when the circuitry is quiescent (no toggling of nodes from 0 to 1 or vice versa). New design
techniques were developed to manage static power consumption. Power gating or power shut-off turns off
power for a set of logic elements. Back-bias techniques are used to raise the voltage threshold at which a
transistor can change its state. While back bias slows the performance of the transistor, it greatly reduces
leakage. These techniques are often combined with multi-voltages and require additional functionality:
power-management controllers, isolation cells that logically and/or electrically isolate a shutdown power
domain from “powered-up” domains, level-shifters that translate signal voltages from one domain to
another, and retention registers to facilitate fast transition from a power-off state to a power-on state for a
domain.
The EDA industry responded with multiple vendors developing proprietary low-power specification
capabilities for different tools in the design and implementation flow. Although this solved the problem
locally for a given tool, it was not a global solution in that the same information was often required to be
specified multiple times for different tools without portability of the power specification. At the Design
a
Information on references can be found in Clause 2.
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viii
IEC 61523-4
IEEE Std 1801-2013 x
Automation Conference (DAC) in June 2006, several semiconductor/electronics companies challenged the
EDA industry to define an open, portable power specification standard. The EDA industry standards
incubation consortium, Accellera Systems Initiative, answered the call by creating a Technical
SubCommittee (TSC) to develop a standard. The effort was named Unified Power Format (UPF) to
recognize the need of unifying the capabilities of multiple proprietary formats into a single industry
standard. Accellera approved UPF 1.0 as an Accellera standard in February 2007. In May 2007, Accellera
donated UPF to the IEEE for the purposes of creating an IEEE standard, and in March 2009, the first version
of the IEEE Std 1801 was released. So this standard, although the second version of the IEEE Std 1801,
represents the third version of what is more colloquially referred to as UPF.
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ix
IEC 61523-4
xi IEEE Std 1801-2013
Notice to users
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iv
IEC 61523-4
IEEE Std 1801-2013 xii
Essential Patent Claims may exist for which a Letter of Assurance has not been received. The IEEE is not
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v
IEC 61523-4
1 IEEE Std 1801-2013
Design andVerification of
Low-Power Integrated Circuits

IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or
environmental protection in all circumstances. Implementers of the standard are responsible for
determining appropriate safety, security, environmental, and health practices or regulatory requirements.
This IEEE document is made available for use subject to important notices and legal disclaimers. These
notices and disclaimers appear in all publications containing this document and may be found under the
heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.”
They can also be obtained on request from IEEE or viewed at http://standards.ieee.org/IPR/
disclaimers.html.
1. Overview
1.1 Scope
This standard establishes a format used to define the low-power design intent for electronic systems and
electronic intellectual property (IP). The format provides the ability to specify the supply network, switches,
isolation, retention, and other aspects relevant to power management of an electronic system. The standard
defines the relationship between the low-power design specification and the logic design specification
captured via other formats [e.g., standard hardware description languages (HDLs)].
1.2 Purpose
The standard provides portability of low-power design specifications that can be used with a variety of
commercial products throughout an electronic system design, analysis, verification, and implementation
flow.
1.3 Key characteristics of the Unified Power Format
The Unified Power Format (UPF) provides the ability for electronic systems to be designed with power as a
key consideration early in the process. UPF accomplishes this by allowing the specification of what was
traditionally physical implementation-based power information early in the design process—at the register
transfer level (RTL) or earlier. Figure 1 shows UPF supporting the entire design flow. UPF provides a
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.

IEEE Std 1801-2013
IEEE STANDARD FOR DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS
IEC 61523-4
IEEE Std 1801-2013 2
consistent format to specify power design information that may not be easily specifiable in an HDL or when
it is undesirable to directly specify the power semantics in an HDL, as doing so would tie the logic
specification directly to a constrained power implementation. UPF specifies a set of HDL attributes and
HDL packages to facilitate the expression of power intent in HDL when appropriate (see Table 4 and
Annex B). UPF also defines consistent semantics across verification and implementation, i.e., what is
implemented is the same as what has been verified.
UPFUPF
HDHDLL
(RTL(RTL))
SySynnthethessiiss
UPFUPF
VerilogVerilog
(N(Netlist)etlist)
P & P & RR
UPUPFF
VerVerilogilog
(Ne(Nettlislistt))
Figure 1—UPF tool flow
As indicated in Figure 1, UPF files are part of the design source and, when combined with the HDL,
represent a complete design description: the HDL describing the logical intent and the UPF describing the
power intent. Combined with the HDL, the UPF files are used to describe the intent of the designer. This
collection of source files is the input to several tools, e.g., simulation tools, synthesis tools, and formal
verification tools. UPF supports the successive refinement methodology (see 4.8) where power intent
information will grow along the design flow to provide needed information for each design stage.
— Simulation tools can read the HDL/UPF design input files and perform RTL power-aware
simulation. At this stage, the UPF may only contain abstract models such as power domains and
supply sets without the need to create the power and ground network and implementation details.
— Synthesis tools can read the HDL/UPF design input files and produce a netlist. The tool or user may
produce a new UPF fileset that, combined with the netlist, represents a further refined version of
same design.
— In those cases where design object names change, a UPF file with the new names is needed. A UPF-
aware logical equivalence checker can read the full design and UPF filesets and perform the checks
to ensure power-aware equivalence.
— Place and route tools read both the netlist and the UPF files and produce a physical netlist,
potentially including an output UPF file.
Published by IEC under license from IEEE. © 2013 IEEE. All rights reserved.
SiSimmuulalattiioonn,L,Logogiicacall EEqquuivivaallenenccee ChCheecckkiingng,, .

IEEE Std 1801-2013
IEEE STANDARD FOR DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS
IEC 61523-4
3 IEEE St
...