ISO 6951:1986

Foreword
ISO (the International Organization for Standardization) is a worldwide federation of
national Standards bodies (ISO member bodies). The work of preparing International
Standards is normally carried out through ISO technical committees. Esch member
body interested in a subject for which a technical committee has been established has
the right to be represented on that committee. International organizations, govern-
mental and non-governmental, in liaison with ISO, also take part in the work.
Draft International Standards adopted by the technical committees are circulated to
the member bodies for approval before their acceptance as International Standards by
the ISO Council. They are approved in accordance with ISO procedures requiring at
least 75 % approval by the member bodies voting.
International Standard ISO 6951 was prepared by Technical Committee ISO/TC 97,
Information processing s ystems.
Users should note that all’ International Standards undergo revision from time to time
and that any reference made herein to any other International Standard implies its
latest edition, unless othetwise stated.
International Organkation for Standardkation, 1986
Printed in Switzerland
ii
ISO 6951-1986 (El
Contents Page
0 Introduction .
1 Scope and field of application .
2 Definitions. . 3
3 Designation of a particular Eurobus .
4 Compliance .
5 Protocols for Eurobus A .
6 Electrical and timing requirements . 11
Annexes
................................... 20
A Eurobus lO/A logical implementation
................................... 20
B Eurobus 18/A logical implementation
...................................
C Eurobus 26/A logical implementation
...................................
D Eurobus 34/A logical implementation
.................................................
E Connector allocation
................................
F Examples of application of protocol rules
.......................
G Method of address allocation for mixed data widths
.............................
H Example of Eurobus backplane construction
........ 43
: Forced air convection cooled double Eurocard
J Mechanical Option 1
......................................................
K Extenderpanel
..............
L Examples of the application of Eurobus A timing requirements
.......................................
M Bus receiver a.c. noise rejection
........
N Test circuit and waveform for determination of transient sink current
...............................................
P Publications referred to
. . .
Ill
This page intentionally left blank

INTERNATIONAL STANDARD
ISO 6951-1986 (E)
Information processing - Processor System bus interface
(Eurobus A)
The full addressing capability of the bus enables devices
0. lntroduction
to address any 8-bit byte of any word in a normal address
0.1 General. This Standard specifies the set of Signal lines
space defined by both of the following.
that constitute the bus itself, and the interfacing of devices
connected to the bus. (a) The addressing range determined by the number
of data/address bits.
This Standard specifies protocols for the allocation of bus
time to devices wishing to make transfers and for the (b) A two-bit extension to the foregoing (a). The full
transfer of data between devices. The Standard does two-bit extension is available on buses with non-shared
not, however, specify priority rules, these being left to width, but on shared-width buses the use of these bits
be formulated individually for each System. is restricted.
This Standard specifies a full set of signalling rules to be In addition, any complete word tan be addressed in a
followed by the device responsible for bus allocation and second address space of equal magnitude to the first,
by devices conducting transfers. Annex F gives illustrative designated the pseudo address space.
examples of each of the possible types of transfer.
0.3 Devices. Free choice is available to the System designer
The’set of electrical and Signal timing requirements as to the devices connected to a Eurobus and the Order in
specified in clause 6 uniquely defines the interface that
which they are connected. However, each bus needs to
is Eurobus A. Certain mechanical requirements are specified include both:
in clause 6, namely those that directly affect the electrical
(a) an arbiter, the purpose of which is to control the
characteristics (e.g. the physical length of the bus,
timedivision multiplexing of transfers on the bus;
the spacing of device connectors on the bus, the pin pitch
(b) if communication with other buses is required, a
on connectors and the Signal disposition on the connectors),
bus link to each of the other buses.
but this Standard does not further specify the mechanical
Figure 1 Shows an example of a bus with a number of
implementation. An example of a possible mechanical
typical devices including an arbiter and a bus link.
implementation of Eurobus A is given in annex J.
0.4 Bus allocation. Information is transferred between
Implernentations of Eurobus A are possible with 8, 16,24,
devices on a master-and-Slave basis. A device bids for
-bit data widths and devices having different data
32,.
control of the bus by means of its starred Request line
widths tan operate on the same bus. Logical implementa-
and becomes the master device for that transfer after
tion summaries for the first four of the possible data
the arbiter has allocated the bus to it. This Standard
widths are given in annexes A to D. Annex E specifies the
specifies the protocols by which devices bid for use of
connector allocation.
the bus and by which the arbiter allocates the use of the
The group of Signal iines constituting an assembled
bus to one of them. The Standard does not, however,
Eurobus A provides the means for the transfer of binary
specify the algorithm used in making the selection,
digital information between up to 20 devices plugged into
thus the System designer is given the choice of an
the backplane of a Single equipment shelf. Devices share
allocation algorithm in Order to optimize System
the bus on a timedivision multiplex basis. The length of
Performance.
the backplane is limited to a maximum of 460 mm.
The Signal lines form an asynchronous unbalanced voltage
The protocol whereby a master device may flag an
interface capable of operating at transfer rates of up to
interrupt to the arbiter is also specified, but the
6,5 x IO6 words or bytes per second.
subsequent action by the arbiter is left to the System
designer to define.
0.5 Bus transfers. In addition to specifying the protocols
0.2 Data width and addressing capability. The data/
for the execution of Read cycles (in which the master
address width of any device using the bus is theoretically
addresses a device as Slave and reads data from it) and
unconstrained. However, the asynchronous protocols
Write cycles (in which the master transfers data to the
and addressing facilities of Eurobus A permit devices of
addressed Slave), this Standard also specifies the protocol
8, 16, 24 and 32-bit data widths to share the Same bus,
and when the bus is so shared, the maximum data width for a Vector cycle in which an address, without data,
is transferred from master to Slave.
is that of the widest device.
ISO 6951-1986 (E)
PROCESSOR DMA-PERIPHERAL
Normaily operates as As no one processor is
INTERFACE
Master device, but tan act deemed to be the Master
CONTROLLER
as Slave when in receipt device on the bus, several Controls the transfer of data
procossors may be
of interrupts. to or from a user peripheral,
connected to the Same bus. performs DMA bus transfers
as a Master device and
receives control words as a
Slave.
1 J
ARBITER
Allocates use of the bus to I
requesting Master devices. 1
I
t
t
J RECUEST LINES
BUS ‘A’
I
MEMORY MEMORY MAPPE0
BUS LINK
Blocks of memory are PERIPHERAL INTERFACE Permits information to be
normally Siave devices, i.e.
CONTROLLER transferred between the two
they respond to transfers This Slave device controls
buses to which it is
initiated by other (Master) the activity of a user
connected.
devices. peripheral.
BUS ‘B’
l
Figure 1. Eurobus with some typical devices
(c) the required characteristics of the bus transmitters
The bus allocation protocols permit a master to hold the
and receivers;
bus for repeated use without the need to make a fresh
bid for every transfer, while also giving the arbiter the
(d) the required characteristics of the spurs to be
abiiity to instruct any master to release the bus for
connected to the bus.
reallocation. A master is also permitted to retain the bus
The specified set of eiectricai characteristics presupposes
for an indivisible sequence of cycles, such as a Read-
certain bus settiing times for the transitions on the Signal
Modify-Write sequence. An additional protocoi is defined
iines. Arising from these, certain timing constraints are
whereby the arbiter may abort a cycle that is deemed to
specified. These constraints ensure that the relevant
have failed.
Signal iines will have settled to the appropriate state before
0.6 Interbus transfers. The protocols for Read, Write and
an associated control Signal transition is issued.
Vector cycles permit a master on bus A, for exampie,
0.8 Commercial and military Versions. Two Versions of
wishing to effect a transfer with a Slave on bus B,
Eurobus A are specified in this Standard, a version for a
to address a bus linker on bus A as Slave. The bus linker
commerciai temperature range (0 *C to 70 “C) and a
then bids for use of bus B as master and addresses the
Version for a military temperature range (-55 *C to
required Slave on bus B. Should master devices on both
125 “C). Where the requirements are different they are
buses attempt simultaneous transfers, the bus link cannot
separateiy specif ied for each Version.
become master on either bus and a condition of deadly
embrace ensues. The Eurobus protocois permit the
embrace to be broken simply.
The protocols used by bus links to perform interbus
1. Scope and field of application
addressing and data transfer are not within the scope
This International Standard specifies a processor System
of this Standard.
bus interface known as Eurobus A (referred to in the
0.7 Electrical requirements. The Standard specif ies the
following text as “the bus”) that is one of a family of in-
electrical and timing requirements that need to be obeyed
terfaces for use in modular data acquisition, processing
by Eurobus A devices. Aspects covered within the electrical
communication and control Systems for military, industrial
requirements include:
and other applications.
NOTE 1. More detailed information about the requirements
(a) the voltage levels of the active and quiescent logic
specified in this international Standard, including the data width
states on the bus;
and addressing capability, devices connected to the bus, bus
(b) the required characteristics of the termination
allocation, bus transfers, interbus transfers and electrical re-
networks; quirements, and background information are given in clause 0.
ISO6951-1986(E)
2.19 indivisible Operation. A sequence of bus cycles for
NOTE 2. In this International Standard, upper case letters are
used for the first letter of names of bus cycles. which the correct System function tan only be guaranteed
if no other bus cycles occur within that sequence,
NOTE 3. The titles of the publications referred to in this lnter-
national Standard are listed in annex P. e.g. a Read-Modify-Wri te sequence.
2.20 interb us transfe r. A transfe r of inf ormation between
2. Definitions
devices that uses two 0 r more bu ses and one or m ore bus
For the purposes of this International Standard the follow-
Imkers.
irig definitions apply.
2.21 interrupt. A flag passed to the arbiter by a device
2.1 address. The location of a data word, or the value on
in Order to initiate a predetermined system-dependent
the highway during the addressing phase of any Read,
function.
Write or Vector cycle.
2.22 master. The device that initiates the transfer in
2.2 arbiter. The device that performs the function of
question.
arbitration for the bus and is also responsible for servicing
2.23 normal address space. An addressing space whose
interrupts and for timing-out failed cycles and aborting
size is determined by the number of lines in the highway
them.
and that is addressable as words or bytes.
2.3 arbitration. The means whereby use of the bus is
2.24 protocol. The signalling ruies used to convey
allocated to one of the bidding devices which then becomes
information or commands between devices connected
the master.
to the bus.
2.4 backplane. The assembly of the bus with connectors
2.25 pseudo address space. A second, independent
into which spur cards may be plugged.
addressing space whose size is determined by the number
2.5 bidding device. A device that wishes to initiate a cycle of lines in the highway and that is addressable as words
or group of cycles on a bus and that requests use of the
only.
bus.
2.26 Read cycle. A bus cycle in which the master obtains
2.6 bus. complete set of bus lines used by a particular
The a word or byte from the Slave.
implerne ntati on of Eurobus.
2.27 reset. The operat io n whereby each dev ice con nected
2.7 bus cycle. A closed group of Signals on the bus that
to th e bus is put into a redetermined in itial condit ion.
P
convey information between devices connected to it.
2.28 Retain cycie. A bus cycle at the end of which the
This group consists of an addressing Phase, in which the
master keeps control of the bus in Order to complete an
master places an address on the highway for recognition
indivisible Operation.
by a Slave and, except in Vector cycles, a subsequent data
2.29 settiing time. The time taken for a bus line to settle
transfer Phase.
unambiguously into its new logical state from its previous
2.8 bus line. An electrical connection between two or
state.
more devices.
2.30 shelf. The physical structure that supports the
2.9 bus linker. A device that plugs into two or more buses
backplane and the cards that plug into it.
thus providing a means whereby a master on one bus may
2.31 skew. On the assumption that two logical transitions
transfer information to or from a Slave on another bus.
are launched simultaneously on two bus lines, the time
2.10 bus voitage. The voltage on a bus line measured
differente betwecn the receipt of those transitions at a
relative to the bus zero voltage reference.
given pair of receivers on a card connected to the bus at
2.11 byte. A contiguous group of 8 bits.
.
the Point in question.
2.12 circuit card. A card on which various electronie
2.32 s lave. The device that r esponds to the address
placed
components are mounted and that plugs into a Eurobus
on the bus by the mast er for the cycle in question.
backplane as a Spur.
2.33 Spur. Device connected to the bus at some Point
2.13 data. The information held at, written to, or read
between th
e two ends of the bus.
from an address.
2.34 state (of a bus line). 0ne of two conditions of a
2.14 deadiy embrace. The conditions when two interbus
bus line, namely active or quiescent.
transfers, using the same bus linker, have been commenced
2.35 Vector cycle. A bus cycle in which the purpose is
and neither transfer tan be completed.
to pass an address from a master to a Slave and in which
2.15 device. A functional block, occupying one or more
no data transfer takes place.
circuit cards, that communicates with other functional
2.36 word. A group of bits whose number corresponds
blocks by means of the bus or a subset of the bus.
to the maximum data width that tan be conveyed over
2.16 extender Panel. A circuit card that tan be inserted
the bus in a Single transfer.
between the bus and another circuit card to permit easy
2.37 0 V. The Signal return path and, as such, the reference
access to the latter while it is still connected to the bus.
for all voltage measurements.
2.17 Hold cycles. A sequence of cycles during which the
NOTE. 0 V is not a safety earth. Where a safety earth is referred to
master is not asked by the arbiter to release the bus for
in this Standard, it is specifically identified.
reallocation.
2.38 Write cycle. A bus cycle in which a master writes a
2.18 highway. Those bus lines used to convey data and
word or byte to a Slave.
addresses between devices on the Eurobus.
ISO 6951-1986 (El
Statement of the limitations imposed on a System into
3. Designation of a particular Eurobus
which the device may be incorporated.
Esch member of the Eurobus A famity shall be designated
4.4 Mechanical compliance. Connector allocations for
using the following format.
data widths of 8, 16, 24 and 32 bits shall be as specified
in annex E.
Eurobus address width /A qualifying information
5. Protocols for Eurobus A
The designation entries shall be determined as follows:
5.1 Preliminary
(a) address width = 10 or 18 or 26 or 34 . . . etc.,
as appropriate (see note 1);
5.1.1 Genera/. The set of Signals constituting Eurobus A
shall be as specified in 5.2. The protocols, for use of those
(b) A designates the electrical characteristics specified
Signals for the allocation of the bus to potential users and
in clause 6;
thereafter for effecting transfers on the bus, shall be as
(c) qualifying information is additionai text stating the
specified in 5.3 and 5.4.
Version (see 0.8) and, optionally, text to enable users
NOTE 1. Annex F gives illustrative examples of the Operation
to identify a particular mechanical implementation.
of the bus protocols in accordance with these requirements.
NOTE 1. The address &dth is the number of highway bits,
NOTE 2. Any transfer using the Eurobus protocols generally
i.e. the number of data bits plus two.
involves three devices:
NOTE 2. It is recommended that sufficient qualifying information
(a) the arbiter which:
should be provided to enable users and potential users to identify
a particular mechanical implementation of Eurobus.
(1) grants use of the bus to a bidding device that then
becomes the bus master; or
NOTE 3. For example, an 18-bit address implementation of
Eurobus A (omitting optional qualifying information) is designated
(2) allows an existing master to continue using the bus;
‘Eurobus 18/A commercial’.
(b) the master device that initiates the transfer by addressing
another device;
4. Compliance
(c) the device that, having recognized the address, accepts the
transfer and so becomes the bus Slave.
4.1 Full compliance of devices. Devices that are Said,
without qualification, to comply with this International
5.1.2 Basic bus cycles. There shall be three basic types of
Standard, shall comply with :
bus cycle (see table ‘l) as follows.
(a) the logical requirements of clause 5;
(a) Read cycle in which data is read from a Slave
device by a master device.
(b) the electrical requirements of clause 6;
(b) Write cycle in which data is written to a Slave
(c) the requirements for connector allocation (see 4.4).
device by a master device.
4.2 Logical compliance
(c) Vector cycle in which an address is transferred
4.2.1 Devices said to be logically compliant shall comply
from the master device to the Slave device.
with the protocol requirements of clause 5 or with an
NOTE. The address used by the master device to identify one
appropriate subset of those requirements.
of a set of locations recognized by a Slave device is the only
NOTE. For example, a slaveonly device need not be capable
information transferred over the bus in a Vector cycle.
of acting as a bidding device.
5.1.3 Bus cycle variants. The number of possible variants
4.2.2 In an implementation said to be logically compliant,
of each basic type shall be two, as follows:
either:
(a) Read and Hold;
(a) the bus lines shall be used only for the purposes
(b) Read and Retain;
specified in this International Standard; or
(c) Write and Hold;
(b) if one or more of the bus lines is used for purposes
(d) Write and Retain;
not so specified:
(e) Vector and Hold;
(1) normal Signals on the bus between devices that
operate according to the specified protocols shall
(f) Vector and Retain.
not Cause any malfunction in the implementation
NOTE 1. The main purpose of a Hold cycle is to allow devices
concerned;
that have a requirement for numerous bus cycles, e.g. processors,
to access the bus repeatedly without having to bid for each
(2) Signals generated within that implementation
individual cycle. Because the use of such a cycle tan delay the
shall not Cause malfunction in devices, connected
reallocation of the bus to another device, such cycles are only
recommended where there is a high probability that the device
to the bus, that operate according to the protocols
concerned will make use of the next bus cycle.
specified in this International Standard.
The main purpose of Retain cycles is to enable indivisible
4.3 Electrical compliance. Devices said to be electrically
.operations to be performed, e.g. Read-Modify-Write.
compliant shall eitber:
NOTE 2. The differentes between these variants and the basic
cycles concern the time at which the bus is released by the device
(a) comply with 6.1 and 6.2, relating to the electrical
for reallocation by the arbiter.
requirements of devices; or
NOTE 3. The bus allocation protocol is designed so that:
(b) when incorporated into a bus, not prevent that bus
(a) the minimum avoidable deiay is experienced when
from complying with 6.3, relating to the electrical
allocating an idle bus;
requirements of buses.
(b) wherever possible, bus allocation is overlapped with bus
If a device is togically compliant (see 4.2) and is electricat-
cycles in Order to reduce delays;
ly comptiant in accordance with item (b) (i.e. not in ac-
(c) a device that requires numerous bus cycles, such as a
cordante with item (a)), alt descriptions of the device that
processor, does not necessarily have to make a fresh request
for each cycle;
refer to this International Standard shall inctude an explicit
ISO 6951-1986 (El
Such Codes shall be ailocated by data width in Order
(d) a device tan perform indivisible cycles (this provides the
facility necessary, for example, for the construction of a
from the smallest widths to the largest width, and any
Ready-Modify-Write cycle from a Read cycle followed by a
code that has then been aliocated shall not be available
Write cycle);
for ailocation to another data width as follows.
(e) a device tan, as an alternative to performing a Read,
(1) If the second, third or fourth block is already
Write or Vector cycle, Signal an Interrupt to the arbiter which
is then responsible for servicing the Interrupt. ailocated for recognition by B-bit devices, 16-bit
devices shall be allocated the next higher available
5.2 Signalling
block;
5.2.1 Use of bus lines. All communication between the
(2) If the second, third or fourth block is already
arbiter, devices acting as master and devices acting as Slave
aliocated for recognition by B-bit or 16-bit devices,
shaii be over the Eurobus protocol lines as specified in
24-bit devices shall be allocated the next higher
table 1. The usage of these lines shali be such that any
available block.
device, or severai devices simuitaneously, tan Cause a
line to be active. If no device has caused a iine to be active, (3) if the se cond, third or fourth block is already
that line shall be quiescent. allocated for recognition by B-bit, 16-bit or 24-bit
devices, 32-bit devices shall be allocated the next
5.2.2 Bitnumbering. The bit number, (IV), of the most
higher available block.
significant data and address line shall be given by:
C Any unused b locks shall be available for extending
( 1
N=Bp- 1
the address range of an y of the devices.
where
5.4 Eurobus A protocol rules
p is any positive integer.
5.4.1 Preliminary. The rules for the use of the bus lines
The bit number (M) of the most significant byte address
specified and named in table 1 shall be as specified in 5.4.2
line shall be given by:
to 5.4.6, as foliows:
M = the largest positive integer that is
(a) for devices bidding for, and the arbiter granting,
less than log2 [UV + 1 )/81
use of the bus; 5.4.2, rules Al to AK?;
Ie, in Order to address one of two bytes in a
NOTE . For examp
word :
16-bit data
(b) for a device acting as master selecting and
N = 15and
communicating with a device acting as Slave; 5.4.3,
M < log, 16/18, i.e.M < 1
rules Ml to Mll;
* M = 0, i.e. only one byte address line is required.
. .
(c) for a device acting as Slave responding to the
master; 5.4.4, rules Sl to S6;
5.2.3 Byte mode address selection. The current bus master
shail specify, by coding the Byte Working and Byte Address
(d) for the arbiter aborting a bus cycle; 5.4.5,
Iines, as given in table 2, the selection of either full-word
rules Cl to C4;
working, or byte working. If full-word working is selected,
(e) for a device, being a bus linker, requesting
the coding shall further specify the selection of pseudo or
deallocation of the bus; 5.4.6, rules Dl to 02.
normal address space. If byte-working is selected,
NOTE. Within this Point-numbered text the rules and conditions
the coding shall further specify which byte is addressed
have been arranged and identified, in Order to aid understanding,
and pseudo address space shall then be unavailable.
by use of a code of upper case letters, lower case letters and
small roman numerals. Esch rule is designated by a letter and
5.3 Address recognition protocol
number (e.g. ‘A 9’). Within each rule the alternative (‘or’)
5.3.1 Data width. The fuil addressing capabiiity of the
conditions are distinguished by lower case letters while
highway, 2(N+3) bits provided by Ad, Ad, simultaneous (‘and’) conditions are distinguished by small
roman numerals.
H(N) to H(o), is available on a bus having oniy devices
all of equal data widths. The use of this capabiiity shall
5.4.2 Rules for bus a//ocation
be by the method given in table 3 for a data width of
Rule Al. When device n requires use of the bus it shall
8 bits.
bid for the bus by holding .m active. lt shall do this
For buses that include devices having unequal data widths,
if and only if:
the method of address aliocation shall be as specified in
i it is not locked (rules A7 and A12); and
( 1
annex G.
(ii) BusGr is quiescent; and
NOTE. The functioning of the bus is not dependent on this method.
(iii) Rs is quiescent.
5.3.2 Recognition of address modifier bits. Any Slave
Rute A2. The arbiter shall allocate the bus to one of the
device operating on a bus that it is sharing with other
bidding devices by also holding the appropriate Rq(n)
devices having different data width(s) from itself, shall in
line active. lt shail do this if and only if:
all instances recognize one coding and one coding only
i Rq(n) is already active; and
( 1
on the Address Modifier lines.
(ii) the arbiter is not aiready holding a Rq line
The specific Codes recognized by devices of a particular
active; and
data width shall, in any System, be aiiocated according to
(iii) Bu is quiescent; and
the following rules.
BusAcq is quiescent; and
(4
under the heading first
(a) The Codes listed in table 4
V i? is quiescent; and
( )
first b e all ocated.
block (columns 3 and 4) shaii
Bus Deallocate is quiescent; and
bd
(b) If further Codes are required, the Codes listed under (vii) CcAbort is quiescent; and
the headings second block, third block and fourth block
(viii) Rs is quiescent.
(columns 5 to 10) shall be aiiocated in that Order.

ISO 6951-1986 (E)
Table 1. Eurobus A protocol lines
Number of Requirements
Signal name
lines
(abbreviations)
High wa y lines
Time division multiplexed bi-directional data and address lines. WÖ) shall be
Data/Address N+l
associated with the least significant bit. The number of the most significant
(H(O)to ‘Ri)
bit, H(N), shall be determined as specified in 5.2.2
2 Address Modifier Iines. These are available and shall be used when it is
Address Modifier
--
required to increase the address range beyond that definable by H(O) to H(N),
Bits (0), (1)
and also for selection between devices of different data width that share the
(AdM(O), Aii)
same bus (see 5.3)
Byte mode/address space selection lines
Byte Working These lines shall be used to qualify the address on the highway in terms of the
(&-iiE) byte mode/address space selection coding (see 5.2.3). The number of the most
significant Byte Address bit, (M), shall be determined as specified in 5.2.2
Byte Address M-t1
If N=7 the Byte Working line shall remain quiescent
Bits (0) to
(BytAd(Oj to
BytAdo)
Bus allocation pro tocol lines
Request(n) One Request Iine shall be star-connected to the arbiter from each device that
1 per potential
requires to be able to bid for bus allocation
(Rq(,J) bus master
Request(n) line shall be activated by device(n) to Signal its bid for bus
allocation. The arbiter shall activate the Request line, in conjunction with
the Bus Granted line, to allocate use of the bus to device(n)
Bus Granted
1 This line shall be activated by the arbiter at the same time as it activates
(BusGT) the Request line of a particular device in Order to affect a new bus allocation.
The device in question shall then be the current bus master for the next
transfer
This line shall also be activated by the arbiter without activating a Request
line to deallocate the current bus master (see 5.4.5)
Bus Acquired This line shall be activated by the current bus master to signify that the bus
(BusAcq) grant has been accepted. The line shall be held active by a Slave if that Slave
is about to activate the Bus Deallocate line
Interrupt This line shall be activated by the current bus master to indicate to the arbiter
-
that its request is for an Interrupt cycle
(It)
Transfer con trol handshake lines
Cycle Begin
1 This line sh&1 be activated by the current master device to indicate that:
(CcBn)
(a) there is a stable address on the highway and byte mode/address space
selection lines;
(b) the Cycle Finish line (which at this Point of the transfer indicates
ReadlVector cycle or Write cycle) is stable
This line shall be activated by a device to indicate that it has recognized the
Cycle Response
address on the highway and has become the current bus Slave. On detecting
(CcRes)
that this line has become active the master shall remove the address from
the highway
Cycle Finished This bi-directional line shall be activated:
(Em)
(a) by the current master:
(1) in a Read cycle to indicate that the address has been removed;
(2) in a Writ e cycle to identify the cycle as a Write cycle and,
when released, to indicate that Write data has been removed;
(b) by the current Slave during the transmission of Read data
ISO 6951-1986 0
Table 1 (concluded)
Requirements
Signal name Number of
(abbreviations) lines
Cycle Abort This line shall be activated by the arbiter to terminate an invalid bus cyck
(ecAbort)
Reset line. This line shall be connected to all devices on the bus. When the
Reset (E)
line is activated by any device that is permitted to do so, it shall Cause a
general bus reset Operation
This line shall be activated by a bus link device in Order to indicate to an
Bus Deallocation
arbiter either:
(BusDeallocate)
(a) that the bus link requires a deadly embrace to be broken; or
(b) that the arbiter is required to ask the bus master to release the bus
for reallocation.
The state of the Cycle Response line shall be used to specify which of the
indications is valid at the time the Bus Deallocate line is activated
Table 2. Coding of byte mode/address space selection lines
-v
BytWk BvtAd(M) BytAd(M - 1) BytAd Selection
X X The whole word (N+l bits) in normal address space
Q Q x
X X
Q Acv X The whole word (N+l bits) in pseudo address space
Acv Q Q Q Q Least significant byte (byte 0)
,
Acv Q Q Q Acv Byte 1
. . . . .
in normal
.
address space
icv Acv Acv Acv a Byte (2(M+l) - 2)
Acv Acv cv Acv Acv Byte (2(M+l) - 1)
IA ’
NOTE 1. In table 2 and later tables the abbreviation ‘Acv’ signifies the active state, and ‘Q’ signifies the quiescent state. Symbol ‘X’
signifies that either state may exist.
NOTE 2. For values of M and N see 5.2.2.
Table 3. Address recognition protocol (N = 7)
dMd(l) dMd[a Addresses Data
Fourth block
Wi
Acv Acv for 8-bit
devices Ho
Third block
H(7)
Acv Q for 8-bit
-- .-
devices
H(O)
Second block Ho
Acv for 8-bit
devices
N@)
First block H(71
Q for 8-bit
devices H(O)
NOTE. See note 1 to table 2.
ISO 6951-1986 (E)
Table 4. Address modifier Codes to be recognized by Slave devices of different widths
sharing the Same bus
Device Address modifier code for recognition of address block
Bus
/-
data width data width
Second bl :k Third block
First block Fourth block
(bits) (bits)
7--
AdM(1) AdM(0) AdM( 1) AdM(0) AdM(1) AdM(0) AdM(1) AdM(0)
t
-
0 Q Acv ’ Q Acv Acv -
Acv Acv Q Acv Acv Q Q
16 Q
-
Q
8 Q 0 Acv Acv Acv -
- -
16 Q Acv Acv Acv Q Q
Acv Q Acv Acv Q 0 Q Acv
- -
Q Q Q Acv Acv Q
- .-
Q Acv Acv Acv Q Q
-
Q Q 0 Q Acv -
24 Acv
Acv Q Q Q Acv Acv Q
32 Acv
I I 1 I 1
- -
NOTE. See note 1 to table 2.
--
(biv) the device is not holding CcFm active; and
Rule A3. The arbiter shall hold Bus@ active if and
only if:
b V 1 the device is about to hold Bus Deallocate
the arbiter has made an allocation under active according to rule Dla or (after
bi)
rule A2; and application of rule Sl) rule Dlb; and
. .
I Rs is quiescent; (bvi) m is quiescent; and
(a 1)
NOTE. Bus allocation is complete. (bvii) Rs is quiescent.
the arbiter is not holding a e line active; NOTE. The Slave device holds Busffcq active before
(bi) or,
E, if it intends to ask the arbiter to remove
and
allocation from the current master, or before
(bii)
CcBn is active; and
Bus Deallocate, if it intends to refuse the cycle.
(biii) CcRes is quiescent; and
Ruie A6. Alternatively to rule A5, a device shall hold E
(biv) Bus Deallocate is active; and
active, and thus initiate an Interrupt cycle, if and only if:
V CcRes was quiescent when Bus Deallocate
b 1
i BusC;r is active; and
( 1
became active; and
(ii) ’ its & line is active (and it is not itself
(bvi) Rs is quiescent.
holding this line active); and
--
NOTE. The arbiter deallocates the cycle that the
(iii) it is not holding BusAcq active; and
Slave has refused.
CcAbort is quiescent; and
bd
Rule A4. A bidding device shall release its 6 line if
V Rs is quiescent.
( 1
and only if:
NOTE. The master generates an interrupt to
a Bus& is active;
( 1
the arbiter.
Rs is active.
M or,
Rule A7. A device shall become locked if and only if:
Rule A5. A device shall hold mq active, if and only if:
it holds BusAcq active according to rule A5a;
M
BusGr is active; and
bi)
it holds it active according to rule A6.
Ud or,
(aii) its & line is active (and it is not itself
Rule A8. The arbiter shall release BusGr if and only if:
holding this line active); and
BusAcq is active; and
bi)
(aiii) Ccßn is quiescent; and
(aii) Bus Deallocate is quiescent:
(aiv) CcRes is quiescent; and
‘8
NOTE. The arbiter acknowledges bus acquisition.
CcFin is quiescent; and
bv)
(bi) or, fi is active; and
(avi) the device is not holding the fi line active;
(bii) Bus Deallocate is quiescent;
and
NOTE, The arbiter acknowledges an interrupt.
(avii) CcAbort is quiescent; and
(ci) or, it is not holding a RT line active; and
(aviii) Rs is quiescent;
(cii) BusAq is quiescent;
NOTE. The master acquires the bus.
NOTE. The arbiter completes the bus deallocation
(bi) or, CcRes is quiescent; and
handshake.
(bii) Ccßn is active; and
(di) or, it is holding CcAbort active; and
(biii) the Signals on the highway and byte mode
(dii)
Bus Deallocate is quiescent;
lines correspond to an address recognized
Rs is active.
(4 or,
by the device; and
ISO 69514986 (El
it releases BusAcq (rules AlOa and AlOb) after
Ud or,
Rule A9. The arbiter shall release any Rq line it is
completion of one cycle as master (rules M9b,
currently holding active if and only if:
M9c and Ml Ia) and before commencement of
m is quiescent; and
(4
another (rule M 1);
BusAcq is quiescent; and
(aii)
NOTE. The master releases the bus for reallocation
(aiii) fi is quiescent; and
following a Hold cycle or a Retain cycle.
the arbiter is not about to hold BusGr under
(aiv)
it releases fi under rule Al la;
(4 or,
rule A3;
NOTE. This is the end of Interrupt cycle.
NOTE. The last allocated master has finished using
(di) or, it completes a cycle as Slave in a Write cycle
the bus.
or a Vector cycle (rules S4a and S4c); and
BusGr is quiescent; and
(bi) or
’
(dii)
it is not holding fi active;
a device holds its & line active; and
(bii)
NOTE. This condition releases the leck following
er
(biii) the arbiter is not about to hold Bus& und
the abortion of a master cycle.
rule A3;
(e) or, it releases BusAcq under rule AlOc;
NOTE. A device requests allocation while the
NOTE. This release is after deallocation.
aliocated master is still using the bus.
(fl w Rs is active.
Bus Deallocate is active;
(~1 or,
NOTE, The arbiter asks the allocated master to
5.4.3 Rules for devices acting as master
release the bus fot reallocation.
Rule Ml. The master shall commence a cycle if and
it is holding CcAboit active;
id) or
’
only if:
Reset is active.
(4 or,
it is holding BusAcq active; and
( i 1
Ruie AlO. A device that is holding BusAcq active shall
CcBn is quiescent; and
(ii)
release it if and only if:
CcRes is quiescent; and
(iii)
the current bus cycle is established (rule M5);
bi)
CcFin is quiescent; and
(iV)
and
V CcAbort is quiescent; and
( 1
(aii) the device’s & line is active; and
Rs is quiescent.
(Vi)
(aiii) it_does not wish to hold the bus for further
NOTE. The cycle Starts after bus f ree.
cycies;
NOTE. Tbc master relinquishes the bus unilaterally. Rule M2. The master shall hold the highway and byte
mode lines to form an address if and only if:
(bi) or, the current bus cycle is established (rule M5);
and
i the cycle is commenced (rule M 1); and
(bii) the device’s & line is quiescent; and
(ii) CcAbort is quiescent; and
(biii) it does not require to retain the bus for an
(iii) Rs is quiescent.
indivisible Operation;
Rule M3. The master shall hold CcFin active if and
NOTE. The arbiter asks the master to release the bus.
only if:
the current cycle is refused (rule M6); and
(ci) or,
bi)
(cii) it is not holding Ccßn active; and
(aii)
(ciii) it is not holding mactive;
(aiii)
NOTE. The master releases the bus in 8 Deallocate
(aiv)
cycle.
NOTE. This is the beginning of a Write cycle.
(di) or it is holding Bus Deallocateactive; and
I
(bi) or the cycle is established (rule M5); and
’
(dii) it is Slave for the current cycle;
(bii) it is not holding an address; and
NOTE. The onus is on the Slave to guarantee that
(biii) it wishes to perform a Read cycle; and
m is active when Bus Deallocate becomes active
(biv) CcAbort is quiescent; and
(sec rules AlOa, AlOb, Sl and Dlb).
it is holding Bus Deallocate active; and V Rs is quiescent.
(ei) or, b 1
remove d from the
it has refused to become Slave for the current NOTE . The address has been
(eii)
bus in a Read cycle.
cycle;. and
Rule M4. The master shall hold CcBn active if and
(eiii) Bu is active;
only it:
CcAbort is active;
(fl or,
it is holding BusAcq active; and
Rs is active. bi)
(9) or,
(aii) it is holding an address; and
Rule Al 1. A device that is holding k active shall release
(aiii) it is holding CcFin active; and
it if and only if:
(aiv) it wishes to perform a Write cycle; and
a BusGr is quiescent;
( 1
CcAbort is quiescent; and
(ad
NOTE. The handshake completes the Interrupt cycle.
(avi) Rs is quiescent;
CcAbort is active;
b) or,
NOTE. The Write address is on the bus.
Rs is active.
ld or,
(bi) or, it is holding BusAcq active; and
Rule Al2. A device shall cease to be locked if and
(bii) it is holding an address; and
only if:
(biii) it wishes to perform a Read cycle; and
a it completes a cycle as master (rules M9b,
( 1
(biv) CcAbort is quiescent; and
M9c and M 1 la) when BusAcq is quiescent;
Rs is quiescent;
bd
NOTE. This is the end of 8 cycle in which the master
released the bus for reallocation.,
NOTE. The Read address is on the bus.

ISO 6951-1986 (E)
(aii) Ccßn is quiescent;
(ci) or, it is holding BusAcq active; and
NOTE. The Slave accepts Write data.
(cii) it is holding an address; and
b) or, CcAbort is active;
(ciii) it wishes to perform a Vector cycle; and
(c) or, Rs is active.
(civ) CcAbort is quiescent; and
kV) Rs is quiescent.
Rule Mll . The master shall release CcFin if and only if;
NOTE. The Vector address is on the bus.
it is not holding Ccßn active; and
bi)
(aii) it is not holding Write data; and
Rule M5. The master shall regard the cycle commenced
under rule M2 as established it and only if CcRes is active (aiii) the cycle is established (rule M5); and
NOTE. The Slave has accepted the address.
(aiv) CcAbort is quiescent;
NOTE. This is the final handshake in a Write cycle.
Rule MB. The master shall regard the cycle commenced
under rule Ml as refused if and only if: (bi) or it is holding CcBn active; and
I
i the master’s Rq line is quiescent; and (bii) CcRes is quiescent; and
( 1
(ii) Bus& is active. (biii) the cycle is established (rule M5);
NOTE. This is a bus deallocation.
NOTE. This event occurs in the middle of a
Read cycle.
Rule M7. The master shall release an address if and
(ci) or, the current cycle is refused (rule M6); and
only if:
(cii) it is not holding an address;
a the cycle is established (rule M5);
( 1
NOTE. This event occurs while a Write cycle is being
the cycle is refused (rule M6);
ib) or,
deallocated.
CcAbort is active;
(4 or,
(di) or, CcAbort k active; and
Rs is active.
(4 or,
(dii) it is not holding an address;
Rule M8. The master shall hold the highway lines to
(ei) or, CcAbort is active; and
form Write data if and only if:
(eii) it is not holding Write data;
i the cycle is established (ruie M5); and
( 1
(fi) or, i% is active; and
(ii) it wishes to perform a Write cycle; and
(fii)
it is not holding an address;
(iii)
CcAbort is quiescent; and
(gi) or, i% is active; and
(iV) Rs is quiescent.
(gii) it is not holding Write data.
Rule M9. The master shall release Ccßn if and only if:
5.4.4 Rufes for devices acting as Slave
it is not holding an address; and
(4
Rule Sl. A device shall hold Cc& active if and only if:
(aii) it is holding Write data on the highway;
i
( 1 Ccßn is active; and
NOTE. This event occurs in a Write cycle.
(ii)
Bus& is quiescent; and
(bi) or it is not holding CcFin active; and
’
--
(‘iii) the Signals on the highway and byte mode
(bii) CcFin is active; and
lines correspond to an address recognized
(biii)
CcRes is quiescent; and
.
by the device; and
(biv) it has accepted the Signals on the highway as
the device is not refusing to become Slave
(iV)
Read data; and
for the current cycle (rule Dla); and
V CcAbort is quiescent;
b 1
V ’ the device is not holding Ccf active; and
( )
NOTE. This event occurs in a Read cycle.
CcAbort is quiescent; and
bi)
(ci) or, it is not holding an address; and
(vii) Rs is quiescent.
(cii) i
...