IEC 60821:1991/AMD1:1999
(Amendment)Amendment 1 - VMEbus - Microprocessor system bus for 1 byte to 4 byte data
Amendment 1 - VMEbus - Microprocessor system bus for 1 byte to 4 byte data
General Information
- Status
- Published
- Publication Date
- 28-Jan-1999
- Technical Committee
- ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
- Current Stage
- PPUB - Publication issued
- Start Date
- 30-Nov-1998
- Completion Date
- 29-Jan-1999
Overview
IEC 60821:1991/AMD1:1999 is Amendment 1 to the IEC 60821 international standard for the VMEbus - microprocessor system bus for 1 byte to 4 byte data. Published in January 1999, this amendment updates signalling definitions, data-transfer rules, timing and arbitration language, mechanical board requirements, and various tables and mnemonics used to describe master/slave capabilities. It clarifies behaviours and tightens mandatory/optional language to improve interoperability of VMEbus modules.
Key topics and technical requirements
- Signal semantics and timing
- Revised definition of WRITE: a level-significant line strobed by the falling edge of the first data strobe (DSA), valid while any data strobe (DSA* or DSB*) is low.
- Corrections to interrupt and acknowledge signal names (e.g., IACK), and changes in arbitration signal identifiers (BRO* → BR0, BGOIN → BG0IN*).
- Data-transfer capabilities and mnemonics
- Stronger normative language: “can accept/monitor” replaced by “must accept/must monitor” in multiple tables for basic, block, and read-modify-write capabilities.
- Specific rules for D08(O) SLAVES forbidding DTACK* during certain byte-location access cycles and clarifying unaligned transfer (UAT) behaviour and permitted cycles.
- Corrections in byte-group mapping and data-line groupings used in multi-byte transfer tables.
- Arbitration and requester rules
- Fair arbiter behaviour clarified: after grant, a requester must monitor its request line and must not issue a new request until that line has been high once.
- Priority interrupt bus
- Updated titles and usage for IRQ1–IRQ7** and IACK, and clarified permissions for interrupt-driving lines.
- Mechanical specifications
- Mandatory board thickness: 1.6 mm ± 0.2 mm in the guide area; updated rules and figures reflecting this requirement.
- Informative and normative annexes
- Appendices updated: some marked normative (connector/pin descriptions, permissible subsets), others informative (metastability and resynchronisation). Metastability guidance and arbitration timing (MTBF considerations) were revised.
Applications and who uses it
- VMEbus hardware designers and module manufacturers implementing 1–4 byte data transfers.
- System integrators and test engineers ensuring interoperability and correct timing/handshaking.
- Standards committees and firmware developers referencing precise signal and arbitration semantics.
- Useful for legacy system maintenance, upgrades, and compliance verification of VMEbus-based embedded and industrial control systems.
Related standards
- Original IEC 60821:1991 (base standard) - this document is Amendment 1 (1999).
- Relevant ISO/IEC JTC1/SC26 working documents referenced for voting and technical basis.
Keywords: IEC 60821 amendment, VMEbus, microprocessor system bus, data transfer, arbitration, interrupts, WRITE*, DSA*, DSB*, D08(O), unaligned transfer, board thickness, metastability.
Frequently Asked Questions
IEC 60821:1991/AMD1:1999 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Amendment 1 - VMEbus - Microprocessor system bus for 1 byte to 4 byte data". This standard covers: Amendment 1 - VMEbus - Microprocessor system bus for 1 byte to 4 byte data
Amendment 1 - VMEbus - Microprocessor system bus for 1 byte to 4 byte data
IEC 60821:1991/AMD1:1999 is classified under the following ICS (International Classification for Standards) categories: 31.080.01 - Semiconductor devices in general; 35.160 - Microprocessor systems; 35.200 - Interface and interconnection equipment. The ICS classification helps identify the subject area and facilitates finding related standards.
IEC 60821:1991/AMD1:1999 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
NORME CEI
INTERNATIONALE
IEC
INTERNATIONAL
STANDARD
AMENDEMENT 1
AMENDMENT 1
1999-01
Amendment 1
VMEbus –
Microprocessor system bus
for 1 byte to 4 byte data
Amendement 1
Bus VMEbus –
Bus système à microprocesseurs
pour données de 1 octet à 4 octets
IEC 1999 Droits de reproduction réservés Copyright - all rights reserved
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: +41 22 919 0300 e-mail: inmail@iec.ch IEC web site http: //www.iec.ch
CODE PRIX
Commission Electrotechnique Internationale
PRICE CODE J
International Electrotechnical Commission
Pour prix, voir catalogue en vigueur
For price, see current catalogue
– 2 – 60821 Amend. 1 © IEC:1999(E)
FOREWORD
This amendment has been prepared by subcommittee 26: Microprocessor systems, of the Joint
Technical Committee ISO/IEC JTC 1: Information technology.
The text of this amendment is based on the following documents:
Text Report on voting
ISO/IEC JTC1/SC 26 N 237 ISO/IEC JTC1/SC 26 N 218
Full information the voting for the approval of this amendment can be found in the report on
voting indicated in the above table.
___________
CHAPTER 2: IEC 60821 BUS DATA TRANSFER BUS
Page 67
2.2.4.5 WRITE*
Replace the first sentence of this subclause by the following:
WRITE* is a level significant signal line that is strobed by the falling edge of the first data
strobe (DSA*) and is valid as long as any data strobe (DSA* or DSB*) is low.
Page 89
2.3.6 Basic data transfer capabilities
Replace Rule 2.65 by the following:
D08(O) SLAVES MUST NOT respond by driving DTACK* low during cycles that request access
to byte locations BYTE(0), BYTE(2), BYTE(1-2), BYTE(2-3), BYTE(0-2), BYTE(1-3), or
BYTE(0-3).
Insert, at the end of Suggestion 2.8, the following text:
4) When a D08(O) SLAVE is requested to do a BYTE(0) or BYTE(2) transfer.
Page 93
Table 2-10 – Mnemonics that specify basic data transfer capabilities
Replace in the third column the words "can accept" and "can monitor" by "must accept" and
"must monitor".
60821 Amend. 1 © IEC:1999(E) – 3 –
2.3.7 Block transfer capabilities
Add, on page 95, at the end of Rule 2.12, the words "in the address space."
Replace, on page 97, at the end of the first sentence of Observation 2.87, "D08-D15" by
"D00-D15".
Page 99
Table 2-11 – Mnemonic that specifies block transfer capabilities
Replace, in the third column, the words "Can accept" and "Can monitor" by "Must accept" and
"Must monitor".
Page 101
Table 2-12 – Mnemonic that specifies read-modify-write capabilities
Replace, in the third column, the words "Can accept" and "Can monitor" by "Must accept" and
"Must monitor".
Page 103
2.3.9 Unaligned transfer capabilities
Page 105
Table 2-13 – Transferring 32 bits of data using multiple byte transfer cycles
Replace, in row B, line 3, and line 6, "Group 1, BYTE(0)" by "GROUP 2, BYTE(0)".
Replace, in row D, line 6, "D00-D23" by "D00-D07".
Page 107
Table 2-14 – Transferring 16 bits of data using multiple byte transfer cycles
Replace, in row F, line 1, "D08-D15" by "D00-D07".
Replace, in row F, line 2, "D16-D23" by "D08-D15".
RULE 2.6
Replace, at the beginning of the sentence, "D08(0)" by "D08(O)"
Replace the text before table 2-15 and after RULE 2.6 by:
Table 2-15 lists how the unaligned transfer (UAT) mnemonic is used to describe MASTERS
and SLAVES.
– 4 – 60821 Amend. 1 © IEC:1999(E)
Table 2-15 – Mnemonic that specifies unaligned transfer capability
Replace table 2-15 by the following revised table:
The following mnemonic When applied to a Means that it
UAT D32 MASTER Can generate the following cycles:
D32 SLAVE MUST accept the following cycles:
Quad byte read cycles:
BYTE(0-3) READ
Quad byte write cycle:
BYTE (0-3) WRITE
Triple byte read cycles:
BYTE(0-3) READ
BYTE(1-3) READ
Triple byte write cycles:
BYTE(0-2) WRITE
BYTE(1-3) WRITE
Double byte read cycles:
BYTE(1-2) READ
Double byte write cycles:
BYTE(1-2) WRITE
Page 109
Table 2-16 – Mnemonic that specifies ADDRESS-ONLY capability
Replace, in the first column, "AD0" by "ADO".
Page 133
Table 2-17 – Timing diagrams that define MASTER, SLAVE and LOCATION MONITOR
operation
Replace, in the first row of the first column, "AD0" by "ADO".
Page 135
Table 2-18 – Definitions of mnemonics used in tables 2-19, 2-20 and 2-21
Replace, in the seventh row, "DRIVEN BY SLAVE" by "DRIVEN BY SLAVE?".
Page 139
Table 2-20 – Use of DS1*, DS0*, AO1 and LWORD* during the various cycles
Replace, in the first row, "AD0" by "ADO".
60821 Amend. 1 © IEC:1999(E) – 5 –
Page 141
Table 2-21 – Use of the data lines to transfer data
Replace, in the first row, "AD0" by "ADO".
CHAPTER 3: IEC 60821 BUS DATA TRANSFER BUS
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