IEC 62615:2010

IEC 62615 ®
Edition 1.0 2010-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Electrostatic discharge sensitivity testing – Transmission line pulse (TLP) –
Component level
Essai de sensibilité aux décharges électrostatiques – Impulsion de ligne de
transmission (TLP) – Niveau composant

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IEC 62615 ®
Edition 1.0 2010-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Electrostatic discharge sensitivity testing – Transmission line pulse (TLP) –
Component level
Essai de sensibilité aux décharges électrostatiques – Impulsion de ligne de
transmission (TLP) – Niveau composant

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
R
CODE PRIX
ICS 17.220.99; 31.080 ISBN 978-2-88910-976-0
– 2 – 62615 © IEC:2010
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
ELECTROSTATIC DISCHARGE SENSITIVITY TESTING –
TRANSMISSION LINE PULSE (TLP) –
COMPONENT LEVEL
FOREWORD
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International Standard IEC 62615 has been prepared by IEC technical committee 47:
Semiconductor devices.
This first edition is based on an ANSI/ESDA document ANSI/ESD STM5.5.1-2008.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2046/FDIS 47/2056/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

62615 © IEC:2010 – 3 –
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 4 – 62615 © IEC:2010
INTRODUCTION
Interest in TLP testing is growing rapidly in the testing of electronic components in the
semiconductor industry. TLP testing techniques are being used for semiconductor process
development, device and circuit design. This technique or practice is being utilized on
products in both wafer level and packaged environments. TLP testing is used as an
electrostatic discharge (ESD) characterization tool to obtain voltage-current pulse
characterization parameters, failure levels, and ESD metrics. The TLP technique is being
used today as a standard measurement for ESD devices. The TLP system to the ESD
engineer is becoming a tool as critical as the ‘parameter analyzer’ is to the semiconductor
engineer.
The majority of TLP systems are designed by engineers in a laboratory environment. A
number of commercial TLP systems have been marketed in the industry. Hence it is clear a
TLP specification was needed for the TLP vendors, semiconductor industry and product
customers to be able to make valid data comparisons. With the usage of TLP data for ESD
characterization, technology benchmarking, and product quality evaluation, there is a growing
need to have standard methodologies, failure criteria, and means of reporting to allow
dialogue between semiconductor suppliers, vendors, and product customers.
This document defines the standard test method used today in the semiconductor industry for
TLP testing method and techniques in both industrial and academic institutions (this
document is intended to be used by electrical technicians, electrical engineers, semiconductor
process and device engineers, ESD reliability and quality engineers, and circuit designers).
The context of this document is the application of TLP techniques for the electrical
characterization of semiconductor components. These semiconductor components can be
single devices, a plurality of devices, integrated circuits, or semiconductor chips. This
methodology is relevant to both active and passive elements. This test method is applicable to
diodes, MOSFET devices, bipolar transistors, resistors, capacitors, inductors, contacts, vias,
wire interconnects, and related components.

62615 © IEC:2010 – 5 –
ELECTROSTATIC DISCHARGE SENSITIVITY TESTING –
TRANSMISSION LINE PULSE (TLP) –
COMPONENT LEVEL
1 Scope and object
This International Standard defines a method for pulse testing to evaluate the voltage current
response of the component under test and to consider protection design parameters for
electro-static discharge (ESD) human body model (HBM). This technique is known as
transmission line pulse (TLP) testing.
This document establishes a methodology for both testing and reporting information
associated with transmission line pulse (TLP) testing. The scope and focus of this document
pertains to TLP testing techniques of semiconductor components.
This document should not become alternative method of HBM test standard such as
IEC 60749-26. The purpose of the document is to establish guidelines of TLP methods that
allow the extraction of HBM ESD parameters on semiconductor devices. This document
provides the standard measurement and procedure for the correct extraction of HBM ESD
parameters by using TLP.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60749-26: Semiconductor devices – Mechanical and climatic test methods – Part 26:
Electrostatic discharge (ESD) sensitivity testing – Human body model (HBM)
IEC 60749-27, Semiconductor devices – Mechanical and climatic test methods – Part 27:
Electrostatic discharge (ESD) sensitivity testing – Machine model (MM)
IEC 60749-28, Semiconductor devices – Mechanical and climatic test methods – Part 28:
Electrostatic discharge (ESD) sensitivity testing – Direct contact charged device model (DC-
CDM)
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
current source method
TLP methodology (sometimes referred to as constant current method) that utilizes a 500 Ω
resistor in series with the DUT and measures the voltage and current at the DUT
3.2
destructive damage
damage where the operating electrical characteristics or parameters are altered and do not
recover to the initial conditions prior to stress
___________
Under consideration.
– 6 – 62615 © IEC:2010
3.3
safe operation area
(SOA)
current and voltage regime where a device is in normal operation without degradation
3.4
second breakdown
condition where a negative resistance state occurs in a device due to thermal processes
NOTE This is designated as the voltage trigger point V and current I . and is typically observed after electrical
t2 t2
breakdown (e.g., V , I )
t1 t1
3.5
thermal instability
condition whereby a device is in a negative resistance regime due to thermal processes
3.6
time domain reflectometer method
(TDR)
TLP methodology that uses an oscilloscope to measure both the incident and the reflected
waves from the device under test (DUT)
3.7
time domain transmission method
(TDT)
TLP methodology that uses an oscilloscope to measure the transmitted wave after application
to the device under test (DUT)
3.8
time domain transmission and reflection method
(TDRT)
TLP methodology that incorporates both the transmitted and reflected waves
3.9
transmission line pulse
(TLP)
a rectangular current pulse formed by discharging a charged transmission line cable.
NOTE In this document, TLP refers to any rectangular pulse formed from any pulse source
3.10
transmission line pulse test system
a test system that applies a rectangular pulse to a device under test and allows measurement
of device electrical characteristics during a pulsed state
NOTE The system typically measures current and voltage across the device, as well as leakage current after TLP
pulse application
4 Test apparatus
4.1 General
Transmission line pulse (TLP) systems vary in their use of equipment, configurations, and
methodology to extract the current and voltage characteristics of a device. TLP design and
system configuration is contained in Annex A.
All equipment within the test system shall be able to withstand the maximum current for the
largest pulse width applied. Additionally, all equipment shall withstand the maximum voltage
from the initial charge voltage (including the reflected voltage) observed in the test system.
Current and voltage probes shall not saturate and/or fail during TLP testing.

62615 © IEC:2010 – 7 –
4.2 Oscilloscope
Oscilloscope requirements:
a) minimum single shot bandwidth of at least 500 MHz
4.3 Voltage probe
Voltage probe requirements:
a) a minimum bandwidth of 200 MHz.
b) shall be able to withstand a maximum voltage of twice the open-circuit maximum voltage
(e.g. twice the pre-charge voltage) without electrical damage
4.4 Current probe
Current probe requirements:
a) a minimum bandwidth of 1 GHz.
b) shall not saturate under TLP test maximum current and/or maximum pulse width
4.5 Transmission line
Transmission line requirements:
a) shall be able to withstand the maximum current for the largest TLP test pulse width
without electrical damage.
b) shall be able to withstand the maximum TLP test voltage observed (combined initial
charge voltage and reflected voltage) without electrical damage.
4.6 High voltage power supply
High voltage power supply requirements:
a) shall be able to source TLP test voltage levels required to evaluate the DUT.
b) shall be able to withstand the maximum TLP test voltage observed (combined initial
charge voltage and reflected voltage) without electrical damage.
4.7 High voltage switch
High voltage switch requirements:
a) shall be able to withstand maximum current for the largest TLP test pulse width without
electrical damage.
b) shall be able to withstand the maximum TLP test voltage observed (combined initial
charge voltage and reflected voltage) without electrical damage.
4.8 Attenuator
Attenuator requirements:
a) shall be able to withstand maximum current for the largest TLP test pulse width without
electrical damage.
b) shall be able to withstand the maximum TLP test voltage observed (combined initial
charge voltage and reflected voltage) without electrical damage.
4.9 Rise time filter
Rise time filter requirements:

– 8 – 62615 © IEC:2010
a) shall be able to withstand maximum current for the largest TLP test pulse width without
electrical damage.
b) shall be able to withstand the maximum TLP test voltage observed (combined initial
charge voltage and reflected voltage) without electrical damage.
5 TLP waveform parameters
5.1 Pulse characteristics
This subclause describes pulse characteristics for specified load conditions. Table 1
summarizes these pulse characteristics.
Table 1 – TLP current and voltage pulse parameters
TLP Pulse Parameters
Typical Value Load Condition
(Voltage and Current Conditions)
Current pulse width 100 ns Short
Voltage rise time 0,2 to 10 ns Open
Current rise time 0,2 to 10 ns Short
Fall time Greater or equal to rise time N/A
Maximum peak voltage overshoot 20 % of plateau Open
Maximum voltage ringing duration 25 % of pulse width Open
Maximum peak current overshoot 20 % of plateau Short
Maximum current ringing duration 25 % of pulse width Short
10 % to 95 % of
Measurement time window N/A
pulse width
5.2 Pulse plateau
The pulse plateau is the pulse time-averaged maximum value.
5.3 Pulse width
The pulse width is defined as the full width half maximum or FWHM. The most commonly
used TLP pulse width is 100 ns (see Figure 1).

62615 © IEC:2010 – 9 –
Plateau
90 %
Pulse width
(FWHM)
50 %
10 %
Rise time Fall time
(Tr) (Tf)
Time
IEC  1177/10
Figure 1 – TLP waveform parameter illustration for pulse width rise time and fall time
(parameters apply to both voltage and current TLP waveforms)
5.4 Rise time
Rise time is defined as the time it takes the voltage or current to rise from 10 % to 90 % of the
pulse plateau (see Figure 1). TLP systems have a typical rise time of less than 10 ns.
5.5 Fall time
Fall time is defined as the time it takes the voltage or current to decrease from 90 % to 10 %
of the pulse plateau (see Figure 1). The fall time shall be equal to or greater than the rise time.
When a pulse source other than a charged transmission line is used for pulse generation, it is
recommended that the fall time be equal to the rise time.
5.6 Maximum peak current overshoot
The maximum peak current overshoot is defined as the magnitude of the overshoot peak
current (into a short circuit) to the current plateau of the measured pulse (see Figure 2). It
shall be less than 20 % of the plateau current.

25 1 000
Voltage
20 800
Current
Measurement
window
10 400
–200
–5
–50 0 50 100 150 200
Time  (ns)
IEC  1178/10
Figure 2 – Illustration of maximum peak current overshoot
Voltage  (V)
Current
V or I
overshoot
Current  (mA)
– 10 – 62615 © IEC:2010
5.7 Maximum current ringing duration
The maximum current ringing duration is defined as the duration of time between the
beginning of the current pulse and the time that the ringing reaches less than 5 % of the
plateau current magnitude. The maximum ringing duration shall be less than 25 % of the
pulse width. For example, a 100 ns TLP pulse shall have a maximum ringing duration of less
than 25 ns.
5.8 Maximum peak voltage overshoot
The maximum peak voltage overshoot is defined as the magnitude of the overshoot peak
voltage to the voltage plateau of the measured pulse (see Figure 3). It shall be less than 20 %
of the plateau voltage magnitude.

10 250
Voltage
Voltage ringing duration
Current
6 150
4 100
2 50
0 0
–2 –50
–50 0 50 100 150 200
Time  (ns)
IEC  1179/10
Figure 3 – Illustration of maximum peak voltage overshoot
5.9 Maximum voltage ringing duration
The maximum voltage ringing duration is defined as the length of time between the first
overshoot beyond the plateau voltage to the time when it settles to within 5 % of the plateau
voltage. The maximum ringing duration shall be less than 25 % of the pulse width. For
example, a 100 ns TLP pulse shall have maximum ringing duration of less than 25 ns.
5.10 Measurement window
The measurement window is the range of time within the pulse width where the voltage and
current of the device under test (DUT) are measured. The length of the measurement window
shall be more than 10 % of the pulse width to achieve accuracy by averaging many data
points.
6 Test requirements and procedures
6.1 Error correction
Adjustments of both current and voltage measurements are important to remove unavoidable
non-ideal system characteristics such as system resistance, contact resistances, and shunt
resistance. Periodic verification using simple components with known properties insures
accurate measurements.
6.2 Tester error correction methodology
6.2.1 General methodology
Perform the error correction methodology, including the open and short circuit measurements,
at least once per shift or when the equipment is modified or changed. Longer periods between
error correction steps may be used if no changes in the error correction factors are observed
Voltage  (V)
Voltage
overshoot
Current  (mA)
62615 © IEC:2010 – 11 –
for several consecutive checks. Create a separate set of adjustment values for each test
pulse rise time, or configuration of cables and probes used to collect device data. The
adjustments derived from the short circuit and open circuit measurements may be applied to
the data within the operating system software, during post processing using spreadsheet or
other data analysis software or can be done manually. To insure accurate results, all
measurements shall be performed on properly calibrated measurement instruments.
6.2.2 Error correction short circuit methodology
Measurements through a short circuit allow for correction of system and contact resistance.
Connect an electrical short circuit to the end of the device testing connections or needles at
the DUT. In the case of wafer probes, placing probe needles on a low resistance clean metal
can be considered as a good electrical short circuit. The short circuit shall be made of the
same type of material to be used during device measurements or verification, and shall be
verified by standard low resistance measurement techniques with accuracy to 1 mΩ.
Perform a TLP test (see 6.4 for test procedure) with at least 5 points set to the maximum
current. If the slope of a line through the test points is not 0 Ω, then the value of the slope of
the line in V/I (Ω) represents the internal adjustment value and shall be used to correct the
DUT I-V test data.
Record the measured V-/I-values for reference and use until the next short circuit error
correction.
For the greatest accuracy, use an I-V plot range of ±1 V with the current range set to highest
value used in the TLP system.
6.2.3 Error correction open circuit methodology
Measurements through an open circuit allow the correction of shunt resistance contributions.
Provide an open circuit at the end of the device testing connections for a socket tester. For
wafer probing, disconnecting the probe needles from the short circuit will provide an optimum
open circuit.
Perform a TLP test (see 6.4 for test procedure) with at least 5 points set to the maximum
voltage. If the slope of a line through the test points is not infinite, then the value of the slope
of the line represents the internal adjustment value and shall be used to correct the DUT I-V
test data.
Record the measured V-/I-values for reference and use until the next open circuit error
correction.
For the greatest accuracy, use an I-V plot range of ±10 mA with the voltage range set to the
highest value used for device testing.
NOTE Typically the current probe losses inject 1 Ω into the current carrying wire, thus the total V/I correction will
be greater than 1 Ω. TLP test leads running to a wafer probe station can add an additional 1 Ω to the V/I error
correction. Therefore, the V/I error correction can be approximately 1 Ω for socket testing and 1 Ω to 2 Ω for wafer
testing. Unless a voltage probe with a lower resistance provides greater shunt losses, the I/V error correction will
vary between 10 kΩ and 100 kΩ.
6.3 Tester verification methodology
Verification of TLP test system accuracy shall be performed on a regular basis and prior to
system use to minimize error in the measurements. The verification procedure and
methodology is dependent on the TLP method being utilized. Verification is performed using

– 12 – 62615 © IEC:2010
both a Zener diode and a resistor. The Zener diode is used to verify the system voltage error.
Once the voltage error is known, a resistor is used to verify the system current error.
a) Choose a Zener diode. Measure the dc reverse bias breakdown voltage.
b) Perform a reverse bias TLP test (see 6.4) on the Zener diode to a voltage above the Zener
diode reverse bias breakdown voltage. Compare the TLP and dc breakdown voltage.
c) Choose a resistor whose resistance value is comparable to the DUT resistance (typical
DUT resistances are between 1 and 50 Ω. Measure the resistance to within 10 mΩ. A four-
wire (Kelvin) technique removes contact resistance from the measurement. For a socket
system, insert the resistor into the test socket. For a wafer probing system, place the
probe needles on the electrical terminals of the resistor element.
d) Perform a TLP I-V measurement (see 6.4 for test procedure). The number of voltage steps
shall be chosen to minimize measurement error relative to the average resistance straight-
line slope. Use the V/I and I/V error correction results to correct for system, contact, and
shunt resistance.
e) After the test completion, calculate the V/I ratio (e.g. slope). Compare the calculated
resistance and measured dc resistance. The difference is a measure of the amount of
error in the TLP measured resistance. Given that the measured voltage has been found to
be accurate (e.g., based on the Zener diode measurement), a determination of current
measurement accuracy can be obtained by comparing the measured and calculated
current. This is based on the measured voltage divided by the known resistance value.
f) Perform the resistance measurement for each rise time and cable configuration to be used.
The accuracy shall be approximately the same for each measurement.
6.4 TLP test procedure
The TLP test procedure uses a series of increasing pulse amplitudes to characterize or test a
device, discrete circuit, or test structure. This test procedure is described below and
illustrated in the test flow diagram of Figure 4.
a) Select appropriate test level, including pulse width, amplitude and polarity.
b) Select step size increments.
c) To insure repeatability and integrity of measurements, a minimum of three devices shall
be tested.
d) A minimum time between successive step pulses of 0,3 seconds shall be used to allow for
DUT cooling during TLP testing.
e) Define failure criteria and perform initial (reference) leakage current measurement on the
DUT (see Clause 7).
f) Apply a stress pulse of a fixed width (in accordance with Item a) above ) to the DUT; TLP
testing shall begin at the lowest desired level of interest and increased using the defined
step stress.
g) Measure and record the stress pulse voltage and current; this will represent one I-V point
on the DUT I-V curve.
h) Perform a post-stress leakage measurement on the DUT. If the device fails (as defined in
Clause 7), the test is complete.
NOTE A simple semiconductor parametric analyzer can be used for measuring leakage of discrete test structures,
but it may not be sufficient for measuring leakages of all circuit types and complex structures. Evaluation may
require pre-conditioning or powered states.
i) If the device passes (as defined in the failure criteria of Clause 7), increase the pulse
amplitude to the next desired level and repeat steps 6.4 f) to h) until the maximum desired
pulse amplitude is reached. This will generate a series of pulses as shown in Figure 5. To
minimize measurement error, it is necessary to set the desired step size to magnitudes
consistent with the test structure response.
NOTE Depending on the DUT configuration and requirements, additional bias can be applied to the DUT terminals
during application of the TLP pulse. External transients can lead to accidental triggering of the DUT when ground
loops exist. Ground loops should be avoided

62615 © IEC:2010 – 13 –
Procedure
Calibration and
verification
Initial leakage/
parametric test
Apply stress pulse
to the DUT
Measure and
record pulse
voltage and
current
Perform post-
Fail
stress leakage Stop testing
measurement
Pass
Increase Max pulse
No
stress pulse amplitude
amplitude reached?
Yes
Stop
IEC  1180/10
Figure 4 – Flow diagram for the TLP component test procedure

Time
IEC  1181/10
Figure 5 – Illustration of TLP pulse sequence
Voltage
– 14 – 62615 © IEC:2010
7 Failure criteria
7.1 General information on failure criteria
Failure criteria are application dependent and are typically associated with an increase in
leakage current. Any device or circuit that fails to meet its device or product specification shall
be regarded as a failure. (see IEC 60749-26, IEC 60749-27 and future IEC 60749-28). All
relevant information shall be recorded.
NOTE 1 Negative resistance region transitions in the TLP I-V plot accompanied by large increases in the leakage
condition (e.g., 10X to 100X increase) are often associated with damage to the DUT. This transition may be defined
as the failure voltage and failure current. Leakage increases observed during successive TLP steps that lead to
DUT characteristic or specification shifts can be regarded as the condition of DUT failure. Leakage increases
observed during TLP testing that do not lead to DUT specification failure do not have to be regarded as DUT failure.
In the case that there is no DUT specification or failure criteria, DUT failure can be defined as a 10X increase in
leakage current.
NOTE 2 Destructive damage is defined as the level at which DUT operating electrical characteristics or parameters
are altered and do not restore to initial pre-stress conditions. Destructive damage may be visible following TLP
stress. Negative resistance regions of a TLP I-V characteristic may not be indicative of destructive damage. For
example, second breakdown is where a negative resistance state occurs in a device due to thermal processes and
may indicate the onset of destructive breakdown. The I-V point at which this occurs is known as the second
breakdown voltage and current (V , I ), observed after electrical breakdown (V , I ).
t2 t2 t1 t1
7.2 Leakage current measurement
The leakage current of a DUT shall be measured prior to and immediately after application of
any TLP pulse.
7.3 Leakage test voltage
The leakage test shall be applied in a voltage range that does not damage the device or
induce DUT leakage. The safe operating area of the DUT is typically less than or equal to
1,1X the technology native voltage or the maximum voltage level in the technology or product
DUT specification.
7.4 Documentation
In the reporting documentation, the following information shall be recorded: I-V characteristics,
pulse width, rise time, measurement window, failure voltage, failure current, maximum current,
leakage test voltage, leakage current characteristic, and any failure criteria information that
may apply.
62615 © IEC:2010 – 15 –
Annex A
(informative)
TLP design guidelines
A.1 Transmission line cable-based system
An important distinction in the transmission line pulse (TLP) test systems is the pulse source.
The main components of a TLP system that utilizes a transmission line cable source include:
a) oscilloscope (see Clause 4) fixed impedance charged transmission line;
b) high voltage switch;
c) high voltage power supply;
d) isolation of the power supply from the charging line;
e) method to trigger the switch;
f) attenuator (see Clause 4);
g) voltage and/or current probes (see Clause 4);
h) method of connecting transmission line to the device under test (DUT);
i) rise time filters (see Clause 4).
A.2 Commercial pulse source-based system
The main components of a TLP system that utilizes a commercial high-current pulse source
include:
a) oscilloscope (see Clause 4);
b) commercial high-current pulse source;
c) method to trigger the pulse;
d) voltage and/or current probes (see Clause 4);
e) method of connecting transmission line to the DUT.
A.3 TLP methods
A.3.1 TLP system classification
Different design methodologies exist in TLP systems. For this subclause, the methods will be
defined and the distinction between them highlighted. There are four fundamental TLP
methodologies:
• current source;
• time domain transmission (TDT);
• time domain reflection (TDR); and
• time domain reflection and transmission (TDRT).
These methods are summarized in Table A.1.

– 16 – 62615 © IEC:2010
Table A.1 – TLP methodologies and parameters
Method of transmission line pulsing (TLP)
Typical features
Current Source TDR TDT TDRT
Impedance (Ω) 500 50 50 100
Current (A) 5 10 10 10
Pulse width, FWHM 50 ns to 1 μs greater than 1 ns less than 2 ns less than 2 ns
less than 3 ns, less less than 200 ps, less less than 200 ps, less less than 200 ps, less
Rise Time, Tr
than FWHM than FWHM than FWHM than FWHM
Reflections
Slight Yes Yes Yes
Reflection polarity N/A Bipolar Bipolar Unipolar
Attenuation
No Yes Yes Yes
recommendation
Two-channel
Yes No No Yes
oscilloscope
Yes
Reference pulse
No Yes Yes
required
(see A.3.3)
A.3.2 Current source TLP method
The current source TLP method is shown in Figure A.1. In this method, there is a 500 Ω
impedance in series with the DUT and a termination. A two-channel oscilloscope is used with
a current probe (to measure current through the DUT) and voltage probe (in parallel with the
DUT to measure DUT voltage). The current is typically limited to 5 A. Only minor reflections
are observed and no reference pulse is required.

TL Current
probe
500 Ω
56 Ω
R
HV
TL1
DUT
10 MΩ
Z = 50 Ω
Termination
V
HV
Z
DUT
V  I
DUT(t) DUT(t)
IEC  1182/10
Figure A.1 – Current source TLP method
A.3.3 Time domain reflectometer (TDR) TLP method
Figure A.2 shows the time domain reflectometer (TDR) TLP method with attenuator for
reflected stress pulses. This method is a 50 Ω impedance system. Multiple reflection pulses
typically occur and shall be attenuated or reduced (by placing an attenuator in series with the
DUT). The current is typically limited to 10 A. A single-channel oscilloscope is used with a
voltage probe (in parallel with the DUT) to measure device voltage. A reference pulse is
required if the reflected pulse overlaps the initial TLP pulse. Figure A.3 illustrates a TDR
system using a balun (transformer that isolates the input from the output) and wafer probe.

62615 © IEC:2010 – 17 –
Recommended attenuator
Connection Delay
R –dB
HV
TL1
DUT
10 MΩ
Z = 50 Ω
V
Z
DUT
V Incident and reflected
V = V + V (t)
DUT incident reflected
pulse without overlap
V
DUT
Z =
DUT
V − V       I
incident reflected
DUT
I =
DUT
Z
IEC  1183/10
Figure A.2 – Time domain reflectometer (TDR) TLP

+HV DC
1 MΩ
Coaxial
20 dB attenuator
DUT
50 Ω coaxial 50 Ω coaxial Balun

V I
wafer
SPDT
Sensors
coaxial
Charge line Cable to balun
switch
or
Balanced
DUT
probe needles
IEC  1184/10
Figure A.3 – Time domain reflectometer (TDR) TLP (with balun and wafer probe)
A.3.4 Time domain transmission (TDT) TLP method
Figure A.4 shows the time domain transmission (TDT) TLP method without attenuation. This
method is a 50 Ω impedance system. Multiple reflections typically occur; however no series
attenuator is required. The current is typically limited to 10 A. A single-channel oscilloscope is
used with a voltage probe (in parallel with the DUT) to measure device voltage. A reference
pulse is required. The variable “a” is the attenuation factor (V = a V).
DUT
– 18 – 62615 © IEC:2010
Attenuator or high impedance voltage probe

R TL1
–dB
HV
DUT
10 MΩ Z = 50 Ω
V
HV
V
V
DUT DUT
V = a × V
Z = Z × I =
DUT
DUT 0 DUT
V – V
Z
chg DUT
DUT
IEC  1185/10
Figure A.4 – Time domain transmission (TDT) TLP
A.3.5 Time domain reflection and transmission (TDRT) TLP method
Figure A.5 shows the time domain reflection and transmission (TDRT) TLP method. This
method is a 100 Ω impedance system. Multiple reflections typically occur. The current is
typically limited to 10 A. A two-channel oscilloscope is used with a termination and voltage
probe (in parallel with the DUT to measure device voltage). A reference pulse is required. The
variable “a” is the attenuation factor.

L L
delay = termination
Connection Delay Termination
Z
DUT
DUT
R TL1
HV
10 MΩ Z = 50 Ω
V
I =
V DUT
HV
50 Ω
V = a × 2 × V
DUT refl
I  V
DUT(t) DUT(t)
IEC  1186/10
Figure A.5 – Time domain reflection and transmission
A.4 TLP test system influences
A.4.1 TLP test system influences – general
TLP test systems are influenced by the following:
a) oscilloscope bandwidth;
b) attenuators;
c) element mismatch;
d) probe bandwidth and response;
e) TLP system fixtures;
f) reflections.
62615 © IEC:2010 – 19 –
TLP test influences are discussed through the use of extended discussion in a technical
report and round robin analysis.
A.4.2 Oscilloscope bandwidth
Fundamental TLP I-V plots only require a oscilloscope sampling rate sufficient to capture
enough data points in the measurement window and insure accuracy. A 5 giga-sample per
second, 500 MHz oscilloscope is sufficient for most applications because it provides 100 data
points in a 20 ns measurement window.
A.4.3 Attenuators
In a TDT system, attenuators can be used to reduce signal amplitude to the oscilloscope and
play a role in the matching characteristics of the TLP system by absorbing reflections when
using a non-50 Ω oscilloscope input. For a 50 Ω characteristic impedance transmission line
system, a 50 Ω impedance attenuator absorbs reflections. In a TDR TLP system, attenuators
are used in series with the DUT to avoid damaging the DUT.
A.4.4 Element mismatch
Non-ideal matching of electrical components in a TLP system can introduce reflections and
mismatch loss. Loss from reflections is minimized by matching the impedance at all port
intersections. Matching all components with the characteristic impedance of the transmission
line (e.g., 50 Ω) allows for the transfer of maximum pulse energy between ports. Resistive
matching networks (e.g., 2 element L-match or 3 element T-match) can be added to the TLP
system to improve the matching at terminal-to-terminal boundaries and to minimize reflection
losses.
A.4.5 Probe bandwidth and response
In a current source TLP system, probes are used to capture the DUT voltage and current
signals. Current probes are placed around the signal line between the charged transmission
line (or pulse source) and the DUT. Voltage probes are connected to the positive side of the
DUT. The probes are then connected to the oscilloscope. The bandwidth of the all probes
shall be such that the probe cut off frequency is at least 3X the oscilloscope cut off frequency.
A.4.6 TLP system fixtures
TLP system fixtures shall be well matched to the TLP system impedance, thereby minimizing
reflections from the fixture connections.
A.4.7 Reflections
An issue concerning the correlation between the different TLP methods is the elimination or
attenuation of reflections resulting in additional DUT stress. Only the Current Source TLP and
the TLP-50 Ω TDR systems are properly terminated with 50 Ω. All other configurations
produce reflections at the DUT. Reflections are a function of the matching conditions, pulse
amplitude, and the DUT impedance. The severity of reflections is also a dependent on DUT
failure susceptibility.
___________
– 20 – 62615 © CEI:2010
COMMISSION ÉLECTROTECHNIQUE INTERNATIONALE
____________
ESSAI DE SENSIBILITÉ AUX DÉCHARGES ÉLECTROSTATIQUES –
IMPULSION DE LIGNE DE TRANSMISSION (TLP) –
NIVEAU COMPOSANT
AVANT-PROPOS
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