WG 5 - TC 47/WG 5

IEC 63068-4:2022(E) provides a procedure for identifying and evaluating defects in as-grown 4H-SiC (Silicon Carbide) homoepitaxial wafer by systematically combining two test methods of optical inspection and photoluminescence (PL). Additionally, this document exemplifies optical inspection and PL images to enable the detection and categorization of defects in SiC homoepitaxial wafers.

IEC 63275-2:2022 gives the test method and a procedure using this method to evaluate the on-state voltage change, on-state resistance change and reverse drain voltage change of silicon carbide (SiC) power MOSFET devices due to body diode operation. This test is not generally requested for Si power transistors.

IEC 63275-1:2022 gives a test method to evaluate gate threshold voltage shift of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) using room temperature readout after applying continuous positive gate-source voltage stress at elevated temperature. The proposed method accepts a certain amount of recovery by allowing large delay times between stress and measurement (up to 10 h).

IEC 63284:2022 covers the protocol of performing a stress procedure and a corresponding test method to evaluate the reliability of gallium nitride (GaN) power transistors by inductive load switching, specifically hard-switching stress

IEC 63373:2022 In general, dynamic ON-resistance testing is a measure of charge trapping phenomena in GaN power transistors. IEC 63373:2022 provides guidelines for testing dynamic ON-resistance of GaN lateral power transistor solutions. The test methods can be applied to the following:
a) GaN enhancement and depletion-mode discrete power devices;
b) GaN integrated power solutions;
c) the above in wafer and package levels.
The prescribed test methods can be used for device characterization, production testing, reliability evaluations and application assessments of GaN power conversion devices. This document is not intended to cover the underlying mechanisms of dynamic ON-resistance and its symbolic representation for product specifications.

IEC 63229:2021(E) gives guidelines for the definition and classification of defects in GaN epitaxial film grown on SiC substrate. They are identified and described on the basis of examples, mainly by schematic illustrations, optical microscope images, and transmission electron microscope images for these defects. This document covers only defects in as-grown GaN epitaxial film on SiC substrate and does not include defects caused by subsequent processes.

IEC 62373-1:2020 provides the measurement procedure for a fast BTI (bias temperature instability) test of silicon based metal-oxide semiconductor field-effect transistors (MOSFETs).
This document also defines the terms pertaining to the conventional BTI test method.

IEC 63068-3:2020 provides definitions and guidance in use of photoluminescence for detecting as-grown defects in commercially available 4H-SiC (Silicon Carbide) epitaxial wafers. Additionally, this document exemplifies photoluminescence images and emission spectra to enable the detection and categorization of the defects in SiC homoepitaxial wafers.

IEC 63068-2:2019(E) provides definitions and guidance in use of optical inspection for detecting as-grown defects in commercially available 4H-SiC (Silicon Carbide) epitaxial wafers. Additionally, this document exemplifies optical images to enable the detection and categorization of the defects for SiC homoepitaxial wafers. This document deals with a non-destructive test method for the defects so that destructive methods such as preferential etching are out of scope in this document.

IEC 63068-1:2019(E) gives a classification of defects in as-grown 4H-SiC (Silicon Carbide) epitaxial layers. The defects are classified on the basis of their crystallographic structures and recognized by non-destructive detection methods including bright-field OM (optical microscopy), PL (photoluminescence), and XRT (X-ray topography) images.

IEC TR 63133:2017(E) specifies a design technique of performance estimation storage element, which can monitor semiconductor ageing and characterize ageing level. The estimated ageing level can be used to improve the reliability of system.

IEC 62880-1:2017(E) describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method can be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time.

IEC 62374-1:2010 describes a test method, test structure and lifetime estimation method of the time-dependent dielectric breakdown (TDDB) test for inter-metal layers applied in semiconductor devices.

IEC 62415:2010 describes a method for conventional constant current electromigration testing of metal lines, via string and contacts.

IEC 62416:2010 describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.

IEC 62417:2010 provides a wafer level test procedure to determine the amount of positive mobile charge in oxide layers in metal-oxide semiconductor field effect transistors. It is applicable to both active and parasitic field effect transistors. The mobile charge can cause degradation of microelectronic devices, e.g. by shifting the threshold voltage of MOSFETs or by inversion of the base in bipolar transistors.

IEC 62418:2010 describes a method of metallization stress void test and associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.

Provides a test method of Time Dependent Dielectric Breakdown (TDDB) for gate dielectric films on semiconductor devices and a product lifetime estimation method of TDDB failure

Provides a test procedure for a bias-temperature (BT) stability test of metal-oxide semiconductor, field-effect transistors (MOSFET)