IEC 62880-1:2017

IEC 62880-1 ®
Edition 1.0 2017-08
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Stress migration test standard –
Part 1: Copper stress migration test standard
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC
copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or
your local IEC member National Committee for further information.

IEC Central Office Tel.: +41 22 919 02 11
3, rue de Varembé Fax: +41 22 919 03 00
CH-1211 Geneva 20 info@iec.ch
Switzerland www.iec.ch
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.

IEC Catalogue - webstore.iec.ch/catalogue Electropedia - www.electropedia.org
The stand-alone application for consulting the entire The world's leading online dictionary of electronic and
bibliographical information on IEC International Standards, electrical terms containing 20 000 terms and definitions in
Technical Specifications, Technical Reports and other English and French, with equivalent terms in 16 additional
documents. Available for PC, Mac OS, Android Tablets and languages. Also known as the International Electrotechnical
iPad. Vocabulary (IEV) online.

IEC publications search - www.iec.ch/searchpub IEC Glossary - std.iec.ch/glossary
The advanced search enables to find IEC publications by a 65 000 electrotechnical terminology entries in English and
variety of criteria (reference number, text, technical French extracted from the Terms and Definitions clause of
committee,…). It also gives information on projects, replaced IEC publications issued since 2002. Some entries have been
and withdrawn publications. collected from earlier publications of IEC TC 37, 77, 86 and

CISPR.
IEC Just Published - webstore.iec.ch/justpublished

Stay up to date on all new IEC publications. Just Published IEC Customer Service Centre - webstore.iec.ch/csc
details all new publications released. Available online and If you wish to give us your feedback on this publication or
also once a month by email. need further assistance, please contact the Customer Service
Centre: csc@iec.ch.
IEC 62880-1 ®
Edition 1.0 2017-08
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Stress migration test standard –

Part 1: Copper stress migration test standard

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.01 ISBN 978-2-8322-4732-7

– 2 – IEC 62880-1:2017 © IEC 2017
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Test method . 7
4.1 Test structures . 7
4.2 Test equipment . 11
4.3 Test temperatures . 11
4.4 Test conditions, sample size and measurements. 11
4.5 Failure criteria . 11
4.6 Passing criteria . 11
5 Data to be reported. 12
Annex A (informative) Explanation for stress migration, stress induced voiding –
Temperature, geometry dependence . 13
A.1 Stress-induced voids . 13
A.2 Stress temperature . 13
A.3 Geometry linewidth dependence of SIV risk . 14
A.4 VIA size dependence of SIV risk . 16
A.5 SIV under multiple VIAs . 17
A.6 Metal thickness dependence of SIV risk . 17
A.7 SM lifetime model . 18
A.8 Sensitivity for test structure . 19
Annex B (informative) Example of geometry dependence for nose pattern . 21
B.1 General . 21
B.2 Geometry factor . 21
Bibliography . 23

Figure 1 – SM test structure sketches . 8
Figure 2 – SM test structure sketches – Illustrative sketches of proposed optional SM
test structures . 10
Figure A.1 – Temperature dependent behaviour of SM MTF values of 5 µm VIA chains
in the range of 125 ºC – 275 ºC . 14
Figure A.2 – Power-law relation of MTF vs linewidth . 15
Figure A.3 – Median time-to-fail SM data as a function of VIA sizes . 16
Figure A.4 – Hydrostatic stress gradient at near room temperatures vs VIA size (area) . 16
Figure A.5 – FA images of two VIA case and MTF vs multiple VIA of SM . 17
Figure A.6 – Metal thickness versus resistance increase under SM tests . 18
Figure A.7 – Stress profile of conventional and VIM VIA chains . 19
Figure A.8 – SM data of conventional and VIM VIA chains . 20
Figure B.1 – Representation of real product interconnect . 21
Figure B.2 – Representation of SM nose pattern . 21
Figure B.3 – Failure rate – Body area dependence with nose pattern . 22

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
STRESS MIGRATION TEST STANDARD –

Part 1: Copper stress migration test standard

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62880-1 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47/2407/FDIS 47/2416/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – IEC 62880-1:2017 © IEC 2017
A list of all parts in the IEC 62880 series, published under the general title Semiconductor
devices – Stress migration test standard, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
SEMICONDUCTOR DEVICES –
STRESS MIGRATION TEST STANDARD –

Part 1: Copper stress migration test standard

1 Scope
This part of IEC 62880 describes a constant temperature (isothermal) aging method for
testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility
to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of
production during technology development, and the results are to be used for lifetime
prediction and failure analysis. Under some conditions, the method can be applied to
package-level testing. This method is not intended to check production lots for shipment,
because of the long test time.
Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or
tantalum nitride (TaN) on the bottom and sides of trenches etched into dielectric layers.
Hence, for structures in which a single via contacts a wide line below it, a void under the via
can cause an open circuit at almost the same time as any percentage resistance shift that
would satisfy a failure criterion.
2 Normative references
There are no normative references in this document.
NOTE Related documents are listed in the Bibliography.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
stress migration
SM
crucial failure phenomenon of the semiconductor device interconnects
3.2
stress induced voiding
SIV
voiding generated in the semiconductor device interconnects which is caused by thermal
stress
Note 1 to entry: In copper interconnect, voiding occurs under VIA or inside VIA, and causes resistance increase
or open failure.
Note 2 to entry: See Annex B for mechanism.

– 6 – IEC 62880-1:2017 © IEC 2017
3.3
wide pattern
chain pattern, which VIA connects wide pattern
Note 1 to entry: There are some combinations of connection.
SEE: Figure 1
3.4
nose pattern
chain pattern, narrow pattern connected to a VIA and attached to a wider pattern
Note 1 to entry: THe SIV risk of this VIA is determined by the width of the plate and the distance of the VIA away
from the plate (described in 4.1).
SEE: Figure 1
3.5
nose length
length of a narrow pattern portion of the nose pattern
SEE: Figure 1
3.6
nose width
width of a narrow pattern portion of the nose pattern
SEE: Figure 1
3.7
DRC
Design Rule Compliant
pattern rule that the designer shall follow, e.g. permitted pattern width, VIA location ,etc.
3.8
VIM
VIA-in-the-middle
wide pattern type of VIA chain
Note 1 to entry: See Figure 1 and Annex A.
3.9
co-axial stacked VIA
SM test structure where VIA is stacked in the vertical direction and coaxially
Note 1 to entry: See Figure 2 and 4.1.
3.10
off-center stacked VIA
SM test structure where VIA is aligned in the vertical direction and the center of VIA is shifted
Note 1 to entry: See Figure 2 and 4.1; a zig-zag type and a spiral type are proposed.
3.11
mesh type VIA
SM test structure chain pattern, VIA is connected to narrow pattern and narrow pattern is
connected to the mesh type wide pattern
Note 1 to entry: See Figure 2 and 4.1.

4 Test method
4.1 Test structures
To test the susceptibility to stress voiding of the technology under evaluation, structures that
emphasize each extreme risk of the technology shall be designed, evaluated, and used in the
test procedure.
Typical SM test structures are in the formats of VIA chains and single VIAs. Special
considerations shall be carried out to assure that the appropriate test structures are used.
The following are the structures that shall be used in the evaluation of stress migration
reliability:
– Design rule compliant (DRC) linewidth test structures:
• Around 100-VIA chains, both conventional (VIA-at-end) and the VIA-in-the-middle (VIM)
VIA chains. Bi-polar or plate-above VIA and plate-below VIA types. Modest VIA
numbers of around 100 to a few hundred are recommended to ensure resistance
sensitivity for SIV risk detections.
• VIA chains with larger VIA numbers such as around 1 000 to around 1E5, are used at
the individual company’s discretion in case of needs for VIA scaling.
• Single Kelvin VIA structures, VIM type.
– For test structures, specific dimensions (nose length/width) shall correspond to each
user’s processes and designs. Potential options may range from 10x min to 100x min
width or its equivalence (e.g., slotted plates) VIM VIA chains, for measuring SM margin
and estimated SM lifetime within limited testing time.
Figure 1 shows the sketches of test structure formats of:
a) conventional VIA chains (around 10 μm interconnect length);
b) VIA-in-the-middle (VIM) VIA chains (around 10 μm interconnect length);
c) single Kelvin VIA (L-shaped);
d) SM nose VIA chain structure of plate-below and plate-above VIA chains.
The plate widths of VIA chains, single Kelvin VIA and SM nose VIA chains can be DRC and
wide plate widths.
– 8 – IEC 62880-1:2017 © IEC 2017

IEC
a) conventional VIA chain
IEC
b) VIA-in-the-middle (VIM) VIA chain
Single Kelvin via
IEC
c) Single Kelvin VIA (L-shaped)
Plate width
Narrow line
width
Nose length
10 µ
3,3 µ
IEC
d) SM nose VIA chains
Key
a) usual wide pattern, VIA is located at edge or near the edge of wide pattern;
b) wide pattern but VIA is located near the center of wide pattern;
c) conventional Kelvin VIA;
d) VIA is located at the narrow pattern and narrow pattern is connected to the wide pattern.
Figure 1 – SM test structure sketches

For SM nose VIA cases where a narrow extension connecting to a VIA is attached to a wider
plate, the SIV risk of this VIA is determined by the width of the plate and the distance of the
VIA away from the plate [6] . The application of nose VIA structures for SIV reliability
assessment shall correspond to their allowable design rules and technologies. If nose VIA
designs are permissible, then nose VIA test structures are part of the product-level SIV
evaluation for SM quantification. Technologies that do not allow nose VIA designs would
naturally conduct SIV evaluations without nose VIA test structures. SM in nose VIA cases are
product specifics and it is each individual company’s discretion to handle the specifics based
on the principle of SM mechanism introduced in this standard. Additional optional SM test
structures for the qualification include:
a) stacked co-axial VIA chains;
b) off-center stacked VIA chains;
c) mesh type VIA chains (minimum line widths) with mesh-above and mesh-below the VIA.
The illustrative sketches of those structures are shown in Figure 2. Those SM test structures
are designed to explore the SIV risk under certain extreme and specific product geometry
cases and they are optional choices of each individual company for its SM qualification tests.
____________
Numbers in square brackets refer to the Bibliography.

– 10 – IEC 62880-1:2017 © IEC 2017
Co-axial
IEC
a) co-axial stacked VIA chain
Off-center: Zig-Zag Off-center: Spiral
IEC
b) two formats of off-center stacked VIA chain
Mesh lines
width = space = min
Mesh length
Mesh width
≈
mesh length
IEC
Link (length, width)
c) mesh type VIA chains (minimum line widths)
IEC
d) mesh type VIA chains (minimum line widths)
Key
a) VIA, chains stacked vertically and coaxially;
b) stack VIA ,center of VIA are shifted each other;
c) top view of mesh type VIA chains (minimum line widths);
d) cross section of Figure 2 c).
Figure 2 – SM test structure sketches – Illustrative sketches of
proposed optional SM test structures

4.2 Test equipment
A calibrated thermal chamber shall be required to subject the wafers or packaged test
structures to the specified temperature for the specified time. Additionally, measurement
instruments shall have sufficient resolution for slight resistance change.
4.3 Test temperatures
Based on the temperature dependence described in Clause A.2, wafer level SM stress
temperatures are the following:
a) Selected constant temperatures between 150 ºC – 275 ºC.
b) For each SM tests, minimum three temperatures shall be required, covering temperature
range from low to high, e.g., 150 ºC, 175 ºC & 225 ºC.
4.4 Test conditions, sample size and measurements
Wafer level tests are recommended for constant Cu stress migration reliability tests due to the
following advantages: 1) capable of testing chips throughout the wafer without possible
influence introduced by packaging tests. 2) capable of testing large number of SM test
structures from the same wafer which is not possible for packaging tests.
Sample size of the wafer level SM tests:
a) Minimum 3 wafers (i.e., 1 wafer/lot from 3 lots) for each stress temperature, e.g. 150 ºC,
175 ºC & 225 ºC.
b) Minimum 30-40 dies per wafer, per metal level, to be tested.
Additional test temperatures (at least four temperatures is recommended) and wafers may be
added for quantitative SM modelling verification and lifetime extrapolations if desired by each
individual company.
Test measurement readout: Resistance value changes of each test structures are monitored
on a required schedule. The minimum is readout at 0 h and 1 000 h. It is optional to perform
additional readout within the 1 000 h for better tracking the SM behaviour. For example, 0 h,
250 h, 500 h, 750 h, 1 000 h.
4.5 Failure criteria
The following criteria are failure criteria for general practice in SM reliability evaluations.
Individual company can revise the resistance increase numbers in their special cases if
needed.
a) Resistance increase (ΔR) for VIA chains > 10 %;
b) Resistance increase (ΔR) for single VIA > 100 %.
4.6 Passing criteria
Criterion a) below is the traditional method of “zero fails during a fixed time period”, which will
explore the SIV risk of DRC test structures as well as extrinsic defects during the 1 000 h
tests. This is a must-have passing criterion.
For the purpose of estimating the SM margin and the extrapolation of product SM lifetime, we
introduce criterion b) for the company to follow. The details of the execution of this second
criterion are based on the company’s choice on an accelerated method of SM lifetime model
(see Clause A.7).
a) Zero DRC test structure fails for all testing temperatures within 1000 h.

– 12 – IEC 62880-1:2017 © IEC 2017
b) Zero SM fails for selected wide line VIA chains within a fixed period, e.g., 250 h, 500 h or
shorter, depending on the choices of wide lin
...