IEC 62418:2010

IEC 62418 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Metallization stress void test

Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation
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IEC 62418 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Metallization stress void test

Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
Q
CODE PRIX
ICS 31.080 ISBN 978-2-88910-697-4
– 2 – 62418 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Test equipment.5
3 Test structure .5
3.1 Test structure patterns .5
3.2 Line pattern.5
3.3 Via chain pattern .5
3.3.1 Pattern types .5
3.3.2 Pattern for aluminium (Al) process.5
3.3.3 Pattern for copper (Cu) process.6
4 Stress temperature.6
5 Procedure .6
5.1 Stress void evaluation methods .6
5.2 Resistance measurement method.6
5.3 Inspection method .7
6 Failure criteria .8
6.1 Resistance method.8
6.2 Inspection method .8
7 Data interpretation and lifetime extrapolation (resistance change method).8
8 Items to be specified and reported.9
8.1 Resistance change method .9
8.2 Inspection method .10
Annex A (informative) Stress migration mechanism .11
Annex B (informative) Technology-dependent factors for aluminium .13
Annex C (informative) Technology-dependent factors for copper .14
Annex D (informative) Precautions.15
Bibliography.17

Figure A.1 – Schematic representation of the stress-void formation mechanism in Al.11

Table 1 – Void classification .7

62418 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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International Standard IEC 62418 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2043/FDIS 47/2050/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – 62418 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
62418 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST

1 Scope
This International Standard describes a method of metallization stress void test and
associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.
This standard is applicable for reliability investigation and qualification of semiconductor
process.
2 Test equipment
A calibrated hot chuck or thermal chamber is required to subject the wafers or packaged test
structures to the specified temperature (±5 °C) for the specified time. For resistance
measurements dedicated equipment is needed. For void inspection deprocessing equipment
is required to remove the scratch protection layer. The inspections are performed with a
scanning electron microscope (SEM).
3 Test structure
3.1 Test structure patterns
Test structures shall be used for all metal layers which have to be inspected and several
different types of structure may be used. The following two types of test structures are
applicable for this test standard.
NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structures
with underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour.
3.2 Line pattern
Parallel lines which are patterned at the minimum linewidth allowed by design form an
appropriate test structure. Unless otherwise specified a minimum length of 500 μm and a total
length of 1 cm to 1 000 cm are recommended condition. Single long isolated lines are
recommended because stress voiding is often sensitive to line-to-line separation.
NOTE 1 Narrow lines are susceptible for stress voiding because the stress in the metal is typically higher in
narrower lines than in wider lines.
NOTE 2 The line length should be sufficient to insure that void nucleation sites will exist.
3.3 Via chain pattern
3.3.1 Pattern types
A via chain pattern is applicable as a test structure. For technology investigations a Kelvin-
pattern for four-point measurements may also be used.
3.3.2 Pattern for aluminium (Al) process
Via chains need to consist of a pattern of vias connected by minimum linewidth. The
recommended number of vias is between 1 000 and 100 000. It is recommended to use
isolated and long minimum linewidths.

– 6 – 62418 © IEC:2010
3.3.3 Pattern for copper (Cu) process
For Cu metallization the following structures are applicable:
a) via chains with top and bottom metal segments with minimum allowed width;
b) via chains with either the top or the bottom metal segment at minimum allowed width, and
the other segment at the maximum width allowed for a single via;
c) vias chains with both top and bottom metal segments at the maximum width allowed for a
single via;
d) Kelvin via structures, with various widths for top and bottom metal.
Chains with 1 000 – 100 000 vias are recommended.
4 Stress temperature
To evaluate the impact of stress voiding on chip reliability under use conditions, accelerated
testing is needed to generate voiding. The acceleration factor can be strongly affected by the
factors listed in Annex B and Annex C. Therefore, it is recommended to determine empirically
the temperature range for accelerated testing which will maximize voiding. Recommended
temperature ranges are given in 5.2 and 5.3.
5 Procedure
5.1 Stress void evaluation methods
Two methods are specified for the metallization stress void test: a resistance measurement
method and a visual inspection method.
– The resistance measure method is the default method.
– The inspection method is applicable for use as a verification when no stress voiding is
expected. It cannot be used for lifetime extrapolations. This method is not applicable to Cu
metallization. The inspection method shall not be used in case the visibility of voids is
insufficient (see Note 2.)
NOTE 1 The test method most likely to detect sensitivity to stress voiding and the one most usually conducted is
constant temperature (isothermal) aging, i.e., annealing or baking at temperatures between the passivation
deposition temperature and the intended use temperature of the product.
NOTE 2 This is the case for e.g. metallization with multiple metal levels, where the lower levels are not clearly
visible, masking of voids by other process features.
5.2 Resistance measurement method
This method assumes the void growth and therefore resistance changes can be modelled, to
obtain an acceleration factor for void growth [1, 2] . Unless otherwise specified, the
temperature condition shall be determined within the range of 150 °C to 275 °C. Samples
need to be separated into each temperature condition group and each group to be baked at
the specified temperature. The procedure for resistance measurement is the following.
a) Measure the resistance of the metal line or via chain. Resistance measurements shall be
made at currents that minimize joule heating.
b) Bake the samples. Unless otherwise specified three temperatures are recommended to
determine the parameters for the extrapolation model. When these parameters are known
it is sufficient to test at a single temperature. In some cases, three temperatures may not
be enough if the temperature range is not chosen correctly - there could be an inflection
point in the activation energy versus temperature curve. If zero or very few failures are
___________
Figures in square brackets refer to the Bibliography.

62418 © IEC:2010 – 7 –
observed it is not possible to determine an activation energy, and a value can be selected
from the literature.
c) Measure the resistance. The samples may be cooled to room temperature for the
resistance test. Cool in less than 2 h to room temperature. (Measurement of the
resistance changes is, in principle, possible in situ at the aging temperature.)
Recommended read points: 168 h, 500 h, 1 000 h.
NOTE Resistance measurements can extend beyond 2 000 h if saturation of void growth is desired.
d) Calculate the relative change in resistance, as a percentage of the line-resistance prior to
the bake, ΔR (%).
e) Calculate the failure rate (number of failed samples/total sample size). For failure criterion
see Clause 6.
f) Determine the total length of metal line inspected.
g) If necessary, inspect failed samples to confirm the failure mode (see 5.3 for Al and e.g. [3]
for Cu).
5.3 Inspection method
The inspection method consists of the following steps.
a) Bake the samples at a specified temperature for a specified time. The recommended
temperature is 200 °C for Al metallization. Recommended read points: 0 h, 168 h, 500 h,
1 000 h. Because the maximum void initiation and growth depends on the bake
temperature, it is recommended to test at more than one temperature. The recommended
temperature range is 150 °C to 275 °C for Al. Baking times can extend beyond 2 000 h if
saturation of void growth is desired.
b) Remove the scratch protection layer with standard deprocessing techniques. If a lower
level of metallization needs to be inspected, remove all other layers to expose the desired
metallization level.
NOTE Deprocessing for Al technologies can be done with e.g. RIE (reactive-ion etching) etch for plasma
nitride/oxynitride/TEOS (incl. TiN), H O (50 °C) for Ti/TiN barrier layers, and PES (Phosphoric Acid, Acetic Acid,
2 2
Nitric Acid) etch for Al.
c) The sample shall not be sputtered with a carbon or gold layer prior to mounting in the
Scanning Electron Microscope (SEM).
d) Place the sample in the SEM, perpendicular to the incident electron beam.
e) Adjust the magnification of the SEM, such that voids down to class A (see Table 1) can be
observed. Count the number of voids in the metal lines. Both wedge shaped voids and slit
shaped voids shall be counted.
f) Perform detailed inspection at an appropriate magnification of the voids observed, to
classify these in accordance with Table 1.
g) Determine the total length of metal line inspected.
h) Calculate the densities of Class A, Class B, and Class C voids N , N , N (in voids per cm)
A B C
with 60 % confidence using Poisson statistics.
In order to classify the severity of the voids observed, the following classification scheme is
used:
Table 1 – Void classification
Class Void size/linewidth
Not counted <10 %
A ≥10 %, …, <25 %
B ≥25 %, …, <50 %
C ≥50 %
– 8 – 62418 © IEC:2010
6 Failure criteria
6.1 Resistance method
The failure criterion for layered metallization with refractory shunt layers is a preselected
percent resistance increase. The value shall be selected within the range from 5 % to 30 %.
NOTE If the metallization is a single-alloy component, such as AlSi or AlCu, the failure criterion of the method is
an open-circuit of the test structure.
6.2 Inspection method
The failure criterion is predefined maximum number of voids in the classes A, B, C, e.g.
N < 1/cm.
C
7 Data interpretation and lifetime extrapolation (resistance change method)
The most straightforward way to interpret the data employs the median time to failure, where
failure is determined by either a specified resistance shift or an open circuit. Because
extended duration can be required to produce sizeable resistance shifts, a lower relative
resistance failure criterion may be desired.
A good way to avoid long test durations is to combine several test structures to effectively
form one long line (or via chain) and plot the resistance change versus time. A well-behaved
plot is usually obtained, which can be easily extrapolated to longer test times to determine the
median time to failure.
The time-to-failure for the chosen fractional change in resistance is found either from plots of
the fractional resistance change versus stress time or the square root of stress time. Void
growth is generally agreed to be a diffusive process and the increase in line resistance (for
layered metallizations) is proportional to the void length, which shall be proportional to a
diffusion length (the average distance a species (i.e. a vacancy in stress voiding mechanism)
travels due to diffusion within the lifetime of the species). Thus a plot of fractional resistance
change versus the square root of the time has the advantage of being approximately linear
until void growth approaches saturation. Failure time is recorded when the resistance exceeds
the level defined for failure.
Plot cumulative failures vs. the log of readout time, assuming failure times are log-normally
distributed, for determination of product lifetime.
A physical model [1, 2] can be used to relate the failure time to physical variables and is
shown as below
-n
t = A × (T - T ) × exp(E /kT) (1)

f dep a
where
t is the median time to failure;
f
A is a constant;
T is the temperature during bake or in use;
E is the effective activation energy for the diffusion process;
a
k is Boltzmann's constant;
n is the creep exponent; and
T is the effective deposition temperature of the isolation layer surrounding the metal.
dep
62418 © IEC:2010 – 9 –
In first approximation this temperature is equal to the deposition temperature. For the
exponent n a value of 2 is used, for Al and for Cu a value of 3 is more appropriate [4].
An effective acceleration factor for stress voiding can be obtained from the ratio of the failure
time under use conditions to that under stress conditions, and is given by
n
A = t /t = (ΔT /ΔT ) × exp [(E /k) × (1/T – 1/T )], (2)
F f,u f,s s u a u s
where
A is the acceleration factor;
F
t is the median time to failure;
f
T is the temperature during bake or in use;
E is the effective activation energy for the diffusion process;
a
k is Boltzmann's constant;
n is the creep exponent; and
ΔT = (T–T ).
dep
The subscripts u and s denote use and stress conditions, respectively. The effective
activation energy can be obtained from a plot of t versus 1/kT for several temperatures. The
f
effective activation energy is influenced by the stress in the metal, by the microstructure of
the line within several tens of microns on either side of the void, and by contributions to mass
transport from interfacial diffusion. Care shall be taken when using Equation (2) that void
growth has not saturated.
The effective activation energy can be determined from fit by the model (1) of the maximum or
average resistance shifts for large numbers of structures of the same type baked at different
temperatures. Alternatively, the median time to failure obtained for the same structure at
several temperatures can be plotted against 1/kT and the resulting slope is interpreted as the
effective activation energy. Data interpretation can be difficult in AlCu alloys because the Cu
precipitation changes with temperature due to the change in solubility.
Arrhenius model (without stress term)
There is peak temperature in stress migration failure rate. By using Equation (1), the
existence of peak failure rate temperature can be expressed. If the chosen temperature range
is below the peak temperature, and if the Arrhenius-plot is a straight line, Equation (1) may be
approximated by the Arrhenius model as shown in Equation (3):
t = A × exp(E /kT) (3)
f a
The activation energy can be obtained easily with only life test temperature and the lifetime.
An effective acceleration factor for stress voiding can be obtained in the same manner from
the ratio of the failure time under use conditions to that under stress conditions, and is given
by:
A = t /t = exp [(E /k) × (1/T – 1/T )]  (4)
F f,u f,s a u s
8 Items to be specified and reported
8.1 Resistance change method
Items to be specified and reported in the resistance change method includes:

– 10 – 62418 © IEC:2010
a) bake temperatures;
b) failure criteria;
c) test structure (line configuration, straight, serpentine, etc.), linewidth and length, number
of vias, via geometry and placement );
d) sample size;
e) wafer fabrication batch(s);
f) measurement intervals (test points);
g) plot(s) of the fractional resistance change versus stress time;
h) plot of the median time to failure t versus 1/KT, including effective activation energy (if
f
determined);
i) the extrapolated lifetime at use temperature (if determined).
NOTE In addition, any deviations from the standard stress void monitor procedure shall be noted.
8.2 Inspection method
Items to be specified and reported in the inspection method includes:
a) bake temperatures;
b) failure criteria;
c) test structure line configuration (straight, serpentine, etc), width or (line-width/grain size),
ratio line length;
d) sample size;
e) wafer fabrication batch(s);
f) measurement Interval(s);
g) the total length of metal line inspected;
h) the number of voids detected per class (N , N , N );
A B C
i) inspection results (picture) of failure sample.
NOTE In addition, any deviations from the standard stress void monitor procedure shall be noted.

62418 © IEC:2010 – 11 –
Annex A
(informative)
Stress migration mechanism
Stress-induced voiding was first identified in 1984 [5, 6], as line failures and voids started
appearing in interconnect lines at zero current density. The problem was soon identified to be
caused by mechanical stress. During the different stages of the integrated circuits (IC)
processing, the patterned metal interconnect lines (see Figure A.1a) are covered with an
intermetal dielectric layer, or a protective passivation layer. During the deposition of these
dielectric layers, the wafer is at a temperature of several hundred degrees Celsius. The metal
line expands to occupy a volume which is larger (ΔV) than the volume at room temperature
(Figures A.1b and A.1c). Upon cooling down to room temperature a large tensile stress is built
up in the metal line, caused by the large differences in the thermal expansion coefficients of
the metallization and the surrounding materials [7].If the stress relaxes completely, the
volume difference ΔV will appear in the form of a void (Figure A.1d).

ΔV
Al
IEC  720/10 IEC  721/10
Figure A.1.a – Cross-section Figure A.1.b – Metal volume increase
of a patterned metal line during dielectric deposition

Al
IEC  722/10
ΔV
IEC  723/10
Figure A.1.c – Metal and dielectric at

dielectric deposition temperature
Figure A.1.d – Metal volume decrease

during cool-down to room temperature

Figure A.1 – Schematic representation of the stress-void
formation mechanism in Al
The subject has been extensively reviewed by Okabayashi [8]. Susceptible metallizations can
grow voids in lines and under or over vias. For simple metallizations like AlSi, such voids can
cause catastrophic failure. For metallizations layered with a refractory shunt layer, voids
cause resistance increases and interact with other failure mechanisms, such as
electromigration and mechanical failure, to shorten lifetime. Stress-induced voiding, can occur
during processing, storage, and use, and is a reliability concern for microelectronics chips that
use Al-based alloys or Cu for on-chip wiring.
The number of voids in different metallizations tends to saturate to a constant value with time.
Beyond this time, the void volume continues to rise and saturates when the stress in the metal
is relaxed. Void nucleation is influenced by several factors, e.g. the presence of etch residue
contaminants or metal damage (holes, roughness, etc.) after metal etch and cleaning, defects
in barrier layers, line-width, ratio of grain-size to line width, and the amount of the alloying

– 12 – 62418 © IEC:2010
element (such as Cu in Al) and variations in line widths and grain size distribution, as well as
several factors listed in Annex B.
The rate of void growth is controlled primarily by two quantities:
a) the tensile stress in the metal;
b) self diffusivity of the metal.
The tensile stress increases linearly as temperature decreases below the dielectric deposition
temperature, while diffusivity increases exponentially with temperature. The product of these
two factors produces a peak in the rate of void growth which is located between the dielectric
deposition temperature and use temperature. Published data indicates that this peak can
occur anywhere in the range from 90 °C to 300 °C [5, 9, 10] for Al and between 150 °C and
200 °C for Cu [4]. The tensile stress is in first approximation proportional to the coefficient of
–6
thermal expansion (CTE) and the Young modulus (E) of the metal. With values of 23,9 10 /K,
–6
70 GPa and 16,5 10 /K, 110 GPa for the CTE and Young modulus of Al and Cu respectively
[4] it is expected that the tensile stress in Cu is slightly higher than in Al. However, because of
the much lower mobility of Cu atoms the flow of vacancies in Cu is much lower than in Al
under comparable stress conditions. Although Cu seems to be much more robust against
stress voiding than Al, there are still circumstances where Cu can lead to severe stress
voiding. The most sensitive structure is a single via on a wide metal line. Defects in the
barrier layer in or near the via can enhance void nucleation [11].

62418 © IEC:2010 – 13 –
Annex B
(informative)
Technology-dependent factors for aluminium

A variety of technology-dependent factors define and modify the stress distribution and the
diffusivity in the metal. These include for example:
a) metal microstructure and additions like alloy impurities or silicon (Si);
b) metal deposition temperature;
c) prior heat treatment;
d) properties of the passivation layer;
e) interfacial adhesion between the passivation and metal;
f) refractory cladding layers and associated mechanical properties;
g) electrical properties of cladding layer;
h) line dimensions;
i) metal-etch profile of the line in cross-section;
j) layout shape;
k) the concentration of additions to the Al, e.g. Cu and Si;
l) interfacial diffusivity (Al/SiO , Al/TiAl , etc.);
m) the presence, configuration, and material of inter-level interconnects;
n) passivation deposition temperature;
o) cool-down rate of wafer after last process step, from temperatures comparable to the
passivation deposition temperature;
p) intermetallic reactions (for layered metallizations).

– 14 – 62418 © IEC:2010
Annex C
(informative)
Technology-dependent factors for copper

A variety of technology-dependent factors define and modify the stress distribution and the
diffusivity in the metal. These include for example:
a) prior heat treatment;
b) properties of the passivation layer;
c) interfacial adhesion between the passivation and metal;
d) line dimensions;
e) metal-etch profile of the line in cross-section;
f) cool-down rate of wafer after last process step, from temperatures comparable to the
passivation deposition temperature;
g) intermetallic reactions (for layered metallizations);
h) gouging of vias in dual damascene Cu interconnects.

62418 © IEC:2010 – 15 –
Annex D
(informative)
Precautions
D.1 Variation of resistance change
It is possible that not all structures on a wafer exhibit resistance shifts. This can be due to
across-wafer variations in e.g. line width, temperature during oxide deposition, metal
thickness, etc. If all wafers are similar in behaviour and the wafer map pattern of resistance
shifts is also the same, this can be handled by considering only the failing structures for
worst-case lifetime extrapolation. However, if failure is random and varies from wafer to wafer
as well, more sophisticated techniques for analysis will likely be required.
D.2 Copper solubility in AlCu
At too high bake temperatures increased Cu solubility in AlCu alloys can affect the results.
For example, 0,5 % Cu dissolves completely in the Al at 310 °C, which can change the mass
transport above this temperature.
D.3 Effective passivation deposition temperature
In Equation (2), ΔT = T – T , and ΔT = T – T , where T is given as the passivation
s o s u o u o
deposition temperature. However, as indicated above in Clause 7, T is only an ‘effective’
o
passivation deposition temperature, and is likely to be less than the actual passivation
deposition temperature [12]. If the difference between T and T is large, as it can be in the
o dep
case of wide lines, then the value of the A calculated by Equation (2) can be significantly
F
affected. This is easily seen by plotting the A in Equation (2) versus.T for T = 20 °C, an
F s u
activation energy of 0,5 eV, for example, and for three different values of T , 400 °C, 350 °C,
o
and 300 °C. The corresponding peak values for the A range from over 1 100 to just below
F
300. For this reason, it is recommended that a wide enough range of temperatures be used to
define the location of the peak A and to determine the effective T .
F o
D.4 Calculated void volume
Assuming the dielectric behaves elastically, the maximum volume of voiding in a specific
structure can be calculated by assuming that only thermal contraction of the metal is relevant.
Then the maximum volume possible for voiding is equal to the volume change for
unconstrained metal, and is given by
ΔV = 3α × ΔT × V (D.1)
where
V is the volume of the interconnect of concern;
–6 –1
α  is the thermal expansion coefficient of the metal (approximately 25 × 10 K ); and
ΔT is the difference in temperature between the passivation deposition temperature and the
stress (bake) temperature.
If the bake temperature is taken at room temperature and the passivation deposition
temperature is 425 °C, for example, then (ΔV/V)max. = 3 % for Al. Clearly, at higher use
temperatures, this relative volume will be less. Observation of voiding in excess of maximum

– 16 – 62418 © IEC:2010
volume at room temperature is likely to mean that some other mechanism in addition to, or
besides, stress voiding is involved.
For several reasons, Equation (2) is generally an overestimate of the maximum volume of
voiding. First, the temperature delta is taken as the difference between the passivation
deposition temperature and the bake temperature, implying that the enclosing dielectric is
rigid, and that the metal is unconstrained and allowed to expand freely until encapsulated in
the oxide. Neither of these cases is accurate. The metal is constrained by the substrate and
therefore does not expand to its full potential, and the oxide relaxes somewhat in response to
the tensile stress in the metal at temperatures below the oxide deposition temperature. Both
of these factors reduce the strain in the metal compared to what is predicted by Equation (1).
The result is equivalent to having a lower value for the passivation temperature in Equation
(1). Second, rather than the coefficient of thermal expansion (CTE) for metal, the difference
between the CTE of the metal and the surrounding oxide shall be used, to be strictly accurate.
–6 –
(However, since the CTE for SiO is around 0,5 10 /K, and that of e.g. Al is around 25 10
/K, the error is small.) This will further reduce the magnitude of voiding predicted by Equation
(1). Since bake temperatures are generally much higher than room temperature, realistic
volume fractions of voiding can be closer to 1 % than 3 %. In addition, the measurement shall
account for the thermal coefficient of resistance for both the metal and the refractory shunt
layer when estimating void volumes from resistance.
In attempting to compare voiding data from different fabrication processes care shall be taken
to allow for differences in the effective sheet resistances of the cladding layers. The
resistance shift produced by a 1 μm long void in a line that is 1 μm wide will be determined by
the resistivity and thickness of the cladding layer in the voided region. The thicker the layer,
the smaller the resistance change. A titanium (Ti) layer will produce a greater resistance
change than a tungsten (W) layer of the same thickness because of the higher resistivity of
the Ti.
NOTE For multi-level Al metallizations, via chains with W-studs are effective because W has a larger thermal
expansion coefficient than SiO . Hence, the stress in metal lines immediately above or below the studs is greater
than elsewhere in the line. The volume of the Al interconnect attached to the stud should be sufficient to generate
a void large enough to extend beyond the stud. Otherwise, it will be difficult to detect electrically the presence of
the void.
62418 © IEC:2010 – 17 –
Bibliography
[1] RAUCH, S.E., and T.D. SULLIVAN. Modeling Stress-Induced Void Growth in Al-4wt%
Cu Lines, Proc. SPIE, 1993, vol. 1805, pp 197-208,. Submicrometer Metallization
Challenges, Opportunities, and Limitations; Thomas Kwok, Takamara Kikkawa, Krishna
Shenai, Eds
[2] SULLIVAN, T.D., et al., Accelerated Testing for Stress Voiding in Multilayered
Metallization, Electrochemical Society Proceedings, 1995, vol. 95-3, pp 54-68
[3] WU, H., et al, Reliability Issues and Advanced Failure Analysis Deprocessing
Techniques for Copper/Low-K Technology, IEEE Proc. of the IRPS, 2003, p. 536.
[4] E.T. OGAWA, E.T., et al, Stress-Induced Voiding under Vias connected to wide Cu
Metal Leads, IEEE Proc. of the IRPS, 2002, p.312.
[5] KLEMA, J., R. PYLE, and E. DOMANQUE, Reliability Implications of Nitrogen
Contamination During Deposition of Sputtered Aluminum/Silicon Metal Films, IEEE Proc.
of the IRPS, 1984, pp. 1-5.
[6] CURRY, J., G. FITZGIBBON, Y. GUAN, R. MUOLLO, G. NELSON, and A. THOMAS,
Proc. 22nd Int. Reliability Symp., 1984, p. 6IEEE, New York,.
[7] FLINN, P.A., A. SAUTER MACK, P.R. BESSER, and T.N. MARIEB, MRS Bulletin, 1993,
vol. 18(12), , p. 26.
[8] OKBAYASHI, HIDEKEZU, Stress-Induced Void Formation in Metallization for Integrated
Circuits, Matls. Sci. and Eng., 1993, R11, No. 5, , Dec. 1, , pp. 191 241.
[9] MCPHERSON, J.W., and C. F. DUNN, A Model for Stress-Induced Metal Notching and
Voiding in Very Large-scale-Integrated Al-Si(1%) Metallization, J. Vac. Sci. Technol.,
1987, B 5(5), pp. 1321-1325,.
[10] HINODE, K., OWADA, N., NISHIDA, T., and MUKAI, K., Stress Induced Grain Boundary
Fractures in Al-Si interconnects, J. Vac. Sci. Technol., 1987, B 5(2), pp. 518-522.
[11] LIM, Y.K. et al, Stress Voiding in Multi-Level Copper/Low-k Interconnects, IEEE Proc. of
the IRPS, 2004, p.240.
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Growth Models and Refinements, Annu. Rev. Mater. Sci., 1996, pp. 333-364.

____________
– 18 – 62418 © CEI:2010
SOMMAIRE
AVANT-PROPOS.19
1 Domaine d’application .21
2 Équipement d’essai .21
3 Structure d'essai .21
3.1 Modèles de structure d'essai .21
3.2 Modèle de ligne.21
3.3 Chaîne de trous de liaison.21
3.3.1 Types de modèles .21
3.3.2 Modèle pour le traitement à l’aluminium (Al) .22
3.3.3 Modèle pour le traitement au cuivre (Cu) .22
4 Température de contrainte .22
5 Procédure .22
5.1 Méthodes d'évaluation des cavités dues aux contraintes .22
5.2 Méthode de mesure de résistance .22
5.3 Méthode d’inspection .23
6 Critères de défaillance.24
6.1 Méthode de la résistance .24
6.2 Méthode d’inspection .24
7 Interprétation d
...