IEC TR 63133:2017

IEC TR 63133 ®
Edition 1.0 2017-10
TECHNICAL
REPORT
colour
inside
Semiconductor devices –
Scan based ageing level estimation for semiconductor devices
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IEC TR 63133 ®
Edition 1.0 2017-10
TECHNICAL
REPORT
colour
inside
Semiconductor devices –
Scan based ageing level estimation for semiconductor devices

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.01 ISBN 978-2-8322-4903-1

– 2 – IEC TR 63133:2017 © IEC 2017
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms, definitions and abbreviated terms . 6
3.1 Terms and definitions . 6
3.2 Abbreviations . 7
4 Ageing level . 9
4.1 Overview. 9
4.2 Ageing level characterization technique (test method) . 9
4.3 Architecture and operation . 11
4.4 Performance estimation storage element . 12
4.5 Simulation results . 14
4.6 Experimental results . 14
Bibliography . 17

Figure 1 – Reliability bathtub curve . 5
Figure 2 – Schematic of ageing level estimation technique . 9
Figure 3 – A guard band and estimated ageing level . 10
Figure 4 – Ageing level monitoring and scan chain architecture . 11
Figure 5 – State diagram for performance estimation controller. 12
Figure 6 – Modified scan cell architecture . 13
Figure 7 – Operations of shadow latch, storage element, and PERC according to CLK
and PECLK . 13
Figure 8 – Simulation results for a case in which ageing occurs on a data path. 14
Figure 9 – PECLKs for various delay points and their results . 16

Table 1 – Power consumption compared with prior work . 15

– 3 – IEC TR 63133:2017 © IEC 2017
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
Scan based ageing level estimation for semiconductor devices

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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The main task of IEC technical committees is to prepare International Standards. However, a
technical committee may propose the publication of a technical report when it has collected
data of a different kind from that which is normally published as an International Standard, for
example "state of the art".
IEC TR 63133, which is a technical report, has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this technical report is based on the following documents:
Enquiry draft Report on voting
47/2405/DTR 47/2425/RVDTR
Full information on the voting for the approval of this technical report can be found in the
report on voting indicated in the above table.

– 4 – IEC TR 63133:2017 © IEC 2017
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
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– 5 – IEC TR 63133:2017 © IEC 2017
INTRODUCTION
A semiconductor device has an important role in reliability-critical applications, e.g., space, air
and road vehicles, medical equipment. Although new technology has improved performance,
power efficiency, cost efficiency etc., but the reliability becomes a serious threat [1] . As can
be seen in Figure 1, failure rate is decreases in early life, and low constant failure rate is
preserved for a while, then wear out failure rate is increases significantly. Especially for
reliability-critical applications, it is important to precisely monitor the ageing level to forewarn
of any impending catastrophic failure. The semiconductor ageing is caused by
negative/positive bias temperature instability, hot carrier injection, and time dependent
dielectric breakdown, electro migration, and stress migration, etc. Path delay is known to be
increased due to various ageing failures. Although a few ageing monitoring techniques have
been developed [2 to 5], the ageing level has not been precisely diagnosed. For reliability-
critical applications, the ageing level information can be utilized for taking adequate measures
timely, e.g., device replacement, performance switching using dynamic voltage-frequency
scaling. This document describes an efficient technique to monitor the ageing and
characterize the ageing level.
Early life failure region
Screens
(infant mortalities)
Wearout failure region
(intrinsic failures)
Operating life failure region
(extrinsic failures)
0 Time
Product useful life time
IEC
Figure 1 – Reliability bathtub curve

___________
Numbers in square brackets refer to the Bibliography.
Instantaneous failure rate
– 6 – IEC TR 63133:2017 © IEC 2017
SEMICONDUCTOR DEVICES –
Scan based ageing level estimation for semiconductor devices

1 Scope
This Technical Report specifies a design technique of performance estimation storage
element, which can monitor semiconductor ageing and characterize ageing level. The
estimated ageing level can be used to improve the reliability of system.
2 Normative references
There are no normative references in this document.
3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
ISO Online browsing platform: available at http://www.iso.org/obp
3.1.1
transistor ageing
for a field effect transistor, increase with time of its threshold voltage
Note 1 to entry: This increase is caused by a combination of NBTI, PBTI, HCI, TDDB, EM, and SM.
Note 2 to entry: This effect decreases the drain current and transconductance and thereby increases the path
delay.
3.1.2
ageing level
degree of transistor ageing under known operating conditions
3.1.3
ageing level monitoring
method of evaluating transistor age
...