IEC 62374-1:2010

IEC 62374-1 ®
Edition 1.0 2010-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices –
Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers

Dispositifs à semiconducteurs –
Partie 1: Essai de rupture diélectrique en fonction du temps (TDDB) pour les
couches intermétalliques
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IEC 62374-1 ®
Edition 1.0 2010-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices –
Part 1: Time-dependent dielectric breakdown (TDDB) test for inter-metal layers

Dispositifs à semiconducteurs –
Partie 1: Essai de rupture diélectrique en fonction du temps (TDDB) pour les
couches intermétalliques
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
P
CODE PRIX
ICS 31.080 ISBN 978-2-88912-178-6
– 2 – 62374-1 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Terms and definitions .5
3 Test equipment.6
4 Test samples.6
4.1 General .6
4.2 Test structure .6
5 Procedures.8
5.1 General .8
5.2 Pre-test .8
5.3 Test conditions.8
5.3.1 General .8
5.3.2 Electric field .8
5.3.3 Temperature.9
5.4 Failure criterion .9
6 Lifetime estimation .10
6.1 General .10
6.2 Acceleration model.10
6.3 Formula of E model .10
6.4 A procedure for lifetime estimation .10
7 Lifetime dependence on inter-metal layer area .13
8 Summary.13
Annex A (informative) Engineering supplementation for lifetime estimation .14
Bibliography.16

Figure 1 – Schematic image of test structure (comb and serpent pattern) .7
Figure 2 – Schematic image of test structure (comb and comb pattern) .7
Figure 3 – Cross-sectional image of test structure for line to stacked line including via .8
Figure 4 – Cross-sectional image of test structure for stacked line to stacked line
including via .8
Figure 5 – Test flow diagram of constant voltage stress method .9
Figure 6 – Weibull distribution plot.11
Figure 7 – Procedure to estimate the acceleration factor due to the electric field
dependence.12
Figure 8 – Procedure to estimate the activation energy using an Arrhenius plot .12

62374-1 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
Part 1: Time-dependent dielectric breakdown (TDDB)
test for inter-metal layers
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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International Standard IEC 62374-1 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2063/FDIS 47/2077/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 62374 series, under the general title Semiconductor devices,
can be found on the IEC website.

– 4 – 62374-1 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
62374-1 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
Part 1: Time-dependent dielectric breakdown (TDDB)
test for inter-metal layers
1 Scope
This part of IEC 62374 describes a test method, test structure and lifetime estimation method
of the time-dependent dielectric breakdown (TDDB) test for inter-metal layers applied in
semiconductor devices.
2 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
2.1
leakage current of inter-metal layer
I
leak
current through the dielectric layer when a use voltage is applied
2.2
initial leakage current of inter-metal layer
I
leak-0
leakage current of inter-metal layer before a stress voltage is applied
2.3
compliance current
I
comp
maximum current of the voltage-forcing equipment
NOTE A compliance limit can be specified for a particular test.
2.4
measured leakage current of inter-metal layer
I
meas
measured current in constant voltage stress (CVS) test
2.5
breakdown time
t
bd
summation of time during which stress voltage is applied to inter-metal layer until failure
NOTE In CVS test, applied stress voltage is interrupted by measuring and assessing repeatedly (see Figure 5).
2.6
dielectric layer thickness
t
d
physical thickness of dielectric layer which is pitched between metal lines

2.7
stress voltage
V
stress
voltage applied during CVS test

– 6 – 62374-1 © IEC:2010
2.8
use voltage
V
use
voltage applied during pre-test and used for lifetime estimation
NOTE This voltage is usually power supply voltage.
2.9
metal electrode length
L
total length of metal electrode which is pitching the dielectric layer
2.10
electric field for inter-metal layer
E
im
voltage across a dielectric layer divided by its horizontal width between metal lines
NOTE The dielectric layer width should be determined by a consistent documented method by the physical
measurement method with SEM, TEM or other. The method or a reference to a documented standard which
describes the method should be included in the data report.
3 Test equipment
This TDDB test can be applied by both the package level test and the wafer level test. A high
temperature oven is used for the package level test. In the case of the wafer level test, a
wafer probe with a hot plate or hot chuck is necessary. Additionally the instruments need to
have sufficient resolution to detect changes of leakage current under high temperature
condition.
NOTE Package level test is test on test structures assembled in package.
4 Test samples
4.1 General
Test samples for TDDB test for inter-metal layer shall have the following test structure.
4.2 Test structure
An appropriate test structure for this test is an interdigitated one as shown in Figure 1,
consisting of comb and serpent patterns, which are connected to the voltage source lines.
There is an alternative structure, that is the interdigitated comb and comb structure shown in
Figure 2. Test structure leads shall be designed to prevent unexpected failures outside the
test structure during the TDDB test. Patterns with vias (Figures 3 and 4) need to be
considered because the failure mechanism might be different from a line-to-line pattern
without via. Unless otherwise specified comb and serpent pattern are be recommended. The
minimum line-to-line spacing is the most severe condition for this mechanism. Therefore, the
minimum dimension allowed by the layout rule shall be evaluated. The total length of the
metal line is recommended to be in the range from 0,01 m to 1 m. For the accurate lifetime
estimation, it is recommended that at least three device conditions of area or length be used,
so proper scaling can be achieved. Unless otherwise specified the above-mentioned
conditions shall be used for test structure parameters.

62374-1 © IEC:2010 – 7 –
Width of dielectric layer
Dielectric layer
between metal lines
Metal line
(serpent pattern)
V
Metal line
(comb pattern)
GND
Metal line
(comb pattern)
V
IEC  2106/10
Figure 1 – Schematic image of test structure (comb and serpent pattern)

Width of dielectric layer
Dielectric layer
Metal line
(comb pattern)
V
Metal line
(comb pattern)
GND
IEC  2107/10
Figure 2 – Schematic image of test structure (comb and comb pattern)

– 8 – 62374-1 © IEC:2010
Upper layer metal
Inter-metal layer
Via
Lower layer metal
Barrier layer
IEC  2108/10
Figure 3 – Cross-sectional image of test structure for line to stacked line including via

Upper layer metal
Inter-metal layer
Via
Lower layer metal
Barrier layer
IEC  2109/10
Figure 4 – Cross-sectional image of test structure
for stacked line to stacked line including via
5 Procedures
5.1 General
In this section the test procedure is explained. Figure 5 shows a procedure for the constant
voltage stress method.
5.2 Pre-test
Pre-test is performed to identify initial failed samples. The leakage current is measured at the
applied use voltage. If the measured current is larger than the defined criterion, then that
sample is rejected as an initial failed sample. When obtaining the defective distribution as
necessary, the CVS test without pre-test may be effective. In this case the pre-test can be
omitted.
5.3 Test conditions
5.3.1 General
The following test condition is recommended for the TDDB test. The sample size should be
selected to provide the necessary confidence level for the application.
5.3.2 Electric field
shall be decided by a trial test to get the TDDB lifetime data in a reasonable time. It is
V
stress
preferable to select at least three electric fields for estimating the field acceleration factor.

62374-1 © IEC:2010 – 9 –
5.3.3 Temperature
It is preferable to select at least three temperatures. Use-junction temperature shall be in the
test temperature range for estimating the temperature acceleration factor (activation energy).
5.4 Failure criterion
Unless otherwise specified, I which exceeds the failure criterion indicates device failure.
meas
The measurement condition (temperature, electric field) for the pass judgment shall be set up
at use conditions or stress conditions. The leakage current shift for failure shall be
established in consideration of the initial current, the measurement resolution, and the
products specifications.
Apply operating use
conditions
leakage current measurement
( )
I
leak-0
No
Pre-test
Reject as initial failure
I
< defined criterion
leak-0
Yes * Criterion must be set less than I comp
Start test
(t =0)
) t
Apply stress voltage ( V interval
stress
leakage current measurement
I
( meas )
CVS
No Record breakdown time
I
meas < defined criterion
(t )
bd
Yes
No
t < t ?
max
Stop test
Yes
t = t + t
interval
IEC  2110/10
t, t , t  total stress voltage applied time, maximum stress voltage applied time for
max interval
evaluation, stress voltage applied time of each measurement loop,
respectively
Figure 5 – Test flow diagram of constant voltage stress method

– 10 – 62374-1 © IEC:2010
6 Lifetime estimation
6.1 General
The method to get the temperature and voltage acceleration factor is explained in this section.
6.2 Acceleration model
The electric field E model is widely used to consider as an acceleration model and it contains
the temperature acceleration model (Arrhenius model). Unless otherwise specified in the
failure acceleration model, E model should be adopted as the acceleration model for lifetime
estimation.
NOTE There were some reports based on the square root-E model recently, and other models' verifications are
expected to be published in the future. When a new type of model is adopted, an evaluation to confirm the model
adaptability needs to be carried out.
6.3 Formula of E model
⎛ E ⎞
a
TTF = A×exp⎜ ⎟exp()− γ × E
(1)
im
⎜ ⎟
kT
⎝ ⎠
where
TTF is the time to failure;
A is the constant;
E is the electric field for inter-metal layer;
im
k is the Boltzmann constant;
γ  is the electric field acceleration factor;
E is the activation energy.
a
6.4 A procedure for lifetime estimation
a) Make a plot of each stress data point using a Weibull distribution or Log-normal
distribution. Unless otherwise specified, Weibull is recommended as the distribution of
choice. Refer to [8] for an explanation of the Weibull label, left axis cumulative failure
rate and bottom axis breakdown time – see Figure 6.
b) Calculate each failure time t(F%). Next, make a plot of each failure time versus electric
field values (E model). Calculate the electric field acceleration factor from the slope (see
Figure 7). Then plot each failure versus with the reciprocal of temperature (1/T). Calculate
the temperature acceleration factor from the slope (activation energy) (see Figure 8).
Using the above acceleration factors, estimate the lifetime t(F%) at the use condition at
certain temperature and voltage.
NOTE 1 For Weibull statistics the correct time to be determined is the time at 63,2% failure. It is the characteristic
time of the Weibull distribution and has the largest confidence. In the case of the log-normal distribution the correct
time would be the time at 50% failures. So, when the electric field acceleration factor or temperature acceleration
factor is calculated, it is preferable that they be calculated with the failure rates which are near that value. The
cumulative failure distribution, especially for the Weibull distribution, should be recorded.
NOTE 2 Highly accelerated tests may not provide long enough breakdown times to provide adequate time
resolution and may not be enough to determine the correct acceleration model and the correct acceleration factor.
Long term test at package level may be required.
———————
The figures in square brackets refer to the Bibliography.

62374-1 © IEC:2010 – 11 –
Weibull distribution for breakdown time
E1 E2 E3
F(A1%)
t1 t2 t3
Log- tbd
IEC  2111/10
E1, E2, E3 (MV/cm) magnitude of applied electric field to the inter-metal layer in the case
of using E model. Relationship of electric field strength is described by
the order of “E1 > E2 > E3”.
t1, t2, t3 (h) breakdown time when the cumulative failure reaches A1 %
Figure 6 – Weibull distribution plot

Cumulative % failure
– 12 – 62374-1 © IEC:2010
E dependence plot
T
use
Slope: γ
t3
t2
t1
E3 E2 E1
E
use
Electric field E  (MV/cm)
IEC  2112/10
Figure 7 – Procedure to estimate the acceleration factor due to the electric field
dependence
Arrhenius plot
Slope : Ea
t3
T3
t2
T2
t1
T1
1/T (1/K)
IEC  2112/10
Figure 8 – Procedure to estimate the activation energy using an Arrhenius plot
Ln – Lifetime
Ln – Lifetime
62374-1 © IEC:2010 – 13 –
7 Lifetime dependence on inter-metal layer area
Revised lifetime is often used to carry out lifetime estimation of actual products with various
dielectric areas which is pitched between metal lines. To convert the test sample lifetime with
a certain dielectric area into an actual product lifetime with a different one, the following
formula shows a simple and easy procedure, which uses a Weibull distribution parameter. The
formulas (2) and (3) show a simple Weibull, so only Weibull is recommended as the
distribution of choice. In general, the line-to-line spacing of the test structure is constant.
Therefore, the metal electrode length L which is the pitching dielectric layer can be used as
the dimension parameter instead of the dielectric area A of formula (3).
m
⎛ ⎞
A
TTF = TTF ×⎜ ⎟ (2)
2 1
⎜ ⎟
A
⎝ 2⎠
m
⎛ ⎞
L
TTF = TTF ×⎜ ⎟ (3)
2 1
⎜ ⎟
L
⎝ 2⎠
where
TTF , A and L is the time to failure, its dielectric area which is pitched between metal lines
1 1 1
and its length of metal electrode of test sample, respectively;
TTF , A and L is the time to failure, its dielectric area which is pitched between metal lines
2 2 2
and its length of metal electrode of actual product, respectively;
m is the shape parameter of Weibull distribution
NOTE Sufficient consideration should be taken to avoid high electric fields in the corners of the test structure. If
voltage stress concentration in the corners occurs due to improper test structure design, the failure distribution will
deviate from the intrinsic failure distribution. Failure analysis should be done to confirm that failure has occurred in
the corner of the metal line. In case that the extrinsic failures concentrate on the corner, they may be excluded
from the lifetime analysis.
8 Summary
The following details shall be specified in the applicable specification:
a) stress conditions (voltage and temperature);
b) conditions of device for failure criteria (leakage current and its measurement condition);
c) specific pattern and its dimension of test structure;
d) sample and lot size for testing;
e) specific lifetime estimate model;
f) specific lifetime estimate condition.

– 14 – 62374-1 © IEC:2010
Annex A
(informative)
Engineering supplementation for lifetime estimation

A.1 Typical value of acceleration factor
The basic formula of E model is the same as shown in 6.3. Typical acceleration factors are
indicated below. According to the result of recent research, various types of combination
which consisted of both a material and inter-metal layer structure brought widely varied values.
The test method of Subclause 5.3 is recommended to extract the appropriate acceleration
factors for lifetime estimation.
⎛ E ⎞
a
TTF = A × exp exp()– γE (A.1)
⎜ ⎟
kT
⎝ ⎠
γ is the electric field acceleration factor
2,1 cm/MV to 6,0 cm/MV
E is the activation energy
a
0,1 eV to 0,57 eV
A.2 Procedure to plot data using Weibull statistics
The plot of the cumulative number of failures against the time-to-breakdown gives the
parameters of the Weibull distribution (see Figure 6).The distribution parameters are the
shape parameter m (which determines the distribution shape) and η (measure of the
parameter) (characteristic life). Once the distribution parameters are known from the
probability plot, a certain failure density level can be calculated.
The Weibull distribution
m
⎧ ⎫
⎛ t⎞
⎪ ⎪
⎜ ⎟
F()t =1– exp – (A.2)
⎨ ⎬
⎜ ⎟
η
⎝ ⎠
⎪ ⎪
⎩ ⎭
where
F(t) is the unreliability or cumulative distribution function;
η is the measure parameter (characteristic life);
m is the shape parameter (which determines the distribution shape);
-1
η is the time at which the fraction of surviving to original population becomes “e ”; as a
percentage this is nearly equal to 63,2 %. The value of m can be read from the slope
of the Weibull plot.
Y-axis is Ln(Ln(1/1-F(t))).
X-axis is Ln(t ).
bd
The method for calculating the lifetime of the certain failure density level is as follows:

62374-1 © IEC:2010 – 15 –
1/ m
t = η{}ln()1/()1– Failurelevel
(A.3)
atcertime failure
When the certain failure level is 0,1 %, t to 0,1 % is below:
1/ m
t = η{}ln()1/1–()0,1/100 (A.4)
0,1%
– 16 – 62374-1 © IEC:2010
Bibliography
[1] R.Tsu, J.W.McPherson and W.R.McKee "Leakage and Breakdown Reliability Issues
Associated with Low-k Dielectric Dual-Damascene Cu Process", proceeding IRPS, 2000,
p348
[2] G.H.Haase, E.Ogawa and J.W.McPherson, "Breakdown Characteristics of Interconnect
Dielectrics", proceeding IRPS, 2005, p466
[3] A.Ishi, et al, "Interface Engineering for High-Reliable 65nm-Node Cu/ULK(k=2.6)
Interconnect Integration", IITC, 2005,
[4] T.Yoshie, et al, "TDDB degradation Analysis Using Ea of Leakag
...