IEC TR 63571:2025

IEC TR 63571 ®
Edition 1.0 2025-05
TECHNICAL
REPORT
Semiconductor devices – Estimation method for lifetime conversion from
“PART” to “SYSTEM”
ICS 31.080.99  ISBN 978-2-8327-0415-8

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CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative reference . 6
3 Terms and definitions . 6
4 “SYSTEM”-level lifetime estimation . 8
4.1 General . 8
4.2 “SYSTEM”-level lifetime . 8
4.3 “UNIT”-level lifetime . 9
5 Applied case . 11
5.1 General . 11
5.2 MOS-TDDB . 11
5.3 Cu-VIA SM . 13
5.4 VIA EM . 14
Annex A (informative) Example of "UNIT"-level lifetime calculation results on specific
cases and supplementary notes . 15
A.1 Simplest calculation: MOS-TDDB . 15
A.2 Simplest calculation: Cu-VIA SM . 15
A.3 Simplest calculation: VIA EM . 17
A.4 BTI and HCI . 19
A.5 Method for converting time-varying stress conditions into constant conditions . 20
A.6 Example of redundancy except redundant parallel circuits . 22
Bibliography . 24

Figure 1 – Schematic view of “SYSTEM”, “UNIT” and “PART” . 7
Figure 2 – “SYSTEM”-level failure diagram, series chain of “UNITs” . 8
Figure 3 – Example of “UNIT”-level failure diagram . 10
Figure A.1 – Example of VIA SM failure diagram of double VIA rule . 16
Figure A.2 – Example of VIA SM redundant result by double VIAs rule . 17
Figure A.3 – VIA number dependency of cumulative distribution of the EM time-to-
failure. 18
Figure A.4 – Simulated delay time distribution and the test circuit model . 20
Figure A.5 – Redundancy effect of memory ECC . 23

Table A.1 – Example of operation condition. 21

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
ESTIMATION METHOD FOR LIFETIME
CONVERSION FROM “PART” TO “SYSTEM”

FOREWORD
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IEC TR 63571 has been prepared by IEC technical committee 47: Semiconductor devices. It is
a Technical Report.
The text of this Technical Report is based on the following documents:
Draft Report on voting
47/2904/DTR 47/2921/RVDTR
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this Technical Report is English.

– 4 – IEC TR 63571:2025 © IEC 2025
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
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The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn, or
• revised.
INTRODUCTION
In the case of large scale integration (LSI) development, “PART” (transistor, dielectric, metal,
etc.)-level lifetimes are evaluated by a test element group (TEG) at the wafer development
phase, and LSI is designed according to the design manual that is confirmed “PART”-level
lifetimes.
In general, circuits are different between TEG and LSI. When the LSI circuit becomes larger
without redundancy, the risk of failure becomes larger. It is important to design LSI circuits with
the recognition of the scale differences between LSI and TEG in addition to the consideration
of the “PART”-level lifetime.
NOTE In this document, the capitalized words SYSTEM, UNIT, and PART are used with quite a narrow meaning to
distinguish them from the ordinary usage of the words; refer to 3.1, 3.2, 3.3 for details.

– 6 – IEC TR 63571:2025 © IEC 2025
SEMICONDUCTOR DEVICES –
ESTIMATION METHOD FOR LIFETIME
CONVERSION FROM “PART” TO “SYSTEM”

1 Scope
This document describes a method to calculate “SYSTEM”-level lifetime from “PART”-level
lifetime. It presents a general mathematical theory and simple calculation examples for
educational purposes. Of the elements related to “SYSTEM”-level lifetime, software-related
elements such as diagnostics are outside the scope of this document.
2 Normative reference
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
websites:
• IEC Electromedical: http://www.electropedia.org/
• ISO Online browsing platform: http://www.iso.org/obp
3.1
SYSTEM
component grouped by the functionality in a product, or the product itself
3.2
UNIT
unit that is one of the functions that constitutes the “SYSTEM” in which failure directly causes
system failure
3.3
PART
element that constitutes the “UNIT” and which includes primary components such as circuit
materials, structural materials, or a combination of them, for example, gate dielectric, wire, VIA,
memory cell, and so on
Note 1 to entry: Figure 1 shows the schematic view of the “SYSTEM”, “UNIT” and “PART”. In Figure 1, the “SYSTEM”
is LSI chip. The LSI chip has multiple functions that are indispensable to drive the "SYSTEM". Those functions are
called "UNITs" in this document. And "UNIT" consists of some “PARTs” that are dielectric, wires, VIAs, and so on.

Key
“SYSTEM”
“UNIT”
“PART”
Figure 1 – Schematic view of “SYSTEM”, “UNIT” and “PART”
3.4
metal-oxide-semiconductor
MOS
device that has a three-layer structure of gate electrode, oxide film, and semiconductor
3.5
time-dependent dielectric breakdown
TDDB
failure phenomena of dielectric breakdown as a result of long-term application of a relatively
low electric field
3.6
bias temperature instability
BTI
transistor characteristic shift induced by gate voltage, due to dangling bonds generated at the
interface between the silicon substrate and the gate dielectric
3.7
hot carrier injection
HCI
transistor characteristic shift caused by hot carriers induced by the voltage between source and
drain
3.8
stress migration
SM
failure phenomena of the interconnects, which is caused by thermal stress
3.9
VIA
junction element that connects wires between the upper layer and lower layer
3.10
VIA connection
connection of wires between the upper layer and lower layer, which consists of a single VIA or
multiple VIAs
– 8 – IEC TR 63571:2025 © IEC 2025
3.11
electromigration
EM
failure phenomenon of the interconnects, which is caused by the current flow
3.12
lifetime
time from a period such as after shipment until the cumulative failure rate reaches a user-
defined value such as 0,1 %.
4 “SYSTEM”-level lifetime estimation
4.1 General
This document focuses on the “SYSTEM”-level lifetime derived from the failure mechanisms
that can be distinguished from failure and non-failure by “PART”-level. That is, in this document,
“PART” or “UNIT” is defined properly according to the definitions above. For example, the failure
mechanism such TDDB, SM, EM and the materials associated with those failure mechanisms
are “PART” themselves. On the other hand, in the case of BTI and HCI degradation, MOS in a
logical circuit is not defined as “PART”, excluding when the characteristic shift obviously causes
“SYSTEM” or “UNIT” failure.
In general, the “SYSTEM”-level lifetime, “UNIT”-level lifetime and “PART”-level lifetime are
derived from the cumulative distribution inverse function of the time-to-failure.
4.2 “SYSTEM”-level lifetime
From the definition of “UNIT” in 3.2, “UNIT” failure directly causes the “SYSTEM” failure, so
“SYSTEM”-level failure diagram is uniquely described by series chain of “UNITs” as Figure 2.
The “SYSTEM”-level cumulative distribution function of the time-to-failure, F (t) is
SYSTEM
described by the “UNIT”-level cumulative distribution function of the time-to-failure, F (t), as
UNIT
shown in Formula (1) and Formula (2). These formulas mean that the non-failure “SYSTEM”
has no failure “UNIT”. If the number of “UNITs” increases, F (t) becomes larger. It means
SYSTEM
that the “SYSTEM”-level lifetime becomes shorter as the number of “UNITs” increases.

Key
UNIT i-th “UNIT” in the “SYSTEM”
i
m Total number of “UNITs” that consist of the “SYSTEM”.
Figure 2 – “SYSTEM”-level failure diagram, series chain of “UNITs”
m
11−=F t − Ft (1)
() ()
( )
SYSTEM ∏ UNIT
i=1 i
m
F (t)=11−− Ft() (2)
SYSTEM ∏ ( UNIT )
i=1
i
where
t is the time starting from the completion of the shipping test;
m is the total number of “UNITs” in the “SYSTEM”;
F (t) is the “SYSTEM”-level cumulative distribution function of the time-to-failure;
SYSTEM
Ft is the i-th “UNIT” cumulative distribution function of the time-to-failure.
()
UNIT
i
4.3 “UNIT”-level lifetime
Figure 3 a) shows one of the simplest failure diagrams of "UNIT" that has no redundancy in the
circuit, that is, the series chain of “PARTs”. Its cumulative distribution function of the time-to-
failure, F (t) is described by the “PART”-level cumulative distribution function of the time-to-
UNIT
failure, F (t), as shown in Formula (3) and Formula (4). These formulas have the same
PART
meaning as Formula (1) and Formula (2).
N
11−=F (t) − F (t) (3)
UNIT ∏ ( PART )
i=1 i
N
F t=11−− F t (4)
() ()
( )
UNIT ∏ PART
i=1 i
where
t is the time starting from the completion of the shipping test;
N is the total number of “PARTs” that consist of the “UNIT”;
F (t) is the “UNIT”-level cumulative distribution function of the time-to-failure;
UNIT
Ft is the i-th “PART” cumulative distribution function of the time-to-failure.
()
PART
i
On the other hand in a real circuit, the redundancy is often added, especially units with large
scale circuit (e.g., large-size memories), units that have important functions (e.g., functions
related to safety). In this case, the failure of one “PART” does not always cause the “UNIT”
failure. There are multiple redundancy methods, such as circuit design and software. Figure 3
b) shows an example of a "UNIT"-level failure diagram consisting of the simplest redundant
circuit, a redundant parallel circuit. In this case, the “UNIT” will only fail when all “PARTs” have
failed. F (t) is described by the “PART”-level cumulative distribution function of the time-to-
UNIT
failure, F (t) as shown in Formula (5). If the number of “PARTs”, that is parallel numbers,
PART
increases, F (t) becomes smaller. It means that the “UNIT”-level lifetime becomes longer as
UNIT
the number of “PARTs” increases.
N
F t = F t (5)
() ()
∏
UNIT PART
i=1 i
In an actual parallel circuit, a series chain is often parallelized, not just a parallel “PART”. In
that case, the “UNIT”-level failure diagram is described in Figure 3 c), that is, the combination
of Figure 3 a) and Figure 3 b). In that case, the formula F (t) can be expressed by
UNIT
Formula (6).
– 10 – IEC TR 63571:2025 © IEC 2025
nn
F (t)= 11−− F (t)
(6)
UNIT ∏∏ ( PART )
{ }
k 11l kl,
where
n is the total parallel number of chains;
is the total number of “PARTs” in each chain;
n
Ft is the l-th “PART” cumulative distribution function of the time-to-failure.
()
PART
kl,
Formula (6) includes the meanings of both Formula (4) and Formula (5). The “UNIT”-level
lifetime becomes shorter when one series chain becomes longer, and conversely, it becomes
longer when the number of parallels increases.
NOTE Though the lifetime of the “UNIT” is improved by increasing the number of parallel circuits, the cost of the
chip increases. In general, redundancy is a trade-off between cost or performance, it is mainly implemented to the
"UNIT" that is important or severe in terms of reliability.

(a) – “UNIT” with no redundancy, series chain of “PARTs”

(b) – “UNIT” with simplest redundancy, parallel chain of “PARTs”

(c) – A series of chains lined up in parallel
Key
PART i-th “PART” in the “SYSTEM”
i
PART l-th “PART” in the 𝑘𝑘-th chain in the “SYSTEM”
k,l
Figure 3 – Example of “UNIT”-level failure diagram
==
5 Applied case
5.1 General
In general, "SYSTEM"- and “UNIT”-level lifetime depends on the "PART”-level lifetime, so they
are determined by the mission profile, the initial characteristics of the device, the operating
frequency, the operating duty, and the self-heat generated by them and so on. At the time of
publication of this document, it is difficult to accurately estimate them in a realistic period when
LSI products are released, even using simulation.
Therefore, it is important to simplify the calculation by limiting the calculation target to the
important “UNIT” where the operation is expected to be particularly severe in terms of reliability
or which has important function. “UNIT”-level lifetime is also most strongly affected by the failure
mechanism with the shortest lifetime among multiple failure mechanisms. It is also important to
calculate the lifetime separately fo
...