IEC 62951-9:2022

IEC 62951-9 ®
Edition 1.0 2022-12
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Flexible and stretchable semiconductor devices –
Part 9: Performance testing methods of one transistor and one resistor (1T1R)
resistive memory cells
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IEC 62951-9 ®
Edition 1.0 2022-12
INTERNATIONAL
STANDARD
colour
inside
Semiconductor devices – Flexible and stretchable semiconductor devices –

Part 9: Performance testing methods of one transistor and one resistor (1T1R)

resistive memory cells
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.99 ISBN 978-2-8322-6222-1

– 2 – IEC 62951-9:2022 © IEC 2022
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Device under testing (DUT) . 7
5 Test method . 8
5.1 General . 8
5.2 Test equipment and tools . 8
5.2.1 General . 8
5.2.2 Read . 9
5.2.3 Forming . 10
5.2.4 SET programming . 11
5.2.5 RESET programming . 12
5.2.6 Endurance . 14
5.2.7 Retention . 16
5.3 Test report . 17
Bibliography . 18

Figure 1 – 1T1R resistive memory cell . 8
Figure 2 – Block diagram of the measurement setup of 1T1R resistive memory cells . 9
Figure 3 – Read operation of 1T1R resistive memory cell . 9
Figure 4 – Cumulative probability distribution of HRS and LRS of 1T1R resistive
memory cells . 10
Figure 5 – Forming operation of 1T1R resistive memory cell . 11
Figure 6 – Simulation test flow chart of the forming process . 11
Figure 7 – SET operation of 1T1R resistive memory cell . 12
Figure 8 – Simulation test flow chart of the SET operation of 1T1R resistive
memory cell . 12
Figure 9 – RESET operation of 1T1R resistive memory cell . 13
Figure 10 – Simulation test flow chart of the RESET operation of 1T1R resistive
memory cell . 13
Figure 11 – Cumulative resistance distribution of 1T1R resistive memory . 14
Figure 12 – Simulation test flow chart of the endurance test of 1T1R resistive
memory cell . 15
Figure 13 – Exemplary endurance data of a 1T1R resistive memory cell . 15
Figure 14 – Simulation test flow chart of retention property of 1T1R resistive
memory cells . 16
Figure 15 – Exemplary retention characteristics of 1T1R resistive memory cells . 16

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES – FLEXIBLE AND
STRETCHABLE SEMICONDUCTOR DEVICES –

Part 9: Performance testing methods of one transistor
and one resistor (1T1R) resistive memory cells

FOREWORD
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IEC 62951-9 has been prepared by IEC technical committee 47: Semiconductor devices. It is
an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2781/FDIS 47/2791/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

– 4 – IEC 62951-9:2022 © IEC 2022
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications.
A list of all parts in the IEC 62951 series, published under the general title Semiconductor
devices – Flexible and stretchable semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The "colour inside" logo on the cover page of this document indicates that it
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SEMICONDUCTOR DEVICES – FLEXIBLE AND
STRETCHABLE SEMICONDUCTOR DEVICES –

Part 9: Performance testing methods of one transistor
and one resistor (1T1R) resistive memory cells

1 Scope
This part of IEC 62951 specifies the test methods for evaluating the performance of unipolar-
type one transistor one resistor (1T1R) resistive memory cells. The performance test methods
in this document include read, forming, SET, RESET, endurance and retention. This document
is applicable to flexible devices as well as rigid resistive memory devices without any limitations
prone to device technology and size.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purpose of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
programming transistor
semiconductor device used to amplify, limit or switch electronic signals and electrical power
3.2
source voltage
V
S
bias applied to the source terminal of the programming transistor

3.3
gate voltage
V
G
bias applied to the gate terminal of the programming transistor
3.4
drain voltage
V
D
bias applied to the drain terminal of the programming transistor
3.5
resistive memory
two terminal device, based on reversible formation and rupture of filament within active layer,
defining low and high resistance states, respectively

– 6 – IEC 62951-9:2022 © IEC 2022
3.6
forming voltage
V
Form
high voltage applied across the active layer to induce defects within the
...