Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect

IEC 63011-2:2018 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking.

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 2: Alignement de puces empilées à petits pas d'interconnexion

L'IEC 63011-2:2018 donne des spécifications d'alignement initial et de maintien d'alignement entre plusieurs circuits intégrés empilés pendant le processus de liaison de puces. Ces spécifications définissent les clés d'alignement et les procédures de fonctionnement de ces clés. Ces spécifications s'appliquent uniquement si une méthode de couplage électrique d'alignement de puces les unes sur les autres est utilisée dans l'empilement des puces.

General Information

Status
Published
Publication Date
27-Nov-2018
Technical Committee
Drafting Committee
Current Stage
PPUB - Publication issued
Start Date
28-Nov-2018
Completion Date
14-Dec-2018
Ref Project

Overview

IEC 63011-2:2018 is an international standard published by the International Electrotechnical Commission (IEC) that addresses the alignment of stacked dies in three-dimensional (3D) integrated circuits using fine pitch interconnect technology. Specifically, this standard provides detailed specifications for the initial alignment and ongoing alignment maintenance of multiple stacked integrated circuits during the die bonding process. It focuses on scenarios where die-to-die alignment is achieved through electrical coupling methods rather than traditional optical or mechanical systems. Ensuring precise alignment is critical for the proper electrical functionality and mechanical integrity of 3D integrated circuits, which are increasingly important in advanced electronics and semiconductor applications.

Key Topics

  • Initial Die Stacking Alignment
    The standard outlines procedures for optical-based initial alignment of dies during stacking. It uses alignment keys-specialized patterns integrated on the dies-which serve as references for positioning. The image of the lower die’s alignment keys is stored and compared with those of the upper die during the alignment process, ensuring fine positional accuracy.

  • Alignment Maintenance During Bonding
    After placing the upper die on the lower one, the bonding process involves thermal and mechanical stresses, posing a risk of misalignment. IEC 63011-2 specifies how to maintain alignment during this stage through real-time monitoring using electrical coupling methods, such as capacitive or inductive signals derived from the interconnects. These electrical signals act as feedback to detect and correct misalignments dynamically in the bonder apparatus.

  • Alignment Measurement After Stacking
    Once stacking and bonding complete, the standard provides methods for assessing final alignment. This assessment helps verify that vertical interconnects and fine pitch wiring meet the accuracy and functional requirements necessary for reliable device performance.

  • Alignment Keys and Operating Procedures
    Defined within this standard are various designs and dimensions for alignment keys optimized for electrical coupling sensing. These include mesh-type and conjugate detectors sensitive to misalignments in both X and Y directions. The operating procedures for using these keys ensure compatibility with die bonding machines and measurement tools.

Applications

  • Three-Dimensional Integrated Circuits (3D ICs)
    IEC 63011-2 is essential for manufacturers developing 3D ICs where multiple semiconductor dies are vertically stacked with through-silicon vias (TSVs). These technologies enable improvements in performance, density, and functionality of chips without shrinking feature sizes. Precise alignment is crucial for ensuring effective electrical coupling and minimizing defects.

  • Semiconductor Die Bonding Equipment
    Bonders equipped with electrical coupling capabilities utilize this standard to refine alignment accuracy, allowing for improved yield and reduced failure rates during assembly. This is particularly valuable in high-volume production environments focusing on next-generation semiconductor packaging.

  • Advanced Package Integration
    The standard supports fine pitch interconnect technology used in heterogeneous integration where different types of semiconductor devices are stacked, such as logic, memory, and sensors, requiring intricate alignment and interconnect precision.

Related Standards

  • IEC 63011-1: Integrated Circuits – Three Dimensional Integrated Circuits – Part 1: Terminology
    This complementary standard defines terms and basic concepts used in 3D ICs and serves as a foundational reference for understanding IEC 63011-2.

  • Standards on Die Bonding and Semiconductor Packaging
    Other relevant international standards govern die attach processes, package assembly, and testing which work alongside IEC 63011-2 to ensure comprehensive quality management in 3D IC manufacturing.

  • Electrical Signal Coupling Technical Specifications
    Standards describing capacitive and inductive coupling technologies are pertinent for implementing the electrical alignment methods recommended in IEC 63011-2.


By adhering to IEC 63011-2:2018, semiconductor manufacturers and equipment developers ensure high-precision alignment of stacked dies with fine pitch interconnects, enhancing the reliability and performance of three-dimensional integrated circuits. This standard is a vital resource for engineers, production managers, and quality control specialists focusing on state-of-the-art semiconductor packaging technologies.

Standard
IEC 63011-2:2018 - Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect
English and French language
28 pages
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Frequently Asked Questions

IEC 63011-2:2018 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect". This standard covers: IEC 63011-2:2018 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking.

IEC 63011-2:2018 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking.

IEC 63011-2:2018 is classified under the following ICS (International Classification for Standards) categories: 17.220.20 - Measurement of electrical and magnetic quantities; 31.200 - Integrated circuits. Microelectronics. The ICS classification helps identify the subject area and facilitates finding related standards.

You can purchase IEC 63011-2:2018 directly from iTeh Standards. The document is available in PDF format and is delivered instantly after payment. Add the standard to your cart and complete the secure checkout process. iTeh Standards is an authorized distributor of IEC standards.

Standards Content (Sample)


IEC 63011-2 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –
Part 2: Alignment of stacked dies having fine pitch interconnect

Circuits intégrés – Circuits intégrés tridimensionnels –
Partie 2: Alignement de puces empilées à petits pas d'interconnexion

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IEC 63011-2 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –

Part 2: Alignment of stacked dies having fine pitch interconnect

Circuits intégrés – Circuits intégrés tridimensionnels –

Partie 2: Alignement de puces empilées à petits pas d'interconnexion

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.200 ISBN 978-2-8322-6291-7

– 2 – IEC 63011-2:2018  IEC 2018
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Die alignment during three dimensional integration . 7
4.1 Alignment during stacking . 7
4.2 Alignment maintenance during die bonding . 7
4.3 Alignment measurement after die stacking . 9
5 Alignment procedure . 9
5.1 Initial die stacking . 9
5.2 Final alignment . 9
5.3 Assessment of alignment . 9
Annex A (informative) Alignment examples . 10
A.1 Alignment maintenance using capacitive coupling . 10
A.2 Alignment maintenance using inductive coupling . 12
A.3 Alignment measurement after stacking is completed . 13
Bibliography . 14

Figure 1 – Procedure of alignment of dies during die stacking . 7
Figure 2 – Misalignment sensing and compensation by aligner . 8
Figure 3 – Adjustment for translational misalignment . 8
Figure 4 – Final alignment of vertical interconnects between the adjacent layers of dies . 9
Figure A.1 – Capacitive coupling between two misaligned wires with different widths. 10
Figure A.2 – Relative capacitance with misalign and metal width . 11
Figure A.3 – Multiple narrow wires . 11
Figure A.4 – 2-D alignment key in (top) mesh type and (bottom) conjugate X- and Y-
direction detectors . 11
Figure A.5 – S roll-off with misalignment (M) for at H = 10 µm, ratio = 0,1, f = 0,01
GHz, and T = 0,5 µm . 12
Figure A.6 – Alignment keys for inductive coupling alignment detector when the
electricity in the upper die is (left) available and (right) unavailable . 13
Figure A.7 – Alignment measurement keys of (top) aligned and (below) misaligned
stacking . 13

Table A.1 – Alignment key dimensions . 12

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 2: Alignment of stacked dies having fine pitch interconnect

FOREWORD
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patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 63011-2 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47A/1061/FDIS 47A/1065/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – IEC 63011-2:2018  IEC 2018
A list of all parts in the IEC 63011 series, published under the general title Integrated circuits
– Three dimensional integrated circuits, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
INTRODUCTION
Three-dimensional (3-D) integration of integrated circuits using through-silicon via (TSV)
technology is an innovative solution to simultaneously achieve a greater performance, an
improved versatility and a higher density of integrated circuits without miniaturization of
feature sizes on a die. Die alignment during the die bonding is the key enabler of the fine
pitch 3-D wiring between vertically stacked dies for proper physical contact. Maintenance of
the alignment during the bonding process and afterward is as important as the precise overlap
prior to die bonding. This standard describes a method of initial alignment and maintenance of
alignment throughout the die bonding process that can be involved with mechanical shaking.
The initial alignment is performed using the optical means. During the maintenance period,
however, relative amount of the misalignment is converted to an electrical signal for on-the-fly
alignment monitoring without the visual image.

– 6 – IEC 63011-2:2018  IEC 2018
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 2: Alignment of stacked dies having fine pitch interconnect

1 Scope
This part of IEC 63011 provides specifications of initial alignment and alignment maintenance
between multiple stacked integrated circuits during the die bonding process. These
specifications define the alignment keys and operating procedures of the keys. These
specifications apply only if electrical coupling method of die-to-die alignment is used in the die
stacking.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
IEC 63011-1, Integrated circuits − Three dimensional Integrated Circuits – Part 1:
Terminology
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 63011-1 apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
die bonding
assembly step to adhere physically or chemically a die to another
3.2
bonder
apparatus performing die bonding
3.3
signal generator
apparatus generating electrical signals
3.4
alignment key
apparatus to monitor or adjust the alignment of the overlaid dies
3.5
aligner
apparatus to perform the alignment of the overlaid dies

4 Die alignment during three dimensional integration
4.1 Alignment during stacking
Once the upper die covers the bottom one, the patterns including align key on the bottom die
are not seen any longer. Therefore, the image of the bottom die is stored in the memory. As
the upper die is moved above the bottom die, the patterns on the upper die are compared with
the stored patterns to be precisely aligned. The procedure is illustrated in Figure 1. The cross-
patters indicate alignment keys, and they are placed at the same location on every die. The
alignment keys are also used as a positioning reference for all other patterns on the die. The
position of patters on the upper die is compared with memorized images of the lower die
because the pattern on the lower die is covered by the upper one and no longer seen by
general alignment tools.
IEC IEC
Figure 1 – Procedure of alignment of dies during die stacking
4.2 Alignment maintenance during die bonding
After the upper die is placed on top of the bottom one, the bonding process is proceeded to
give the permanent physical contact on the bonder as shown in Figure 2. The bonding
process is involved with thermal and mechanical agitation to provide the adhesive contact
between the TSV and micro bump. Physical agitation destroys the alignment. The image of
the bottom die is not observed by optical microscope using visible light. Although the infrared
light penetrates the solid to the limited depth, the resolution deteriorates drastically as the
thickness of the top die increases. In addition, the metallic piece of die holder blocks images
in the infrared microscope. Another alignment sensor is desired to monitor the deviation from
the perfect alignment using the electrical signal. The misalign information is, then, fed back to
the aligner to compensate the misalignment. The aligner shall be capable of recovering the
translational misalignment along the two principle axes parallel to the die surface, and
rotational misalignment perpendicular to the die surface. The signal generator provides the
source signal to be supplied to the die through the transmitter. The receiver collects the
transmitted signal that is distorted by the amount of misalignment as depicted by a curve in
Figure 2 below.
– 8 – IEC 63011-2:2018  IEC 2018
Signal
Misalignment
Aligner
RX
TX
Signal
generator
Bonder
IEC
Figure 2 – Misalignment sensing and compensation by aligner
In order to convert the physical misalignment to the electrical signal during the die bonding
step, the alignment keys shall sense the alignment when they are not in contact. The
electrical or magnetic coupling is an efficient medium of alignment information. Figure 3
illustrates a possible example of alignment key deployment in the stacked two dies. The
intensity of the received signal becomes strong when active alignment keys are placed on the
facing surfaces of the two stacked dies, i.e. bottom of the upper die and top of the lower die.
Both transmitter and receiver are located on the bottom die and the upper die does not have
any active device so that the upper die does not need to have electricity. The power is
provided through the fixed bottom die and the top floated upper die provides passive bridges.
Then, the upper die is free to move for alignment recovery and bonding. The signal is emitted
by the alignment key connected to the transmitter on bottom die, and it is coupled by left part
of the bridge on bottom surface of the upper die. The signal travels to the right half of the
bridge and couples back to the transponder that is connected to the receiver on the top
surface of the bottom die. The attenuation of the received signal from the transmitted one is
determined by the distance and misalignment of align keys. If the upper die shakes constantly,
the amount of attenuation tells which direction is for the perfect alignment. The bridge on the
upper die is exposed to the ambient, but the transponder on bottom die is covered with thin
dielectric film to avoid direct contact between the alignment keys and to maximize the
received signal as well. Clauses A.1 and A.2 show an example of the shape of a typical
sensor element and the strength of coupling to misalignment.
IEC
Figure 3 – Adjustment for translational misalignment

4.3 Alignment measurement after die stacking
The alignment of the two dies may be disrupted by the mechanical or thermal agitation during
the die bonding process. The typical cross-section view of the stacked dies with misalignment
in the vertical interconnects is shown in Figure 4. After the upper die is completely bonded
onto the lower die mechanically and electrically, the alignment is once again measured by an
appropriate instrument. The quality of the final alignment of the three dimensional integrated
circuits is delivered in the form of amount of misalignment. An example of a structure for
detecting misalignment after bonding is shown in Annex A.3.
IEC
Figure 4 – Final alignment of vertical interconnects between
the adjacent layers of dies
5 Alignment procedure
5.1 Initial die stacking
Place the bottom die and store the image of alignment key in the memory before the top die is
brought above the bottom one. Then, compare the image of alignment key on the top die and
that in the memory to make the initial alignment. The accuracy of the alignment shall be better
than a half of spacing of alignment unit in the coupling alignment keys.
5.2 Final alignment
Turn on the electrical alignment key to track the alignment with electrical signal during the
subsequent bonding process. Shake the upper die in X direction to get the best alignment
along that direction using one of coupling alignment methods. And repeat the alignment check
along Y direction. Rotate the upper die around the axis perpendicular to the die surface to
compensate the rotational misalignment. Repeat translational and rotational alignment until
the misalignment is small enough.
5.3 Assessment of alignment
Whenever a layer of die is stacked, the quality of final alignment shall be measured using an
appropriate method, e.g. resistance measurement as described in IEC 63011-3.

– 10 – IEC 63011-2:2018  IEC 2018
Annex A
(informative)
Alignment examples
A.1 Alignment maintenance using capacitive coupling
Capacitive coupling between the two wires separated vertically by ‘H’, and misaligned
horizontally by ‘M’ is modelled in Figure A.1. Two pairs of wires with different aspect ratio of
the cross-section, W/T, are shown in Figure A.1 below.
IEC
Key
M misalignment in horizontal
H wafer space in vertical
W1 width of narrow wire
W2 width of wide wire
T thickness of unit alignment key
W1 and W2 to be discriminated.
Figure A.1 – Capacitive coupling between
two misaligned wires with different widths
The relative attenuation of capacitance by the misalignment is significant when wires are
narrow as shown on the left in Figure A.2. However, the absolute intensity of capacitive
coupling becomes strong when the wires are wide. It is described on the right in Figure A.2
below.
IEC
Figure A.2 – Relative capacitance with misalign and metal width
In order to have both coupling strength and alignment sensitivity, multiple narrow wires are
necessary as illustrated in Figure A.3.
IEC
Key
H wafer space in vertical
W width of wire
T thickness of unit alignment key
Figure A.3 – Multiple narrow wires
Using the analysis of the capacitive coupling, the two types of alignment keys can be used as
illustrated in Figure A.4.
IEC
Figure A.4 – 2-D alignment key in (top) mesh type
and (bottom) conjugate X- and Y-direction detectors

– 12 – IEC 63011-2:2018  IEC 2018
The attenuation of the received signal is function of the vertical separation of coupling pairs
(H), W/O ratio, the number wires (N) and the dimension of the alignment keys. Figure A.5
shows the field simulation results of conjugate align keys with different dimensions.
IEC
Figure A.5 – S roll-off with misalignment (M) for at H = 10 µm,
ratio = 0,1, f = 0,01 GHz, and T = 0,5 µm
For proper functionality of the alignment sensor in different technologies the following
parameters that are listed in the Table A.1 are desired to be specified. In some cases,
different classes of dimensions of alignment keys may be specified.
Table A.1 – Alignment key dimensions
Parameter Name Class-1 Class-2
Side length of unit alignment key(L)
Thickness of unit alignment key(T)
Wafer space (H)
Ratio of W/O (ratio)
Number of holes (N)
Frequency (f)
A.2
...

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