IEC 63011-2:2018

IEC 63011-2 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –
Part 2: Alignment of stacked dies having fine pitch interconnect

Circuits intégrés – Circuits intégrés tridimensionnels –
Partie 2: Alignement de puces empilées à petits pas d'interconnexion

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IEC 63011-2 ®
Edition 1.0 2018-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Integrated circuits – Three dimensional integrated circuits –

Part 2: Alignment of stacked dies having fine pitch interconnect

Circuits intégrés – Circuits intégrés tridimensionnels –

Partie 2: Alignement de puces empilées à petits pas d'interconnexion

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.200 ISBN 978-2-8322-6291-7

– 2 – IEC 63011-2:2018  IEC 2018
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Die alignment during three dimensional integration . 7
4.1 Alignment during stacking . 7
4.2 Alignment maintenance during die bonding . 7
4.3 Alignment measurement after die stacking . 9
5 Alignment procedure . 9
5.1 Initial die stacking . 9
5.2 Final alignment . 9
5.3 Assessment of alignment . 9
Annex A (informative) Alignment examples . 10
A.1 Alignment maintenance using capacitive coupling . 10
A.2 Alignment maintenance using inductive coupling . 12
A.3 Alignment measurement after stacking is completed . 13
Bibliography . 14

Figure 1 – Procedure of alignment of dies during die stacking . 7
Figure 2 – Misalignment sensing and compensation by aligner . 8
Figure 3 – Adjustment for translational misalignment . 8
Figure 4 – Final alignment of vertical interconnects between the adjacent layers of dies . 9
Figure A.1 – Capacitive coupling between two misaligned wires with different widths. 10
Figure A.2 – Relative capacitance with misalign and metal width . 11
Figure A.3 – Multiple narrow wires . 11
Figure A.4 – 2-D alignment key in (top) mesh type and (bottom) conjugate X- and Y-
direction detectors . 11
Figure A.5 – S roll-off with misalignment (M) for at H = 10 µm, ratio = 0,1, f = 0,01
GHz, and T = 0,5 µm . 12
Figure A.6 – Alignment keys for inductive coupling alignment detector when the
electricity in the upper die is (left) available and (right) unavailable . 13
Figure A.7 – Alignment measurement keys of (top) aligned and (below) misaligned
stacking . 13

Table A.1 – Alignment key dimensions . 12

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
THREE DIMENSIONAL INTEGRATED CIRCUITS –

Part 2: Alignment of stacked dies having fine pitch interconnect

FOREWORD
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International Standard IEC 63011-2 has been prepared by subcommittee 47A: Integrated
circuits, of IEC technical committee 47: Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47A/1061/FDIS 47A/1065/RVD
Full information on the voting for the approval of this International Standard can be found in
the report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

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