IEC 60191-6-6:2001

IEC 60191-6-6 ®
Edition 1.0 2001-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-6: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Design guide for fine pitch land grid
array (FLGA)
Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-6: Règles générales pour la préparation des dessins d'encombrement
des dispositifs à semiconducteurs à montage en surface – Guide de conception
des dispositifs FLGA
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IEC 60191-6-6 ®
Edition 1.0 2001-03
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –

Part 6-6: General rules for the preparation of outline drawings of surface

mounted semiconductor device packages – Design guide for fine pitch land grid

array (FLGA)
Normalisation mécanique des dispositifs à semiconducteurs –

Partie 6-6: Règles générales pour la préparation des dessins d'encombrement

des dispositifs à semiconducteurs à montage en surface – Guide de conception

des dispositifs FLGA
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX M
ICS 31.080.01 ISBN 978-2-83220-590-7

– 2 – 60191-6-6 © IEC:2001
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-6: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA)

FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in
addition to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical
committees; any IEC National Committee interested in the subject dealt with may participate in this preparatory
work, International, governmental and non-governmental organizations liaising with the IEC also participate in this
preparation. The IEC collaborates closely with the International Organization for Standardization (ISO) in
accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form of
standards, technical specifications, technical reports or guides and they are accepted by the National Committees
in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any divergence
between the IEC Standard and the corresponding national or regional standard shall be clearly indicated in the
latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject of
patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-6 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
This bilingual version (2013-01) corresponds to the monolingual English version, published in
2001-03.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/404/FDIS 47D/421/RVD
Full information on the voting for the approval of this standard can be found in the report on voting
indicated in the above table.
The French version of this standard has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 3.
The committee has decided that the contents of this publication will remain unchanged until 2003.
At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
60191-6-6 © IEC:2001 – 3 –
INTRODUCTION
The demand for area array style packages exists because of the multi-functions and high
performance of electrical equipment. The objective of this design guide is to standardize outlines
and to get interchangeability of FLGA packages. The terminal pitch and package outlines of these
fine-pitch array packages are smaller than those of LGA packages.

– 4 – 60191-6-6 © IEC:2001
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-6: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA)

1 Scope
This part of IEC 60191 provides common outline drawings and dimensions for all types of
structures and composed materials of fine-pitch land grid array (hereinafter called FLGA) whose
terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is square.
2 Normative references
The following normative documents contain provisions which, through reference in this text,
constitute provisions of this part of IEC 60191. For dated references, subsequent amendments to,
or revisions of, any of these publications do not apply. However, parties to agreements based on
this part of IEC 60191 are encouraged to investigate the possibility of applying the most recent
editions of the normative documents indicated below. For undated references, the latest edition
of the normative document referred to applies. Members of IEC and ISO maintain registers of
currently valid International Standards.
IEC 60191 (all parts), Mechanical standardization of semiconductor devices
3 Definitions
For the purposes of this part of IEC 60191, the following definitions, as well as those given in the
other parts of this standard, apply.
3.1
flanged type
type whose package body size (body length and width) consists of its own flange composed
around the encapsulation or lid
3.2
type of real chip size
type whose package body size (body length and width) consists of an encapsulation around the
real chip only
3.3
FLGA
packages with metal lands or metal bumps of which the terminal height is less than, or equal to,
100 µm, and whose terminal pitch is less than, or equal to, 0,80 mm, positioned in an array on the
base plane of the package as external terminals
This package structure makes it possible to surface-mount the packages to the printed circuit
board
60191-6-6 © IEC:2001 – 5 –
3.4
material designation
FLGA packages are classified according to the following two material designations:
3.4.1
plastic type (P-FLGA)
plastic-type classification is assigned to packages which consist of resin substrate as interposer
material (for example, glass-epoxy, poly-imid)
3.4.2
ceramic type (C-FLGA)
ceramic-type classification is assigned to packages which consist of ceramic substrate as
interposer material
– 6 – 60191-6-6 © IEC:2001
IEC  300/01
Design guide for
fine-pitch land grid array family

60191-6-6 © IEC:2001 – 7 –
NOTE 1 Zone of a visible index on the top surface.
NOTE 2 Datum A and B are the axes defined by the terminal positions indicated with datum targets.
NOTE 3 Primary datum S and seating plane to be defined by the method of least squares of spherical crowns of
terminals.
– 8 – 60191-6-6 © IEC:2001
Table 1 – Group 1: Dimensions appropriate to mounting and interchangeability
Limits to be observed Recommended values
Ref. for the dimensions Note
Min. Nom. Max.
mm
n X  1, 2
nD X  1
nE X
A  X A max. = 1,20, 1,70, 2,00 Includes heat slug
Includes package warpage and tilt
A  X A max. = 0,10
1 1
X X X At ceramic FLGA (C-FLGA)
∅b
Min. Nom. Max.
at e = 0,80 0,45 0,50 0,55
at e = 0,65 0,35 0,40 0,45
at e = 0,50 0,25 0,30 0,35
at e = 0,40 0,20 0,25 0,30
At plastic FLGA (P-FLGA)
Min. Nom. Max.
at e = 0,80 0,35 0,40 0,45
at e = 0,65 0,28 0,33 0,38
at e = 0,50 0,20 0,25 0,30
at e = 0,40 0,15 0,20 0,25
D X At flanged type
D = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0,
11,0, 12,0, 13,0, 14,0, 15,0, 16,0,
17,0, 18,0, 19,0, 20,0, 21,0
At type of real chip size
D = from 3,1 to 21,0 Dimension range shows nominal
value
E X At flanged type
E = 4,0, 5,0, 6,0, 7,0, 8,0, 9,0, 10,0,
11,0, 12,0, 13,0, 14,0, 15,0, 16,0,
17,0, 18,0, 19,0, 20,0, 21,0
At type of real chip size
E = from 3,1 to 21,0 Dimension range shows nominal
value
e X  e = 0,80, 0,65, 0,50, 0,40
v  X v = 0,15  Includes burrs
w  X at e = 0,80 w = 0,20
at e = 0,65 w = 0,20
at e = 0,50 w = 0,20
at e = 0,40 w = 0,15
x  X at e = 0,80 x = 0,08
at e = 0,65 x = 0,08
at e = 0,50 x = 0,05
at e = 0,40 x = 0,05
60191-6-6 © IEC:2001 – 9 –
Table 1 – (continued)
Limits to be observed Recommended values
Ref. for the dimensions Note
Min. Nom. Max.
mm
...