IEC 62258-1:2009

IEC 62258-1 ®
Edition 2.0 2009-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor die products –
Part 1: Procurement and use
Produits de puces de semiconducteurs –
Partie 1: Approvisionnement et utilisation

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by
any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or
IEC's member National Committee in the country of the requester.
If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,
please contact the address below or your local IEC member National Committee for further information.

Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite
ni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie
et les microfilms, sans l'accord écrit de la CEI ou du Comité national de la CEI du pays du demandeur.
Si vous avez des questions sur le copyright de la CEI ou si vous désirez obtenir des droits supplémentaires sur cette
publication, utilisez les coordonnées ci-après ou contactez le Comité national de la CEI de votre pays de résidence.

IEC Central Office
3, rue de Varembé
CH-1211 Geneva 20
Switzerland
Email: inmail@iec.ch
Web: www.iec.ch
About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.
ƒ Catalogue of IEC publications: www.iec.ch/searchpub
The IEC on-line Catalogue enables you to search by a variety of criteria (reference number, text, technical committee,…).
It also gives information on projects, withdrawn and replaced publications.
ƒ IEC Just Published: www.iec.ch/online_news/justpub
Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available
on-line and also by email.
ƒ Electropedia: www.electropedia.org
The world's leading online dictionary of electronic and electrical terms containing more than 20 000 terms and definitions
in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical
Vocabulary online.
ƒ Customer Service Centre: www.iec.ch/webstore/custserv
If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service
Centre FAQ or contact us:
Email: csc@iec.ch
Tel.: +41 22 919 02 11
Fax: +41 22 919 03 00
A propos de la CEI
La Commission Electrotechnique Internationale (CEI) est la première organisation mondiale qui élabore et publie des
normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.

A propos des publications CEI
Le contenu technique des publications de la CEI est constamment revu. Veuillez vous assurer que vous possédez
l’édition la plus récente, un corrigendum ou amendement peut avoir été publié.
ƒ Catalogue des publications de la CEI: www.iec.ch/searchpub/cur_fut-f.htm
Le Catalogue en-ligne de la CEI vous permet d’effectuer des recherches en utilisant différents critères (numéro de référence,
texte, comité d’études,…). Il donne aussi des informations sur les projets et les publications retirées ou remplacées.
ƒ Just Published CEI: www.iec.ch/online_news/justpub
Restez informé sur les nouvelles publications de la CEI. Just Published détaille deux fois par mois les nouvelles
publications parues. Disponible en-ligne et aussi par email.
ƒ Electropedia: www.electropedia.org
Le premier dictionnaire en ligne au monde de termes électroniques et électriques. Il contient plus de 20 000 termes et
définitions en anglais et en français, ainsi que les termes équivalents dans les langues additionnelles. Egalement appelé
Vocabulaire Electrotechnique International en ligne.
ƒ Service Clients: www.iec.ch/webstore/custserv/custserv_entry-f.htm
Si vous désirez nous donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du
Service clients ou contactez-nous:
Email: csc@iec.ch
Tél.: +41 22 919 02 11
Fax: +41 22 919 03 00
IEC 62258-1 ®
Edition 2.0 2009-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor die products –
Part 1: Procurement and use
Produits de puces de semiconducteurs –
Partie 1 : Approvisionnement et utilisation

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
X
CODE PRIX
ICS 31.080.99 ISBN 2-8318-1036-7
– 2 – 62258-1 © IEC:2009
CONTENTS
FOREWORD.5
INTRODUCTION.7
1 Scope.8
2 Normative references.8
3 Terms and definitions .9
3.1 Basic definitions .9
3.2 General terminology .10
3.3 Semiconductor manufacturing and interconnection terminology.12
4 General requirements .13
5 Data exchange .13
6 Requirements for all devices .14
6.1 Data package .14
6.1.1 General .14
6.1.2 Information source.14
6.1.3 Data version .14
6.1.4 Data exchange formats .14
6.2 Identity and source .14
6.2.1 General .14
6.2.2 Type number .14
6.2.3 Manufacturer .14
6.2.4 Supplier .14
6.2.5 Signature.14
6.3 Function .14
6.4 Physical characteristics .15
6.4.1 Semiconductor material .15
6.4.2 Technology.15
6.5 Ratings and limiting conditions.15
6.5.1 Power dissipation.15
6.5.2 Operating temperature .15
6.6 Connectivity.15
6.6.1 General .15
6.6.2 Terminal count.15
6.6.3 Terminal information .15
6.6.4 Permutability.16
6.7 Documentation .16
6.8 Form of supply.16
6.8.1 Physical form .16
6.8.2 Packing .16
6.9 Simulation and modelling .16
6.9.1 General .16
6.9.2 Electrical modelling and simulation.16
6.9.3 Thermal data and modelling.16
7 Requirements for bare die and wafers with or without connection structures .17
7.1 General .17
7.2 Identity .17
7.2.1 General .17

62258-1 © IEC:2009 – 3 –
7.2.2 Die name.17
7.2.3 Die version .17
7.3 Materials .17
7.3.1 Substrate material.17
7.3.2 Substrate connection .17
7.3.3 Backside detail .17
7.3.4 Passivation material.17
7.3.5 Metallisation .17
7.3.6 Terminal material.17
7.3.7 Terminal structure.18
7.3.8 Vias.18
7.4 Geometry .18
7.4.1 General .18
7.4.2 Units of measurement.18
7.4.3 Geometric view.18
7.4.4 Die size .18
7.4.5 Die thickness .18
7.4.6 Dimension tolerances .18
7.4.7 Geometric origin .18
7.4.8 Terminal shape and size .18
7.4.9 Die fiducials.19
7.4.10 Die picture .19
7.5 Wafer data .19
7.5.1 General .19
7.5.2 Wafer size .19
7.5.3 Wafer index .19
7.5.4 Wafer die count and step size .19
7.5.5 Wafer reticules .19
8 Minimally-packaged devices.19
8.1 General .19
8.2 Number of terminals .19
8.3 Terminal position .19
8.4 Terminal shape and size.20
8.5 Device size.20
8.6 Seated height .20
8.7 Encapsulation material.20
8.8 Moisture sensitivity .20
8.9 Package style code.20
8.10 Outline drawing.20
9 Quality, test and reliability .21
9.1 General .21
9.2 Outgoing quality level.21
9.2.1 Value.21
9.2.2 Description .21
9.3 Electrical parameters specified .21
9.4 Compliance to standards .21
9.5 Additional device screening .21
9.6 Product status .21
9.7 Testability features .21

– 4 – 62258-1 © IEC:2009
9.8 Additional test requirements.21
9.9 Reliability.22
9.9.1 Reliability estimate.22
9.9.2 Reliability calculation .22
10 Handling and packing .22
10.1 General requirements for all devices.22
10.1.1 General .22
10.1.2 Customer part number .22
10.1.3 Type number .23
10.1.4 Supplier .23
10.1.5 Manufacturer .23
10.1.6 Traceability.23
10.1.7 Quantity.23
10.1.8 ESD sensitivity.23
10.1.9 Requirements for environmental protection .23
10.2 Specific requirement for bare die or wafers – mask version .23
10.3 Specific requirement for wafers – wafer map.23
10.4 Special item requirements .23
10.4.1 General .23
10.4.2 Special protection requirements .24
10.4.3 Unencapsulated die warning label .24
10.4.4 Toxic material warning .24
10.4.5 Fragile components warning .24
10.4.6 ESD sensitivity warning.24
11 Storage .24
11.1 General .24
11.2 Storage duration and conditions.24
11.3 Long-term storage .24
11.4 Storage limitations .24
12 Assembly.25
12.1 General .25
12.2 Attach methods and materials.25
12.3 Bonding method and materials.25
12.4 Attachment limitations.25
12.4.1 General .25
12.4.2 Temperature/time profile.25
12.5 Process limitations .25
Annex A (informative) Terminology.26
Annex B (informative) Acronyms.36
Bibliography .43

62258-1 © IEC:2009 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DIE PRODUCTS –
Part 1: Procurement and use
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62258-1 has been prepared by IEC technical committee 47:
Semiconductor devices.
This second edition cancels and replaces the first edition published in 2005, and constitutes a
technical revision.
The main changes that have been introduced in this issue have been to ensure consistency
across all parts of the standard. The ordering of the subclauses, particularly in Clause 6, has
been changed to be more logical and the text of some of the requirements has been amended
to add requirements on further information as covered by IEC/TR 62258-4, IEC/TR 62258-7
and IEC/TR 62258-8. New requirements include information on permutability of terminals and
functional elements (6.6.4) and moisture sensitivity for partially encapsulated devices (8.8).

– 6 – 62258-1 © IEC:2009
The text of this standard is based on the following documents:
CDV Report on voting
47/1974/CDV 47/2004/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all the parts in the IEC 62258 series, under the general title Semiconductor die
products, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until the
maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
62258-1 © IEC:2009 – 7 –
INTRODUCTION
th
This standard is based on the work carried out in the ESPRIT 4 Framework project GOOD-
DIE which resulted in the publication of the ES59008 series of European specifications.
Organisations that helped prepare this document included the European IST ENCASIT project,
JEITA, JEDEC and ZVEI.
The structure of this International Standard as currently conceived is as follows:
Part 1: Procurement and use
Part 2: Exchange data formats
Part 3: Recommendations for good practice in handling, packing and storage (technical
report)
Part 4: Questionnaire for die users and suppliers (technical report)
Part 5: Requirements for information concerning electrical simulation
Part 6: Requirements for information concerning thermal simulation
Part 7: XML schema for data exchange (technical report)
Part 8: EXPRESS model schema for data exchange (technical report)
Further parts may be added as required.

– 8 – 62258-1 © IEC:2009
SEMICONDUCTOR DIE PRODUCTS –
Part 1: Procurement and use
1 Scope
This part of IEC 62258 has been developed to facilitate the production, supply and use of
semiconductor die products, including
• wafers,
• singulated bare die,
• die and wafers with attached connection structures,
• minimally or partially encapsulated die and wafers.
The standard defines the minimum requirements for the data that are needed to describe such
die products and is intended as an aid to the design of and procurement for assemblies
incorporating die products. It covers the requirements for data, including
• product identity
• product data
• die mechanical information
• test, quality, assembly and reliability information
• handling, shipping and storage information
It covers the specific requirements for the data that are needed to describe the geometrical
properties of die, their physical properties and the means of connection necessary for their use
in the development and manufacture of products. It also contains, in the annexes, a vocabulary
and list of common acronyms.
2 Normative references
The following referenced documents are indispensable for the application of this document. For
dated references, only the edition cited applies. For undated references, the latest edition of the
referenced document (including any amendments) applies.
IEC 60050 (all parts), International Electrotechnical Vocabulary
IEC 60191 (all parts), Mechanical standardization of semiconductor devices
IEC 60191-4:1999, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor device packages
Amendment 1 (2001)
Amendment 2 (2002)
IEC 61360-1, Standard data element types with associated classification scheme for electric
components – Part 1: Definitions – Principles and methods
IEC 62258-2, Semiconductor die products – Part 2: Exchange data formats
IEC/TR 62258-3, Semiconductor die products – Part 3: Recommendations for good practice in
handling, packing and storage
62258-1 © IEC:2009 – 9 –
IEC/TR 62258-4, Semiconductor die products – Part 4: Questionnaire for die users and
suppliers
IEC 62258-5, Semiconductor die products – Part 5: Requirements for information concerning
electrical simulation
IEC 62258-6, Semiconductor die products – Part 6: Requirements for information concerning
thermal simulation
IEC/TR 62258-7, Semiconductor die products – Part 7: XML schema for data exchange
IEC/TR 62258-8, Semiconductor die products – Part 8: EXPRESS model schema for data
exchange
ISO 14644-1:1999, Cleanrooms and associated controlled environments – Part 1: Classification
of air cleanliness
3 Terms and definitions
For the purpose of this document, the following terms and definitions are applicable. All the
terms and definitions defined here are in addition to the relevant terms and definitions that are
defined in IEC 60050 series . Additional terms and acronyms are given for information in
Annexes A and B.
3.1 Basic definitions
3.1.1
die (singular or plural)
separated piece(s) of semiconductor wafer that constitute a discrete semiconductor or whole
integrated circuit
3.1.2
wafer
slice or flat disc, either of semiconductor material or of such a material deposited on a
substrate, in which devices or circuits are simultaneously processed and which may be
subsequently separated into die
3.1.3
singulated die
individual and distinct die which have been separated from the wafer
3.1.4
singulation
die separation
separation of wafers into individual die devices, including sawing, scribing and dicing
3.1.5
bare die
unpackaged discrete semiconductor or integrated circuit with pads on the upper surface
suitable for interconnection to the substrate or package
___________
The terms in this series are available at www.Electropedia.org, also known as the “IEV On line”.

– 10 – 62258-1 © IEC:2009
3.1.6
bare die with connection structures
unpackaged die that have had added bumps, lead frames or other terminations to interconnect
for electrical attachment
NOTE Typically these can be die that have had solder or other metallic bumps added to the metallised pads on
the die in the form of peripheral bumps or arrays (also known as flip-chip) or die that have had fine leads attached
to the metallised pads on the die known as TAB.
3.1.7
minimally-packaged die
MPD
die that have had some exterior packaging medium and interconnection structure added for
protection and ease of handling
NOTE This definition includes such packaging technologies as Chip Scale Package (CSP) and Wafer Level
Package (WLP) in which the area of the package is not significantly greater than the area of the bare die.
3.1.8
die device
bare die, with or without connection structures, or a minimally-packaged die
3.1.9
data package
aggregate of information on a die device produced in compliance with this standard
3.2 General terminology
3.2.1
chip
common parlance for die
3.2.2
chip scale package
chip size package
CSP
generic term for packaging technologies that result in a packaged part that is only marginally
larger than the internal die
3.2.3
wafer level package
WLP
generic term for packaging technologies in which the encapsulation and any interconnection
structures are added to the wafer before separation into individual die
3.2.4
discrete (semiconductor)
single two-, three- or four-terminal semiconductor device
NOTE Discrete semiconductors include such devices as individual diodes, transistors and thyristors.
3.2.5
hybrid (circuit)
module or encapsulated sub-assembly that comprises semiconductor die and printed or
otherwise attached passive components
NOTE Also see multi-chip module and multi-chip package.

62258-1 © IEC:2009 – 11 –
3.2.6
known good die
KGD
qualification of a semiconductor die which indicates that the die has been tested to a specified
or determined level of quality or “goodness”
NOTE A commonly accepted definition of KGD is a die that has been tested and/or screened to quality levels that
are of the same order as those applicable to the equivalent packaged parts.
3.2.7
package
total assembly which protects one or more electronic components from mechanical,
environmental and electrical damage throughout its operational life and which provides means
of interconnection
3.2.8
packaging
process of assembling one or more electronic components into a package
NOTE The use of “packaging” as a participle (e.g. “When packaging ICs into dual-in-line packages …”) is
deprecated.
3.2.9
packing
material which is used to protect electronic items from mechanical, environmental and
electrical damage during transportation or storage and which is discarded prior to the
incorporation of the item into its end application
3.2.10
multi-chip module
MCM
module that contains two or more die and/or minimally-packaged die
NOTE Also see hybrid 3.2.5 and multi-chip package 3.2.11.
3.2.11
multi-chip package
MCP
package that contains two or more die and/or minimally-packaged die
NOTE Also see hybrid (3.2.5) and multi-chip module (3.2.10).
3.2.12
system in a package
SiP
functional system or sub-system in a single package that contains two or more die devices that
individually perform separate system functions
3.2.13
multi-device sub-assembly
MDS
sub-system which consists of multiple electronic devices including at least one integrated
circuit
NOTE This is a generic term which includes, among others, hybrid, MCM, MCP and SiP.
3.2.14
pad
conducting feature on a die device forming a terminal to which external electrical connections
are made
– 12 – 62258-1 © IEC:2009
NOTE For bare die without external connections, the pad acts as the terminal itself. For bumped die the terminal
is in the form of additional conducting material placed on a pad whilst for die with attached lead frame the terminal
is in the form of a conductor connected to the pad and extending from the die.
3.3 Semiconductor manufacturing and interconnection terminology
3.3.1
mask
a) optical overlay used in photo-etching during the process of semiconductor fabrication
b) major individual patterning stages that are used within the fabrication process
3.3.2
layer
level in the interconnection structure on a die device
3.3.3
passivation
top or final processing and covering on a die, usually of semiconductor oxide or nitride, that
protects and seals the active areas of the die from further external chemical or mechanical
contamination
NOTE Bond pads require an opening in this passivation to allow electrical contact.
3.3.4
scribe line
scribe lane
area surrounding the die that is set aside on the wafer for the purposes of scribing and sawing
the die from the wafer
NOTE This feature may be covered by many other terms such as scribe street, saw lane, dicing lane etc.
3.3.5
wire bonding
process of attaching interconnection wire or ribbon to a die
3.3.6
bond pads
metallised areas on the die that are used for temporary or permanent electrical connection
(bonding)
3.3.7
bump
pillar
post
column
raised metallised area on the die that is used for temporary or permanent electrical connection
3.3.8
lead frame
supporting structure upon which a die is mounted and which also includes the connection
structure to which the die is bonded
3.3.9
die attach
method and materials used to attach a die to a substrate
3.3.10
flip-chip
semiconductor die which is electrically and/or mechanically connected to an interconnection
structure in such a way that the active area faces the interconnection structure

62258-1 © IEC:2009 – 13 –
3.3.11
interposer
material placed between two surfaces giving electrical insulation, mechanical strength and/or
controlled mechanical separation between the two surfaces
NOTE An interposer may be used as a means for redistributing electrical connections and/or allowing for different
thermal expansions between adjacent surfaces.
3.3.12
redistribution
process of moving terminals on die to more convenient positions by additional connectivity
layers or by the use of an interposer
3.3.13
die stacking
wafer stacking
placing of die or wafers on top of each other to form a three dimensional stack die stacking
NOTE 1 Die are interconnected by wire-bonding, edge plating or printing, or by using through silicon vias.
NOTE 2 Die or wafers may be stacked back to face and/or face to face.
3.3.14
through silicon via
TSV
interconnection structure made through the semiconductor material of the die device from one
surface of the device to the other
NOTE The via may also have a bump, pillar or post attached to either or both sides to enable stacking of the die,
or the via itself may form a copper nail.
4 General requirements
Suppliers of die devices shall furnish, in a data package, information that is necessary and
sufficient for users of the devices at all stages of design, procurement, manufacture and test of
products containing them. Details of the requirements are given below and in other parts of this
standard.
Whilst it is expected that much of the information supplied in conformance with this
International Standard will be in the public domain and available from such sources as
manufacturers’ data sheets, this specification does not place an obligation on a supplier to
make information public. Any information that a supplier considers to be proprietary or
commercially sensitive may be supplied under the terms of a non-disclosure agreement.
For further details of requirements, refer to Clauses 6 to 12.
5 Data exchange
It is recommended that data intended for exchange by electronic means should be formatted in
accordance with the provisions of IEC 62258-2, IEC/TR 62258-7 and IEC/TR 62258-8. The
questionnaire in IEC/TR 62258-4, and the associated spreadsheet, may be used as an aid to
compliance with the requirements of this part of the standard with the possibility of converting
the spreadsheet content into one of the exchange formats.

– 14 – 62258-1 © IEC:2009
6 Requirements for all devices
6.1 Data package
6.1.1 General
Information on the data package itself shall be supplied, including sources of the information,
its version and corresponding dates.
6.1.2 Information source
The identity of the organisation or individual responsible for creating the data set shall be given.
6.1.3 Data version
The version and/or date of creation of the data set shall be given.
6.1.4 Data exchange formats
Where the data are supplied in a form suitable for data exchange using a defined schema, the
identity and version of the schema shall be stated. In addition, if the data were produced by a
software package, the identity and version of the software should also be given.
NOTE For information on suitable defined schemas, reference should be made to IEC 62258-2, IEC/TR 62258-7
and IEC/TR 62258-8.
6.2 Identity and source
6.2.1 General
The identity and source of supply for die devices shall be given with sufficient information for
the customer to communicate adequately with the supplier.
6.2.2 Type number
The type number or reference name given by the manufacturer and/or supplier to identify the
die device as supplied to the customer shall be given. In addition, the type number of an
equivalent packaged part using the same die should also be given.
6.2.3 Manufacturer
The identity of the firm responsible for manufacture of the die or wafer shall be given.
6.2.4 Supplier
The identity of the supplier of the die when this is different from the die manufacturer shall be
stated.
6.2.5 Signature
Where information on the identity of the device is embedded electronically or optically, this
should be stated together with details of the methods needed to read it.
6.3 Function
A description of the electrical function and performance variants of the die device shall be
given.
62258-1 © IEC:2009 – 15 –
6.4 Physical characteristics
6.4.1 Semiconductor material
The type of active semiconductor material used in fabricating the die device should be stated.
6.4.2 Technology
The technology of manufacture of the die device, for example CMOS, BiCMOS, bipolar etc.
shall be stated.
6.5 Ratings and limiting conditions
6.5.1 Power dissipation
Either the power dissipation within the die or the operating supply current at nominal operating
voltage under stated normal operating conditions shall be provided.
NOTE If figures for both typical and maximum power dissipation are available, both should be given.
6.5.2 Operating temperature
The range of operating temperatures of the die over which the device will operate according to
its published specifications shall be given.
6.6 Connectivity
6.6.1 General
The electrical function of all terminals shall be given in such a way that the relationships
between electrical function and geometric position of the terminals are fully defined.
6.6.2 Terminal count
The number of separate terminals, pads or other connections on the die device shall be stated.
6.6.3 Terminal information
For each terminal or pad on the die device, the following information shall be given :
a) position – the coordinates of the geometric centre of the terminal with respect to the
geometric origin
b) shape – the shape and associated dimensions of the terminal at that position

– 16 – 62258-1 © IEC:2009
c) orientation – the orientation of the terminal with respect to a reference direction on the die
device
d) signal name – the name of the signal or supply connection made to the terminal
e) signal type – the type of signal, power supply or other connection to each terminal (input,
output, supply voltage, no connect etc.)
6.6.4 Permutability
Where applicable, information should be given which is needed to specify logical and/or
physical permutability of terminals and functional blocks of a die device.
6.7 Documentation
Data sheets containing all the information prescribed herein shall be provided. These may be
supplied as hard copy or in electronic form.
6.8 Form of supply
6.8.1 Physical form
The physical form in which the die devices or wafers are supplied shall be stated, whether as
singulated die, sawn or unsawn wafers and with or without connection structures or minimal
packaging.
6.8.2 Packing
Information on the packing used to protect the die devices or wafers during handling, shipment
and storage shall be given.
6.9 Simulation and modelling
6.9.1 General
Information should
...