IEC PAS 62686-1:2011

IEC/PAS 62686-1 ®
Edition 1.0 2011-04
PUBLICLY AVAILABLE
SPECIFICATION
PRE-STANDARD
Process management for avionics – Aerospace qualified electronic components
(AQEC) –
Part 1: General requirements for high reliability integrated circuits and discrete
semiconductors
IEC/PAS 62686-1:2011(E)
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IEC/PAS 62686-1 ®
Edition 1.0 2011-04
PUBLICLY AVAILABLE
SPECIFICATION
PRE-STANDARD
Process management for avionics – Aerospace qualified electronic components
(AQEC) –
Part 1: General requirements for high reliability integrated circuits and discrete
semiconductors
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
X
ICS 03.100.50; 31.020; 49.060 ISBN 978-2-88912-468-8

– 2 – PAS 62686-1 © IEC:2011(E)
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms, definitions and abbreviations . 8
4 Abbreviations . 10
5 Technical requirements . 11
Annex A (normative) STACK Specification S/0001 Issue 14 . 12

PAS 62686-1 © IEC:2011(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
PROCESS MANAGEMENT FOR AVIONICS –
AEROSPACE QUALIFIED ELECTRONIC COMPONENTS (AQEC) –

Part 1: General requirements for high reliability integrated circuits
and discrete semiconductors
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
A PAS is a technical specification not fulfilling the requirements for a standard, but made
available to the public.
STACK Specification S/0001 revision 14 General Requirements for Integrated Circuits and
Discrete Semiconductors has served as a basis for the development of Part 1 of this publicly
available specification.
IEC PAS 62686-1 has been processed by IEC technical committee 107: Process management
for avionics.
– 4 – PAS 62686-1 © IEC:2011(E)

The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document
Draft PAS Report on voting
107/126/PAS 107/136A/RVD
Following publication of this PAS, which is a pre-standard publication, the technical committee
or subcommittee concerned may transform it into an International Standard.
This PAS shall remain valid for an initial maximum period of 3 years starting from the
publication date. The validity may be extended for a single 3-year period, following which it
shall be revised to become another type of normative document, or shall be withdrawn.
A bilingual version of this publication may be issued at a later date.

PAS 62686-1 © IEC:2011(E) – 5 –
PROCESS MANAGEMENT FOR AVIONICS –
AEROSPACE QUALIFIED ELECTRONIC COMPONENTS (AQEC) –

Part 1: General requirements for high reliability integrated circuits
and discrete semiconductors
1 Scope
This PAS defines the minimum requirements for general purpose ‘off the shelf’ COTS
integrated circuits and discrete semiconductors for high reliability applications.
This PAS complements IEC/TS 62564-1. IEC/TS 62564-1 is to be used for high reliability
applications where additional manufacturer’s data is required beyond the publicly available
manufacturer published datasheets, e.g. where additional thermal performance data is
required for thermally challenging applications or when additional DO-254 verification data is
needed for complex components for flight critical applications etc.
This PAS is to be used wherever possible for components that typically can be applied to
operate in high reliability applications within the manufacturers publicly available datasheet
limits. It is recommended that this PAS be used in conjunction with IEC/TS 62239 for avionics
applications.
This PAS is identical to STACK Specification S/0001 revision 14 which is included in Annex A.
NOTE Adoption of the STACK Specification S/0001 revision 14 will enable all existing STACK Certified
manufacturers to be audited by IECQ under the new STACK-IECQ joint venture.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60695-2-2, Fire hazard testing – Needle flame test
IEC 61340-5-1, Electrostatics – Part 5-1: Protection of electronic devices from electrostatic
phenomena – General requirements
IEC/TS 62239, Process management for avionics – Preparation of an electronic components
management plan
IEC/TS 62564-1, Aerospace qualified electronic component (AQEC) – Part 1: Microcircuits
STACK S/0001 revision 14, General Requirements for integrated circuits and discrete
semiconductors
EN 100015-3, Protection of electrostatic sensitive devices. Requirements for clean room
areas
EIA 471, Symbol and Labels for Electrostatic Sensitive Devices (ESD)
EIA 541, Packaging materials for ESD sensitive items

– 6 – PAS 62686-1 © IEC:2011(E)
EIA 556, Outer shipping container bar code label standard
JP001.01, Foundry process qualification guidelines
JEP119, Performing Standard Wafer level Electromigration Accelerated |Test (SWEAT)
JEP130-A, Guidelines for Packing and Labeling of Integrated Circuits in Unit Container
Packing (Tubes, Trays, and Tape and Reel)
JEP138, User guidelines for IR thermal imaging determination of die temperature
JESD6 , Measurement of small values of transistor capacitance
JESD22-A101, Steady state temperature humidity bias life test
JESD22-A102 , Accelerated moisture resistance unbiased autoclave
JESD22-A103 , High temperature storage life
JESD22-A104 , Temperature cycling
JESD22-A108 , Temperature bias and operating life
JESD22-A109 , Hermeticity
JESD22-A110 , Highly accelerated temperature and humidity stress test (HAST)
JESD22-A113 , Preconditioning of plastic surface mount devices prior to reliability testing
JESD22-A114 , Electrostatic Discharge Sensitivity (ESDS) testing Human Body Model (HBM)
JESD22-A117 , Endurance – Program/Erase cycle
JESD22-A118 , Accelerated moisture resistance – unbiased HAST
JESD22-B100 , Physical Dimension
JESD22-B101 , External visual
JESD22-B102 , Solderability test method
JESD22-B103 , Vibration, variable frequency
JESD22-B104 , Mechanical shock
JESD22-B105, Lead integrity
JESD22-B106 , Resistance to soldering heat
JESD22-B107 , Marking permanency
JESD22-B116 , Wire bond shear test
JESD24, Power MOSFETS
PAS 62686-1 © IEC:2011(E) – 7 –
JESD24-3, Addendum No 3 to JESD24 – Thermal impedance measurements for vertical
power mosfets (delta source-drain voltage method)
JESD24-4, Addendum No 4 to JESD24 – Thermal impedance measurements for bipolar
transistors (delta base-emitter voltage method)
JESD28, Procedure for measuring N-Channel MOSFET hot-carrier degradation at maximum
substrate current under DC stress
JESD282, Silicon rectifier diodes
JESD313, Thermal resistance measurements of conduction cooled power transistors
JESD36, Standard Description of Low-Voltage TTL-Compatible, 5 v Tolerant CMOS Logic
Devices
JESD46, Customer notification of Product/Process changes by Semiconductor Supplier’s
JESD47, Stress test driven qualification of integrated circuits
JESD48, Product Discontinuance
JESD51-1, Integrated Circuit Thermal Measurement Method – Electrical Test Method (Single
Semiconductor Device)
JESD51-2, Integrated circuits thermal test method environmental conditions – natural
convection (still air)
JESD52, Standard For Description of Low Voltage TTL-Compatible CMOS Logic Devices
JESD531, Thermal resistance test method for signal and regulator diodes (forward voltage,
switching method)
JESD625, Requirements for handling Electrostatic Discharge Sensitive devices
JESD76, Description of 1.8 V CMOS Logic Devices
JESD76-1, Standard Description of 1.2 V CMOS Logic Devices (Wide Range Operation)
JESD76-2, Standard Description of 1.2 V CMOS Logic Devices (Normal Range Operation)
JESD76-3, Standard Description of 1.5 V CMOS Logic Devices
JESD78, IC Latchup test
JESD79, Double Data Rate (DDR) SDRAM Specification
JESD79-2, DDR2 SDRAM Specification
JESD79-3, DDR3 SDRAM Standard
JESD80, Standard for Description of 2.5 V CMOS Logic Devices
JESD86, Electrical Parameter Assessment

– 8 – PAS 62686-1 © IEC:2011(E)
JESD89, Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-
Induced Soft Errors in Semiconductor Devices
JESD94.01, Application Specific Qualification Using Knowledge Based Test Methodology
JESD99, Terms, Definitions and Letter Symbols for Microelectronic Devices
J-STD-004, Requirements for soldering fluxes
J-STD-020, Moisture/reflow sensitivity classification for non-hermetic solid state surface
mount devices
J-STD-033, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount
Devices
J-STD-035, Acoustic microscopy for non-hermetic encapsulated electronic components
MIL-STD-883, Test methods standard microcircuits
MIL-STD-750, Test Method standards for semiconductor devices
UL94, Flammability of plastic materials for parts in devices and appliances, tests for
AEC-Q100, Stress Test Qualification for Integrated Circuit
AEC-Q101, Stress Test Qualification for Discrete Semiconductors, Customer Specific
Requirements (ISO/TS-16949) Semiconductor Commodity – For use by the Semiconductor
Suppliers
3 Terms, definitions and abbreviations
For the purposes of this document, the following terms, definitions and abbreviations apply.
When the following terms are used in Italics, they have the meaning defined in this clause.
3.1
calendar days
continuous days, including weekends and holidays
3.2
customer, user
original equipment manufacturer (OEM) who procures integrated circuits and/or
semiconductor devices compliant to this PAS and uses them to design, produce, and maintain
systems
3.3
data sheet
document prepared by the manufacturer that describes the electrical, mechanical, and
environmental characteristics of the component
3.4
deviation
user agreement to allow the delivery of a shipping lot which does not fully meet the
requirements of this specification
Considered equivalent to concession for the purposes of this document.

PAS 62686-1 © IEC:2011(E) – 9 –
3.5
device specification
document written by a user and agreed by the supplier
3.6
form
shape, arrangement of parts, visible aspect, mode in which a part exists or manifests itself,
the material an item is constructed from
3.7
fit
qualified and competent; correct size and shape
3.8
function
work to a specification that an item is designed to without degrading reliability
3.9
incoming lot
one or more shipments of a device, grouped together for the purpose of incoming inspection
3.10
inner box
a box or bag containing devices, either in magazines or bulk packaged
3.11
integrated circuit
microcircuit in which all or some of the circuit elements are inseparably associated and
electrically interconnected so that it is considered to be indivisible for the purpose of
construction and commerce
3.12
limitation
requirement of this specification that is not met
3.13
magazine
sticks, tubes, matrix trays, tape/reel, etc.
3.14
microcircuit, component, device
electrical or electronic device, with a high circuit-element density, in which all or some of the
circuit elements are inseparably associated and electrically interconnected (on one or more
substrates, in a unique indivisible package) so that it is considered to be indivisible for the
purpose of construction and commerce
3.15 outer box
outer shipping container, containing one or more inner boxes
3.16
room remperature
o o
temperature of 25 C ± 5 C
– 10 – PAS 62686-1 © IEC:2011(E)
3.17
semiconductor, device
electronic devices in which the essential electrical characteristic distinguishing electronic
conduction takes place due to the flow of charge carriers within one or more semiconductor
materials
This includes:
a) semiconductor diodes which are semiconductor devices having two terminals and
exhibiting a nonlinear voltage-current characteristic, and
b) transistors which are active semiconductor devices capable of providing power
amplification and having three or more terminals.
3.18
shipping lot
single lot of one or more outer boxes received by a user
3.19
supplier
the company identified by the logo or name marked on the device
3.20
termination
element of a component that connects it electrically and mechanically to the next level of
assembly
3.21
triboelectric charge
electrical charge generated by frictional movement or separation of two surfaces
3.22
user
the general public using this IEC specification , STACK Members, IECQ Certification Bodies
(CBs) or organizations authorized by the STACK Office to use this specification
3.23
waiver
written notice that a requirement of this specification no longer applies or is relaxed as
requested during the registration process
If granted by the STACK Members, the waiver shall be documented on the Registration
Certificate and is applicable to that individual supplier only.
4 Abbreviations
AQEC  Aerospace qualified electronic component
BPSG  Borophosphosilicate glass
COTS  Commercial off the shelf
CMOS  Complementary metal oxide semiconductor
DPM Defects per million. It may also be referred as PPM (parts per million).
DSCC  Defence supply centre Columbus (see http://www.dscc.dla.mil/)

PAS 62686-1 © IEC:2011(E) – 11 –
ECMP  Electronic component management plan
FFF  Form, fit and function
FIT  Failures in time
HAST  Highly accelerated stress test
HCI  Hot carrier injection
HTOL  High temperature operating life
LTB  Last time buy
LTPD Lot tolerance percent defective
MSL Moisture sensitivity level as defined in J-STD-20 relating to the packaging and
handling precautions needed for semiconductors
NBTI  Negative bias temperature instability
PCN  Product change notification
SEE  Single event effect
SEU  Single event upset
SER  Soft error rate
THB  Temperature humidity bias
T min Minimum operating temperature
op
T max Maximum operating temperature
op
5 Technical requirements
The supplier shall provide the user requirements for quality, reliability and general
requirements for integrated circuits and discrete semiconductors not otherwise governed by
and supplied to Military Specifications, as stated in STACK S/0001 revision 14.
STACK S/0001 specification revision 14 is included in Annex A.
NOTE 1 The required information is available to STACK Members by a method agreed during registration and to
IECQ certified companies from their IECQ certification body (IECQ CB).
NOTE 2 Limitations may be identified during a certification audit where some of suppliers products do not meet
the requirements of this specification due to marketing reasons. In that event, the supplier shall be noted as having
limitations which shall be recorded in the audit report and on the certificate. These limitations are applicable to that
individual supplier only.
– 12 – PAS 62686-1 © IEC:2011(E)
Annex A
(normative)
STACK Specification S/0001 Issue 14

IEC QUALITY ASSESSMENT SYSTEMS FOR HIGH RELIABILITY
INTEGRATED CIRCUITS AND DISCRETE SEMICONDUCTORS

PAS 62686-1 © IEC:2011(E) – 13 –

Page 13 of 39
STACK 0001
Issue 14
IEC QUALITY ASSESSMENT SYSTEMS FOR HIGH RELIABILITY INTEGRATED
CIRCUITS AND DISCRETE SEMICONDUCTORS

(IECQ System)
GENERAL REQUIREMENTS FOR INTEGRATED CIRCUITS

AND DISCRETE SEMICONDUCTORS
JOINT COMPANY STANDARD
This is a Joint STACK INTERNATIONAL & IECQ
Specification issued by:
IECQ on behalf of both organisations
www.iecq.org
www.stackinternational.com
Tel: +44 (0) 1727 829100
Fax: +44 (0) 1727 821542
Copyright  10 January 2009 STACK International.
This document may be reproduced with this copyright notice

– 14 – PAS 62686-1 © IEC:2011(E)

GENERAL REQUIREMENTS
Page 14 of 45
FOR INTEGRATED CIRCUITS AND STACK 0001
DISCRETE SEMICONDUCTORS Issue 14

CONTENTS
1. INTRODUCTION 10. AUDIT CAPABILITY 14. RELIABILITY
1.1 Purpose and scope 10.1 Internal quality audits
14.1 Operating reliability
1.2 Use of equivalent tests 10.2 Sub contract 14.2 Failure criteria
1.3 Liaison manufacturing 14.3 Corrective action
1.4 Translation 14.4 Warranty
11. QUALITY ASSURANCE
1.5 Compliance with internal 14.5 Suspension of qualification
company standards 11.1 Quality system approval
11.2 Sampling plans
14.6 Single event effects
2. REFERENCED 11.3 Failure analysis support Table 4 Operating life failure
STANDARD
11.4 Outgoing quality rates
Table 1 Device Family
3. TERMS AND DEFINITIONS
15. PRODUCT MONITOR
12. INCOMING INSPECTION 15.1 Monitor program
4. ADMINISTRATION
12.1 Lot acceptance 15.2 Problem notifications
4.1 Registration 12.2 Suspension of deliveries 15.3 Data reporting
4.2 Certification 12.3 Loss of approval 15.4 Samples
4.3 Proprietary data 12.4 AQL/LTPD figures 15.5 Production maturity factors
4.4 Deviation 12.5 100% screening 15.6 Device dissipation
4.5 Updates to this Table 2 Incoming test 15.7 Corrective action
specification 15.8 Suspension of certification
13. QUALIFICATION 15.9 Accumulated test data
5. PROCEDURES
13.1 Methodology Table 5 Product Monitor Tests
5.1 Product discontinuation 13.2 Test Samples
5.2 ESD protection during 13.3 Qualification categories 16. ENVIRONMENTAL,
manufacture 13.4 Maintenance of HEALTH AND SAFETY
5.3 Specification control qualification standard 16.1 EHS Compliance
5.4 Traceability 13.5 In process test results 16.2 Device handling
13.6 Product monitor results 16.3 Device materials
6. CHANGE NOTIFICATION 13.7 References
6.1 Notification 13.8 Qualification report 17. SHIPMENT PACKAGING
6.2 Notification details 13.9 Archiving 17.1 General
6.3 Notifiable changes Table 3 Technology/Family 17.2 Magazine reuse
Qualification and Device 17.3 Tubes
7. SHIPMENT CONTROLS Qualification 17.4 Trays
7.1 Reference standard 13.10 Qualification By Similarity
7.2 Date code remarking 13.11 Similarity Assessment 18. LABELS
7.3 Inner box formation 13.11.1 Die changes 18.1 General
7.4 Date code age on delivery 13.11.2 Process/Wafer Fab 18.2 Label Content
7.5 ESD marking changes
7.6 MSL 13.11.3 Package/Assembly 19. TEST CODE
changes INFORMATION
8. ELECTRICAL
8.1 Operating conditions 20. DOCUMENT REVISION
8.2 Electrical test HISTORY
9. MECHANICAL
9.1 Package dimensions
9.2 Device marking
9.3 Moisture sensitivity
9.4 Robustness of hermetic
seals
9.5 Termination finishes
PAS 62686-1 © IEC:2011(E) – 15 –

GENERAL REQUIREMENTS
Page 15 of 45
FOR INTEGRATED CIRCUITS AND STACK 0001
DISCRETE SEMICONDUCTORS Issue 14

1. INTRODUCTION
1.1 Purpose and Scope: This specification defines user quality, reliability and general requirements
for integrated circuits and discrete semiconductors, not otherwise governed by and supplied to
Military Specifications. Thus it forms the basis of the Stack Registration and Certification
programs. Organizations complying with this specification may apply for assessment and
certification under the International IECQ Process Approvals Scheme by contacting an approved
IECQ Certification Body (CBs) listed at www.iecq.org.

1.2 Use of Equivalent Tests: To comply with the requirements of this specification, the supplier may
use the test methods and methodologies specified herein or any other equivalent test method.
Proposed equivalent test methods, rationale and supporting data shall be reviewed during the
Registration and or Certification processes by the STACK members or the audit team (including
the IECQ CB assessment Team) and shall achieve the same end objectives as specified herein.
The user reserves the right to reject product failing to meet the test methods (or equivalent test
methods) specified herein. Use of such equivalent tests shall not be considered to be deviations
or waivers to the requirements of this specification.

1.3 Liaison: Enquiries relating to this specification, which concern product deliveries or orders, shall
be addressed to the user. Enquiries relating to registration should be addressed to:

STACK International,
Tyttenhanger House,
Coursers Road,
Colney Heath,
St. Albans,
AL4 0PG,
U.K.
Tel: +44 (0)1727 829100
Fax: +44 (0)1727 821542
1.4 Translation: If translated into other languages the English language version of this specification
shall prevail.
1.5 Compliance with Internal Standards: This document does not exempt the suppliers of their
responsibility to meet their own company internal requirements.

2. REFERENCED STANDARDS
2.1 References to other documents form a part of this specification to the extent specified herein.
Where no particular document revision is given the latest revision is intended. In case of conflict
between this specification and the content of any referenced standard (excluding Section 19), the
content of this specification defines the STACK requirement.

EN 100015-3 Protection of electrostatic sensitive devices. Requirements for clean room areas.
EIA 471 Symbol and Labels for Electrostatic Sensitive Devices (ESD).
EIA 541 Packaging materials for ESD sensitive items.
EIA 556 Outer shipping container bar code label standard.
IEC 60695-2-2 Fire hazard testing - Needle flame test.
IEC 61340-5-1 Electrostatics - Part 5-1: Protection of electronic devices from electrostatic
phenomena - General requirements.
JP001.01 Foundry process qualification guidelines.
JEP119 Performing Standard Wafer level Electromigration Accelerated |Test (SWEAT).

– 16 – PAS 62686-1 © IEC:2011(E)

GENERAL REQUIREMENTS
Page 16 of 45
FOR INTEGRATED CIRCUITS AND STACK 0001
DISCRETE SEMICONDUCTORS Issue 14

JEP130-A Guidelines for Packing and Labeling of Integrated Circuits in Unit Container
Packing (Tubes, Trays, and Tape and Reel).
JEP138 User guidelines for IR thermal imaging determination of die temperature.
JESD6 Measurement of small values of transistor capacitance.
JESD22-A101 Steady state temperature humidity bias life test.
JESD22-A102 Accelerated moisture resistance unbiased autoclave.
JESD22-A103 High temperature storage life.
JESD22-A104 Temperature cycling.
JESD22-A108 Temperature bias and operating life.
JESD22-A109 Hermeticity.
JESD22-A110 Highly accelerated temperature and humidity stress test (HAST).
JESD22-A113 Preconditioning of plastic surface mount devices prior to reliability testing.
JESD22-A114 Electrostatic Discharge Sensitivity (ESDS) testing Human Body Model (HBM).
JESD22-A117 Endurance - Program/Erase cycle.
JESD22-A118 Accelerated moisture resistance - unbiased HAST.
JESD22-B100 Physical Dimension.
JESD22-B101 External visual.
JESD22-B102 Solderability test method.
JESD22-B103 Vibration, variable frequency.
JESD22-B104 Mechanical shock.
JESD22-B105 Lead integrity.
JESD22-B106 Resistance to soldering heat.
JESD22-B107 Marking permanency.
JESD22-B116 Wire bond shear test.
JESD24 Power MOSFETS
JESD24-3 Addendum No 3 to JESD24 - Thermal impedance measurements for vertical power
mosfets (delta source-drain voltage method).
JESD24-4 Addendum No 4 to JESD24 - Thermal impedance measurements for bipolar
transistors (delta base-emitter voltage method).
JESD28 Procedure for measuring N-Channel MOSFET hot-carrier degradation at maximum
substrate current under DC stress.
JESD282 Silicon rectifier diodes.
JESD313 Thermal resistance measurements of conduction cooled power transistors.
JESD36 Standard Description of Low-Voltage TTL-Compatible, 5 v Tolerant CMOS Logic
Devices.
JESD46 Customer notification of Product/Process changes by Semiconductor Supplier’s.
JESD47 Stress test driven qualification of integrated circuits.
JESD48 Product Discontinuance.
JESD51-1 Integrated Circuit Thermal Measurement Method - Electrical Test Method (Single
Semiconductor Device).
JESD51-2 Integrated circuits thermal test method environmental conditions - natural
convection (still air).
JESD52 Standard For Description of Low Voltage TTL-Compatible CMOS Logic Devices
JESD531 Thermal resistance test method for signal and regulator diodes (forward voltage,
switching method).
JESD625 Requirements for handling Electrostatic Discharge Sensitive devices.
JESD76 Description of 1.8 V CMOS Logic Devices.
JESD76-1 Standard Description of 1.2 V CMOS Logic Devices (Wide Range Operation).
JESD76-2 Standard Description of 1.2 V CMOS Logic Devices (Normal Range Operation).
JESD76-3 Standard Description of 1.5 V CMOS Logic Devices.
JESD78 IC Latchup test.
JESD79 Double Data Rate (DDR) SDRAM Specification.
JESD79-2 DDR2 SDRAM Specification.
JESD79-3 DDR3 SDRAM Standard.
PAS 62686-1 © IEC:2011(E) – 17 –

GENERAL REQUIREMENTS
Page 17 of 45
FOR INTEGRATED CIRCUITS AND STACK 0001
DISCRETE SEMICONDUCTORS Issue 14

JESD80 Standard for Description of 2.5 V CMOS Logic Devices.
JESD86 Electrical Parameter Assessment.
JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-
Induced Soft Errors in Semiconductor Devices.
JESD94.01 Application Specific Qualification Using Knowledge Based Test Methodology.
JESD99 Terms, Definitions and Letter Symbols for Microelectronic Devices.
J-STD-004 Requirements for soldering fluxes.
J-STD-020 Moisture/reflow sensitivity classification for non-hermetic solid state surface mount
devices.
J-STD-033 Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount
Devices.
J-STD-035 Acoustic microscopy for non-hermetic encapsulated electronic components.
MIL-STD-883 Test methods standard microcircuits.
MIL-STD-750 Test Method standards for semiconductor devices.
UL94 Flammability of plastic materials for parts in devices and appliances, tests for.
AEC-Q100 Stress Test Qualification for Integrated Circuits.
AEC-Q101 Stress Test Qualification for Discrete Semiconductors
Customer Specific Requirements (ISO/TS-16949) Semiconductor Commodity – For
use by the Semiconductor Suppliers.

3. TERMS AND DEFINITIONS
3.1 For the purposes of this specification, when the following terms are used in Italics they have the
meaning defined in this section:

Available: The required information is available to STACK Members by a method
agreed during registration and to IECQ Certified companies from their
IECQ Certification Body (IECQ CB).
Calendar Days: Continuous days, including weekends and holidays.
Deviation: User agreement to allow the delivery of a shipping lot which does not fully
meet the requirements of this specification. Considered equivalent to
concession for the purposes of this document
Data Sheet: A device specification written by the device manufacturer.
Device: An integrated circuit or discrete semiconductor.
Device Specification: A device specification written by a user and agreed by the supplier.
Discrete Semiconductor: Applies to transistor, diode, or semiconductors of similar complexity.
DPM: Defects per million may also be referred as PPM (parts per million)
Form/Fit/Function: As defined in JESD46 i.e.:
Form - Visual appearance including shape, color, marking and surface finish etc.
Fit - External dimensions and associated tolerances etc.
Function - Electrical, mechanical, thermal, and performance characteristics, etc.
Incoming Lot: One or more shipments of a device, grouped together for the purpose of
incoming inspection.
Inner Box: A box or bag containing devices, either in magazines or bulk packaged.
Integrated Circuit: A microcircuit is a small circuit having a high equivalent circuit element
density which is considered as a single part composed of interconnected
elements on or within a single substrate (silicon) to perform an electronic
circuit function. (This excludes printed wiring boards (PWBs), circuit card
assemblies (CCAs) and modules composed exclusively of discrete
electronic parts.)
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Limitation: It may be identified during a Certification Audit that some of a suppliers
products do not meet the requirements of this specification due to
marketing reasons. In that event, the supplier shall be noted as having
limitations which shall be recorded in the audit report and on the
Certificate. These limitations are applicable to that individual supplier
only.
LTPD: Lot tolerance percent defective.
Manufacturing Lot: A definite quantity of devices tracked at each manufacturing operation. It
is associated with a travel log and constitutes a group, homogeneously
processed through all manufacturing operations under uniform
manufacturing conditions.
May: Indicates a course of action which is permissible within the limits of this
document.
Magazine: Sticks, tubes, matrix trays, tape/reel, etc.
MSL: Moisture Sensitivity Level as defined in J-STD-20 relating to the
packaging and handling precautions needed for semiconductors.
PCN: Product Change Notification.
Outer Box: An outer shipping container, containing one or more inner boxes.
o o
Room Temperature: 25 C ± 5 C
Shall: Indicates a requirement.
Should: Offers a guideline or recommendation that might be used or helpful to
assure compliance to this document.
Shipping Lot: A single lot of one or more outer boxes received by a user.
Specification: This specification together with all other documents referred to as forming
part thereof.
Supplier: The company identified by the logo or name marked on the device.
Termination: Method by which the device is attached to a board, includes leads, pads,
balls, columns etc.
T min: Minimum operating temperature.
op
T max: Maximum operating temperature.
op
Triboelectric Charge: Electrical charge generated by frictional movement or separation of two
surfaces.
User: STACK Members, IECQ Certification Bodies (CBs) or organizations
authorized by the STACK Office to use this specification.
Waiver: A written notice that a requirement of this specification no longer applies
or is relaxed as requested during the Registration process. If granted by
the STACK Members, the waiver shall be documented on the Registration
Certificate and is applicable to that individual supplier only.

3.2 Other common physical and electrical terms along with industry-standard symbols and
abbreviations for the characterization, nomenclature, and classification of a device should be as
described in JESD99.
4. ADMINISTRATION
4.1 Registration to this Specification:
4.1.1 STACK Supplier Registration or IECQ Registration is a formal supplier declaration that the
supplier's standard qualification procedure, product monitor program and manufacturing processes
are in compliance with this specification or that compliance will be achieved in a specified time
and, that the other requirements of this specification will be met when devices are purchased to
this specification. A waiver may be granted at the discretion of the STACK Membership or IECQ
CBs. IECQ Certificate of Approval may be issued, to demonstrate compliance with this
specification, by an IECQ CB according to IECQ Process Approvals requirements. Applications are
to be lodged with IECQ CBs.
PAS 62686-1 © IEC:2011(E) – 19 –

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4.1.2 STACK Distributor Registration or IECQ Registration is a formal distributor declaration that the
distributor's procedures will ensure the following requirements of this specification are met when
parts are ordered to this specification for a supplier currently listed as registered on
www.stackinternational.com. (All other requirements will be deemed the responsibility of the
registered supplier.)
• Forwarding of product change and discontinuance notices received from the supplier.
• Date code age on delivery.
IECQ Certificate of Approval may be issued, to demonstrate compliance with this specification, by
an IECQ CB according to IECQ Process Approvals requirements. Applications are to be lodged
with IECQ CBs.
4.1.3 Suspension of STACK Registration / IECQ Registration can occur if it is determined that a
Registered supplier is not fully compliant with this specification, or any waivers granted and if after
due discussion, an agreement cannot be reached to resolve the problem. Registration / IECQ
Registration may be suspended until the non-compliance is corrected or a corrective action plan
has been agreed upon. Suspension of registration may have an impact on any certifications held.

4.2 STACK Certification or IECQ Certification to the Specification:
4.2.1 STACK Supplier or IECQ Certification is a formal audit by a team of STACK auditors or IECQ CBs,
directed by a Lead Auditor who is responsible for closing out the audit to the requirements of this
specification. The results of the audit shall be written up in an audit report, available to all STACK
and IECQ Members, which shall contain details of any limitations, use of equivalent tests or
processes approved during the audit by the Stack auditors and IECQ CBs. The audit checklist
SP04 shall be used and shall be the basis of the audit report.
IECQ Certificate of Approval may be issued, to demonstrate compliance with this specification, by
an IECQ CB according to IECQ Process Approvals requirements. Applications are to be lodged
with IECQ CBs.
4.2.2 Suspension of STACK or IECQ Certification can occur if it is determined that a STACK or IECQ
Certified supplier is not fully compliant with this specification, or accepted limitations if any and if
after due discussion, an agreement cannot be reached to resolve the non-compliance.
Certification may be suspended until the non-compliance is corrected or a corrective action plan
has been agreed upon. Suspension of certification may have an impact on any registrations held.

4.3 Proprietary Data: Where the information provided for Registration or Certification purposes is
considered proprietary, that information shall be disseminated from the supplier to the STACK
members or IECQ CBs through the STACK or IECQ office. Non-Disclosure Agreements can be
used, if required.
4.4 Deviations:
a) In the event that a supplier intends to deviate from the requirements of the purchase order,
relevant specifications, or this specification for a custom part where the user is known, prior
written consent must be obtained from the user. If device specific deviation procedures are
otherwise specified, (e.g. in a Custom ASIC purchase contract) those requirements will apply.
b) In the event that a supplier deviates from the requirements of the purchase order, relevant
specifications, standard data sheet, or this specification for an “off the shelf” catalogue part
where the user is unknown, the suppliers shall distribute this information via their sales teams
and/or on their web pages and to all franchised distributors.
c) Applications for deviations must contain the following information. If any item is not known at
time of request, the request should be submitted with the remaining information to follow as
soon as practicable:
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Supplier type number
Description of deviation(s)
Quantities or time period affected
User part number
Cause of deviations.
Corrective actions being taken to overcome the deviation on subsequent deliveries, as
required.
d) Devices subjected to application for a deviation shall be held at the supplier's premises pending
reply unless otherwise instructed by the user.

4.5 Updates to this Specification:
Updates to this specification will be circulated to all STACK registered suppliers and IECQ
Registered Suppliers. A period of time will be defined at each release date depending on the
extent of the change to allow suppliers to formally accept the new issue.

5. PROCEDURES
5.1 Product Discontinuation: Notification shall be in accordance with JESD48 or equivalent with the
exception of Timing as described in paragraphs 5.1.1, 5.1.2 below.

5.1.1 The supplier shall provide to the user a minimum 12 months notice of last order dates for single
source devices and 6 months for multi sourced devices.

5.1.2 The supplier may give less than the specified notice period provided a mutually acceptable
extension (up to the specification limit) is negotiated with any STACK Member needing a different
period.
5.1.3 For custom ASIC’s the normal procedure is to include discontinuation notice in the purchase
contract.
5.2 ESD Protection during Manufacture: All integrated circuits and discrete semiconductors are
considered to be static sensitive and shall be so protected through the supplier’s manufacturing
operation. Suppliers shall ensure that devices are not exposed to static damage and are not
degraded or damaged due to static discharge. EN100015-3 and JESD625 are examples of
suitable standards for ESD precautions in wafer fab and probe. Suppliers holding current IECQ
Certification for compliance with IEC 61340-5-1 shall be deemed to have satisfied this
requirement.
5.3 Specification Control: The supplier shall:
a) Have central or local recor
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