WG 13 - TC 91/WG 13

IEC 61967-7:2025 defines SystemC® with Transaction Level Modeling (TLM) as an ISO standard C++ class library for system and hardware design. SystemC®1 as an ANSI standard C++ class library for system and hardware design.
The general purpose of this standard is to provide a C++-based standard for designers and architects who need to address complex systems that are a hybrid between hardware and software. The specific purpose of this standard is to provide a precise and complete definition of the SystemC class library including a TLM library so that a SystemC implementation can be developed with reference to this standard alone. This standard is not intended to serve as a user’s guide or to provide an introduction to SystemC, but it does contain useful information for end users.
The changes with respect to the previous edition are provided in Annex D.
This standard is published as a double logo IEC-IEEE standard.

IEC 62014-4:2025 describes an eXtensible Markup Language (XML) schema for meta-data documenting intellectual property (IP) used in the development, implementation, and verification of electronic systems. This schema provides both a standard method to document IP that is compatible with automated integration techniques and a standard method (generators) for linking tools into a system development framework, enabling a more flexible, optimized development environment. Tools compliant with this standard will be able to interpret, configure, integrate, and manipulate IP blocks that comply with the IP meta-data description. The standard is independent of any specific design processes. It does not cover behavioral characteristics of the IP that are not relevant to integration. This standard enables the creation and exchange of IP in a highly automated design environment.
This standard is published as a double logo IEC-IEEE standard.

IEC 63501-2416:2023 describes a parameterized and abstracted power model enabling system, software, and hardware intellectual property (IP)-centric power analysis and optimization. It defines concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature (PVT) independence; power and thermal management interface; and workload and architecture parameterization. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models to help guide development and usage of other related power, workload, and functional modeling standards. This standard is published as a double logo IEC-IEEE standard.

IEC 63504-2804:2023 defines an architecture description standard from the software design perspective - this provides a common interface that abstracts the hardware properties that are critical to enable multicore tools. The standard includes performance estimation accuracy for complex processors like Very Long Instruction Word (VLIW) core and complex contention scenarios, description of caches to include uncached memory regions and caches for subsets of memories, properties for coarse power consumption estimation, and reusability by separating eXtensible Markup Language (XML) files for processor description and other memory/communication-related information. This is an IEC/IEEE dual logo standard.

IEC 61523-4:2023 defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries). This is an IEC/IEEE dual logo standard.
The contents of the corrigendum 1 (2024-02) have been included in this copy.

IEC 63055:2023 defines a common interoperable format that will be used for the design of a) large-scale integration (LSI), b) packages for such LSI, and c) printed circuit boards on which the packaged LSIs are interconnected. Collectively, such designs are referred to as LSI-Package-Board (LPB) designs. The format provides a common way to specify information/data about the project management, netlists, components, design rules, and geometries used in LPB designs. This is an IEC/IEEE dual logo standard.

IEC 61691-1-1:2023 defines the syntax and semantics of the VHSIC Hardware Description Language (VHDL). The acronym VHSIC (Very High Speed Integrated Circuits) in the language’s name comes from the U.S. government program that funded early work on the standard. This is an IEC/IEEE dual logo standard.

IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.

IEC TR 63051:2017(E) describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.

IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.

IEC 62531:2012(E) defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages. This second edition cancels and replaces the first edition, published in 2007, and constitutes a technical revision.

IEC 61523-1:2012(E) focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. This second edition cancels and replaces the first edition, published in 2001, and constitutes a technical revision.

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

IEC 61691-1-1:2011(E) Revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification. The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications. This publication has the status of a double logo IEEE/IEC standard.

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

IEC 61691-7:2009(E) defines SystemC®1 as an ANSI standard C++ class library for system and hardware design. The specific purpose is to provide a precise and complete defination of the System C class library so that a System C implementation can be developed.

Defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages.

The Standard Delay Format (SDF)is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process.The ASCII data in the SDF le is represented in a tool and language independent way and includes path delays,timing constraint values,inter-connect delays and high level technology parameters. This standard is published with a double logo IEC-IEEE. standard.

The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs.

Gives specifications for electronic behavioral of digital integrated circuit input/ output analog characteristics. It specifies a consistent software-parsable format for essential behavioral information. The goal of this standard is to support all simulators of all degrees of sophistication.

Provides the semantics definitions for the categories of information related to electronic circuit designs. Each category of design information is modelled as an EXPRESS schema