IEC 61691-6:2009

IEC 61691-6
Edition 1.0 2009-12
™
IEEE Std 1076.1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions

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IEC 61691-6
Edition 1.0 2009-12
™
IEEE Std 1076-1
INTERNATIONAL
STANDARD
Behavioural languages –
Part 6: VHDL Analog and Mixed-Signal Extensions
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 25.040, 35.060 ISBN 978-0-7381-6283-6

– i –
IEEE Std 1076.1-2007(E)
CONTENTS
Foreword .v
IEEE introduction .viii
0. Overview. 1
0.1 Purpose and scope. 1
0.2 Normative references. 1
0.3 Structure and terminology of this standard.2
1. Design entities and configurations. 5
1.1 Entity declarations . 5
1.2 Architecture bodies . 10
1.3 Configuration declarations. 12
2. Subprograms and packages. 19
2.1 Subprogram declarations . 19
2.2 Subprogram bodies . 22
2.3 Subprogram overloading. 24
2.4 Resolution functions . 27
2.5 Package declarations. 27
2.6 Package bodies. 29
2.7 Conformance rules. 30
3. Types and natures . 31
3.1 Scalar types . 32
3.2 Composite types. 38
3.3 Access types. 43
3.4 File types. 46
3.5 Protected types. 48
3.6 Natures . 51
4. Declarations . 55
4.1 Type declarations. 55
4.2 Subtype declarations . 56
4.3 Objects . 57
4.4 Attribute declarations. 75
4.5 Component declarations. 76
4.6 Group template declarations . 77
4.7 Group declarations. 77
4.8 Nature declaration. 78
5. Specifications. 81
5.1 Attribute specification. 81
5.2 Configuration specification. 83
5.3 Disconnection specification. 91
5.4 Step limit specification . 93
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– ii –
IEEE Std 1076.1-2007(E)
6. Names . 97
6.1 Names . 97
6.2 Simple names. 98
6.3 Selected names. 99
6.4 Indexed names . 101
6.5 Slice names . 102
6.6 Attribute names. 102
7. Expressions . 105
7.1 Expressions . 105
7.2 Operators. 106
7.3 Operands . 115
7.4 Static expressions. 121
7.5 Universal expressions . 123
7.6 Linear forms. 124
8. Sequential statements. 127
8.1 Wait statement . 127
8.2 Assertion statement. 129
8.3 Report statement . 130
8.4 Signal assignment statement. 130
8.5 Variable assignment statement . 135
8.6 Procedure call statement . 137
8.7 If statement. 137
8.8 Case statement . 138
8.9 Loop statement. 139
8.10 Next statement . 140
8.11 Exit statement. 140
8.12 Return statement . 140
8.13 Null statement . 141
8.14 Break statement. 141
9. Concurrent statements. 143
9.1 Block statement. 143
9.2 Process statement. 144
9.3 Concurrent procedure call statements. 145
9.4 Concurrent assertion statements . 146
9.5 Concurrent signal assignment statements . 147
9.6 Component instantiation statements . 151
9.7 Generate statements . 157
9.8 Concurrent break statement . 158
10. Scope and visibility. 159
10.1 Declarative region. 159
10.2 Scope of declarations . 160
10.3 Visibility . 161
10.4 Use clauses. 164
10.5 The context of overload resolution . 165

Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– iii –
IEEE Std 1076.1-2007(E)
11. Design units and their analysis . 167
11.1 Design units . 167
11.2 Design libraries . 167
11.3 Context clauses . 168
11.4 Order of analysis. 169
12. Elaboration and execution. 171
12.1 Elaboration of a design hierarchy . 171
12.2 Elaboration of a block header . 173
12.3 Elaboration of a declarative part. 175
12.4 Elaboration of a statement part . 179
12.5 Dynamic elaboration. 182
12.6 Execution of a model . 183
12.7 Time and the analog solver. 194
12.8 Frequency and noise calculation. 195
13. Lexical elements . 197
13.1 Character set. 197
13.2 Lexical elements, separators, and delimiters . 199
13.3 Identifiers . 200
13.4 Abstract literals . 201
13.5 Character literals . 202
13.6 String literals. 202
13.7 Bit string literals. 203
13.8 Comments . 204
13.9 Reserved words. 205
13.10 Allowable replacements of characters . 207
14. Predefined language environment. 209
14.1 Predefined attributes . 209
14.2 Package STANDARD . 231
14.3 Package TEXTIO. 240
15. Simultaneous statements. 245
15.1 Simple simultaneous statement. 245
15.2 Simultaneous if statement. 246
15.3 Simultaneous case statement. 246
15.4 Simultaneous procedural statement . 247
15.5 Simultaneous null statement . 250
Annex A (informative) Syntax summary. 251
Annex B (informative) Glossary. 275
Annex C (informative) Potentially nonportable constructs . 297
Annex D (informative) Changes from IEEE Std 1076.1-1999. 299
Annex E (informative) Features under consideration for removal . 301
.
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– iv –
IEEE Std 1076.1-2007(E)
Annex F (informative) Bibliography . 303
Annex G (informative) List of Participants.305
Index . 307

Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– v –
IEEE Std 1076.1-2007(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
BEHAVIOURAL LANGUAGES –
Part 6: VHDL Analog and Mixed-Signal Extensions

FOREWORD
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International Standard IEC 61691-6/IEEE Std 1076.1 has been processed through IEC
technical committee 93: Design automation.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1076.1 (2007) 93/280/FDIS 93/286/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
A list of parts of the IEC 61691 series can be found on the IEC web site.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– vi –
IEEE Std 1076.1-2007(E)
IEC/IEEE Dual Logo International Standards
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Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– vii – IEC 61691-6:2009(E)
IEEE Std 1076.1-2007(E)
IEEE Standard VHDL Analog and
Mixed-Signal Extensions
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 17 May 2007
IEEE SA-Standards Board
Abstract: This standard defines the IEEE 1076.1 language, a hardware description language for
the description and the simulation of analog, digital, and mixed-signal systems. The language, also
™
informally known as VHDL-AMS, is built on IEEE Std 1076 -2002 (VHDL) and extends it with
additions and changes to provide capabilities of writing and simulating analog and mixed-signal
models.
Keywords: analog design, computer, computer languages, hardware design, mixed-signal design,
VHDL
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– viii –
IEEE Std 1076.1-2007(E)
IEEE introduction
The IEEE 1076.1 language, informally known as VHDL-AMS, is a superset of IEEE Std 1076-2002 (VHDL) that
provides capabilities for describing and simulating analog and mixed-signal systems with conservative and
nonconservative semantics for the analog portion of the system. The language supports many abstraction levels in
electrical and non electrical energy domains. The modeled analog systems arelumped systems that can be described by
ordinary differential equations and algebraic equations. The language does not specify any particular technique to solve
the equations, but it rather defines the results that must be achieved. The solution of the equations may include
discontinuities. Interaction between the digital part of a model and its analog part is supported in a flexible and efficient
manner. Finally, support for frequency domain small-signal and noise simulation is provided.

The extension of VHDL to support analog and mixed-signal systems began in 1989, as part of the second revision of
IEEE Std 1076 targeted for a 1993 release. A large number of requirements to support analog and mixed-signal systems
were submitted, and it soon became apparent that the complexity of the topic required the formation of a separate working
group. The design of the IEEE 1076.1 language formally began in 1993, when the IEEE 1076.1 Working Group was
formed under the auspices of the Design Automation Standards Committee of the IEEE Computer Society, under Project
Authorization Request (PAR) 1076.1. Its charter was to extend the IEEE 1076 (VHDL) language to support the
requirements for the description and simulation of analog and mixed-signal systems. The IEEE 1076.1 Working Group
approved the draft standard in June 1997. The first release of the draft of IEEE Std 1076.1-1999 was approved by the IEEE
Standards Board on 18 March 1999.

The 2007 revision includes changes made to IEEE Std 1076-2002 since the first release of the IEEE 1076.1 standard. It
also includes clarification of IEEE 1076.1 language definitions and corrections of typographical errors that were
introduced in the 1999 version of the IEEE 1076.1 language reference manual. See the Annex D for a list of changes
from the 1999 release.
Notice to users
Errata
Errata, if any, for this and all other standards can be accessed at the following URL: http://
standards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errata
periodically.
Interpretations
Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee/interp/index.html.

Patents
Attention is called to the possibility that implementation of this standard may require use of subject matter covered by
patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent
rights in connection therewith. The IEEE is not responsible for identifying Essential Patent Claims for which a license may
be required, for conducting inquiries into the legal validity or scope of Patents Claims or determining whether any licensing
terms or conditions provided in connection with submission of a Letter of Assurance, if any, or in any licensing agreements
are reasonable or non-discriminatory. Users of this standard are expressly advised that determination of the validity of any
patent rights, and the risk of infringement of such rights, is entirely their own responsibility. Further information may be
obtained from the IEEE Standards Association.

IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or environmental protection
in all circumstances. Implementers of the standard are responsible for determining appropriate safety, security,
environmental, and health practices or regulatory requirements.

This IEEE document is made available for use subject to important notices and legal disclaimers. These notices and
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Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

IEEE Std 1076.1-2007(E)
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– 1 –
IEEE Std 1076.1-2007(E)
BEHAVIOURAL LANGUAGES –
Part 6: VHDL Analog and Mixed-Signal Extensions

0. Overview
This clause describes the purpose, scope, and organization of this standard.
0.1 Purpose and scope
This standard defines IEC 61691-6/IEEE 1076.1™ language, a hardware description language for the description and
the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is

built on the IEC 61691-1-1/IEEE 1076™ (VHDL) language and extends it to provide capabilities of writing and
simulating analog and mixed-signal models.
This document contains the complete reference of the IEC 61691-6/IEEE 1076.1 VHDL language, including the
unchanged portions of the base language and the extensions. Formally, IEC 61691-6:2009/IEEE Std 1076.1-2007 defines
the extensions only, and portions of text marked with change bars are either exclusively part of IEC 61691-6:2009/IEEE
Std 1076.1-2007 or define changes compared to IEC 61691-1-1:2004/IEEE Std 1076-2002. Portions of text not marked
with change bars are identical in this document and in IEC 61691-1-1:2004/IEEE Std 1076-2002.
The primary audience of this document are implementers of tools supporting the language and advanced users of the
language. The document is not intended to provide any introductory or tutorial information. It rather provides formal
definitions of language elements and language constructs.
The IEC 61691-6/IEEE 1076.1 language is a superset of the IEC 61691-1-1/IEEE 1076 language (VHDL). As such,
any legal IEC 61691-1-1/IEEE 1076 model is a IEC 61691-6/IEEE 1076.1 model, and any IEC 61691-6/IEEE
1076.1 tool shall provide the same simulation results as obtained with an IEC 61691-1-1/IEEE 1076 tool.
IEC 61691-1-1:2004/IEEE Std 1076-2002 and IEC 61691-6:2009/IEEE Std 1076.1-2007 will remain separate
standards. This means that when IEC 61691-1-1:2004/IEEE Std 1076-2002 is revised, IEC 61691-6:2009/IEEE Std
1076.1-2007 will not be automatically revised accordingly. A separate effort will be required to keep both standards
synchronized and to avoid inconsistencies.
0.2 Normative references
The following referenced documents are indispensable for the application of this document (i.e., they must be
understood and used, so each referenced document is cited in the text and its relationship to this document is
explained). For dated references, only the edition cited applies. For undated references, the latest edition of the
referenced document (including any amendments or corrigenda) applies.
This standard is dependent upon IEC 61691-1-1:2004/IEEE Std 1076-2002. In addition, certain definitions in this
document depend on IEEE Std 1076.2-1996, which describes via standard packages and definitions mathematical
functions that can be used within VHDL design units.
IEC 61691-1-1:2004 Behavioural languages - Part 1-1: VHDL language reference manual
2, 3, 4
IEEE Std 1076-2002, IEEE Standard VHDL Language Reference Manual.
_______
Information on references can be found in 0.2.
IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854, USA
(http://standards.ieee.org/). IEC publications are available from the Sales Department of the International Electrotechnical Commission, Case

Postale 131, 3, rue de Varembé, CH-1211, Genève 20, Switzerland/Suisse (http://www.iec.ch/).'
The IEEE standards or products referred to in this clause are trademarks of the Institute of Electrical and Electronics Engineers, Inc.
IEEE Std 1076-2002 was adopted as IEC 61691-1-1:2004.
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

– 2 – IEC 61691-6:2009(E)
IEEE Std 1076.1-2007(E)
IEEE Std 1076.2-1996 (Reaff 2002), IEEE Standard VHDL Mathematical Packages.
0.3 Structure and terminology of this standard
This standard is organized into clauses, each of which focuses on some particular area of the language.
Within each clause, individual constructs or concepts are discussed in each subclause.
Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of
the construct is described using one or more grammatical productions.
A set of paragraphs describing the meaning and restrictions of the construct in narrative form then follow.
In this document, the word shall is used to indicate a mandatory requirement. The word should is used to
indicate a recommendation. The word may is used to indicate a permissible action. The word can is used for
statements of possibility and capability.
Finally, each clause may end with examples, notes, and references to other pertinent clauses.
0.3.1 Syntactic description
The form of a VHDL description is described by means of context-free syntax using a simple variant of the
Backus-Naur Form; in particular:
a) Lowercase words in roman font, some containing embedded underlines, are used to denote syntactic
categories, for example:
formal_port_list
Whenever the name of a syntactic category is used, apart from the syntax rules themselves, spaces
take the place of underlines [thus, “formal port list” would appear in the narrative description when
referring to the syntactic category in item a)].
b) Boldface words are used to denote reserved words, for example:
array
Reserved words shall be used only in those places indicated by the syntax.
c) A production consists of a left-hand side, the symbol “::=” (which is read as “can be replaced by”),
and a right-hand side. The left-hand side of a production is always a syntactic category; the right-
hand side is a replacement rule. The meaning of a production is a textual-replacement rule: any
occurrence of the left-hand side may be replaced by an instance of the right-hand side.
d) A vertical bar (|) separates alternative items on the right-hand side of a production unless it occurs
immediately after an opening brace, in which case it stands for itself, as follows:
letter_or_digit ::= letter | digit
choices ::= choice { | choice }
In the first instance, an occurrence of “letter_or_digit” can be replaced by either “letter” or “digit.”
In the second case, “choices” can be replaced by a list of “choice,” separated by vertical bars [see
item f) for the meaning of braces].
e) Square brackets [ ] enclose optional items on the right-hand side of a production; thus, the following
two productions are equivalent:
return_statement ::= return [ expression ] ;
return_statement ::= return ; | return expression ;
Note, however, that the initial and terminal square brackets in the right-hand side of the production
for signatures (see 2.3.2) are part of the syntax of signatures and do not indicate that the entire right-
hand side is optional.
Published by IEC under licence from IEEE. © 2007 IEEE. All rights reserved.

IEEE Std 1076.1-2007(E)
f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may
appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive
rule. Thus, the following two productions are equivalent:
term ::= factor { multiplying_operator factor }
term ::= factor | term multiplying_operator factor
g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category
name without the italicized part. The italicized part is intended to convey some semantic informa-
tion. For example, type_name and subtype_name are both syntactically equivalent to name alone.
h) The term simple_name is used for any occurrence of an identifier that already denotes some
declared entity.
0.3.2 Semantic description
The meaning and restrictions of a particular construct are described with a set of narrative rules immediately
following the syntactic productions. I
...