IEC 62016:2003
(Main)Core model of the electronics domain
Core model of the electronics domain
Provides the semantics definitions for the categories of information related to electronic circuit designs. Each category of design information is modelled as an EXPRESS schema
General Information
Standards Content (Sample)
INTERNATIONAL IEC
STANDARD
First edition
2003-12
Core model of the electronics domain
Reference number
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INTERNATIONAL IEC
STANDARD 62016
First edition
2003-12
Core model of the electronics domain
© IEC 2003 – Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale
XH
International Electrotechnical Commission
Международная Электротехническая Комиссия
For price, see current catalogue
– 2 – 62016 IEC:2003(E)
CONTENTS
FOREWORD.5
INTRODUCTION.7
1 Scope and object.8
2 Reference documents.9
3 General modelling issues .9
3.1 Ownership and reference.9
3.2 Uniqueness by value .12
3.3 Default values.12
3.4 Optional versus empty sets .12
3.5 Model topology.12
4 Concepts.13
4.1 The information base.13
4.2 Global ports and global port bundles .13
4.3 Libraries.13
4.4 Cells.14
4.5 Clusters and cell representation sets.14
4.6 Cell representations.14
4.7 Master ports and master port bundles .14
4.8 Instances.15
4.9 Instance ports and instance port bundles .15
5 Connectivity.16
5.1 Logical connectivity.16
5.2 Structural connectivity with wide instances .17
5.3 Structural connectivity of connectivity views .19
6 The design hierarchy mechanism .21
6.1 The design hierarchy.21
6.2 Annotations.23
7 Core Model for electronic design .24
7.1 Libraries.24
7.2 Interfacing to cells.25
7.3 Cell definition hierarchies.27
7.4 Instantiation.27
7.5 Logical connectivity.28
7.6 Structural connectivity.28
7.7 Global connectivity.32
7.8 Design and configuration.33
7.9 Annotation.34
8 Core Model EXPRESS-G.34
8.1 Partial EXPRESS-G of cell .35
8.2 Partial EXPRESS-G of cell_representation .36
8.3 Partial EXPRESS-G of cluster .37
8.4 Partial EXPRESS-G of cluster_configuration .38
8.5 Partial EXPRESS-G of cluster_interface.39
8.6 Partial EXPRESS-G of connectivity_generic_bus .40
62016 IEC:2003(E) – 3 –
8.7 Partial EXPRESS-G of connectivity_generic_net .41
8.8 Partial EXPRESS-G of design .42
8.9 Partial EXPRESS-G of global_port .43
8.10 Partial EXPRESS-G of information_base.44
8.11 Partial EXPRESS-G of instance.45
8.12 Partial EXPRESS-G of instance_configuration.46
8.13 Partial EXPRESS-G of library.47
8.14 Partial EXPRESS-G of master_port_annotate.48
8.15 Partial EXPRESS-G of name_information.49
8.16 Partial EXPRESS-G of occurrence_annotate .50
8.17 Partial EXPRESS-G of occurrence_annotate .51
8.18 Partial EXPRESS-G of occurrence_annotate .52
8.19 Partial EXPRESS-G of occurrence_hierarchy_annotate.53
8.20 Partial EXPRESS-G of port_structure .54
8.21 Partial EXPRESS-G of property.55
8.22 Partial EXPRESS-G of property_override .56
8.23 Partial EXPRESS-G of signal .57
9 Core Model schemas.58
9.1 connectivity_structure_model.58
9.2 connectivity_view_model.59
9.3 design_hierarchy_model.60
9.4 design_management_model.62
9.5 documentation_model.63
9.6 hierarchy_model.64
9.7 information_base_model.67
9.8 library_model .68
9.9 logical_connectivity_model.69
9.10 support_definition_model.70
10 Core Model information model .72
10.1 connectivity_structure_model.72
10.2 design_hierarchy_model.89
10.3 documentation_model.114
10.4 hierarchy_model.116
10.5 information_base_model.157
10.6 support_definition_model.166
11 Index .188
Figure 1 – The owner relationship.10
Figure 2 – Owner relationship with multiple potential owners .11
Figure 3 – The reference mechanism .11
Figure 4 – Uniqueness by value .12
Figure 5 – An example of signal hierarchy .17
Figure 6 – A net joins a port on an instance in the commoned style .18
Figure 7 – A bus joins a port bundle on an instance in the commoned style .18
Figure 8 – A bus joins a port bundle on an instance in the fanned-out style .19
Figure 9 – Internal and external libraries.25
Figure 10 – Port bundling – 1.26
– 4 – 62016 IEC:2003(E)
Figure 11 – Port bundling – 2.26
Figure 12 – Instantiation .27
Figure 13 – Connectivity net .28
Figure 14 – Connectivity bus.29
Figure 15 – Connectivity bus – Commoning .29
Figure 16 – Connectivity bus – Logical equivalent of commoning .30
Figure 17 – Connectivity bus – Fanning-out .30
Figure 18 – Connectivity bus – Logical equivalent of fanning-out .31
Figure 19 – Connectivity bus-slice .31
Figure 20 – Connectivity ripper .
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