IEC 61189-5-1:2016

IEC 61189-5-1 ®
Edition 1.0 2016-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, printed boards and other interconnection
structures and assemblies –
Part 5-1: General test methods for materials and assemblies – Guidance for
printed board assemblies
Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres
structures d'interconnexion et ensembles –
Partie 5-1: Méthodes d'essai générales pour les matériaux et les assemblages –
Lignes directrices pour les assemblages de cartes à circuit imprimé

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IEC 61189-5-1 ®
Edition 1.0 2016-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Test methods for electrical materials, printed boards and other interconnection

structures and assemblies –
Part 5-1: General test methods for materials and assemblies – Guidance for

printed board assemblies
Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres

structures d'interconnexion et ensembles –

Partie 5-1: Méthodes d'essai générales pour les matériaux et les assemblages –

Lignes directrices pour les assemblages de cartes à circuit imprimé

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180 ISBN 978-2-8322-3506-5

– 2 – IEC 61189-5-1:2016 © IEC 2016
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 8
2 Normative references. 8
3 Accuracy, precision and resolution . 8
3.1 General . 8
3.2 Accuracy . 8
3.3 Precision . 9
3.4 Resolution. 10
3.5 Report . 10
3.6 Student’s t distribution . 10
3.7 Suggested uncertainty limits . 11
4 Catalogue of approved test methods . 12
5 List of contents of the IEC 61189-5 series . 12
Annex A (informative) Tests . 13
Annex B (informative) Guidance documents and handbooks . 15
B.1 General . 15
B.2 Handbook and guide to supplement IPC-J-STD-001 . 15
B.3 Guidelines for Electrically Conductive Surface Mount Adhesives (IPC-3406) . 15
B.4 Users Guide for Cleanliness of Unpopulated Printed Boards (IPC-5701) . 15
B.5 Guidelines for OEM’s in Determining Acceptable Levels of Cleanliness of
Unpopulated Printed Boards (IPC-5702) . 15
B.6 Surface Insulation Resistance Handbook (IPC-9201) . 16
B.7 Material and Process Characterisation / Qualification Test Protocol for
Assessing Electrochemical Performance (IPC-9202) . 16
B.8 User Guide for the IPC/IEC B52 Process Qualification Test Vehicle
(IPC-9203) . 16
B.9 PWB Assembly Soldering Process Guideline for Electronic Components
(IPC-9502) . 16
B.10 Aqueous Post Solder Cleaning Handbook (IPC-AC-62A) . 17
B.11 Guidelines for Cleaning of Printed Boards and Assemblies (IPC-CH-65A) . 17
B.12 Handbook (IPC-J-STD-005) . 17
B.13 Acceptability of Electronic Assemblies (IPC-HDBK-610) . 18
B.14 Guidelines for Design, Selection and Application of Conformal Coatings
(IPC-HDBK-830) . 18
B.15 Solder mask Handbook (IPC-HDBK-840) . 18
B.16 Guidelines and Requirements for Electrical Testing of Unpopulated Printed
Boards (IPC-9252) . 19
B.17 In-Process DPMO and Estimated Yield for PCAs (IPC-9261A) . 19
B.18 Assembly Soldering Process Guideline for Electronic Components
(IPC-9502 PWB) . 20
B.19 Users Guide for IPC-TM-650, Method 2.6.27, Thermal Stress, Convection
Reflow Assembly Simulation (IPC-9631) . 20
B.20 High Temperature Printed Board Flatness Guideline (IPC-9641) . 20
B.21 User Guide for the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament
(CAF) Resistance Test (Electrochemical Migration Testing) (IPC-9691A) . 21

B.22 Mechanical Shock Test Guidelines for Solder Joint Reliability (IPC-JEDEC-
9703) . 21
B.23 Printed Circuit Assembly Strain Gage Test Guideline (IPC-JEDEC-9704A) . 22
Bibliography . 23

Table 1 – Student’s t distribution . 11
Table A.1 – General test methods for materials and assemblies . 13

– 4 – IEC 61189-5-1:2016 © IEC 2016
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
TEST METHODS FOR ELECTRICAL MATERIALS,
PRINTED BOARDS AND OTHER INTERCONNECTION
STRUCTURES AND ASSEMBLIES –
Part 5-1: General test methods for materials and assemblies –
Guidance for printed board assemblies

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
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with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
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5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
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Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61189-5-1 has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this standard is based on the following documents:
CDV Report on voting
91/1273/CDV 91/1354/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

A list of all parts in the IEC 61189 series, published under the general title Test methods for
electrical materials, printed boards and other interconnection structures and assemblies, can
be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 6 – IEC 61189-5-1:2016 © IEC 2016
INTRODUCTION
IEC 61189 relates to test methods for printed boards and printed board assemblies, as well as
related materials or component robustness, irrespective of their method of manufacture.
The standard is divided into separate parts, covering information for the designer and the test
methodology engineer or technician. Each part has a specific focus. Methods are grouped
according to their application and numbered sequentially as they are developed and released.
In some instances test methods developed by other technical committees (for example, TC
104) have been reproduced from existing IEC standards in order to provide the reader with a
comprehensive set of test methods. When this situation occurs, it will be noted on the specific
test method. If the test method is reproduced with minor revisions, those paragraphs that are
different are identified.
This part of IEC 61189 contains test methods for evaluating printed board assemblies as well
as materials used in the manufacture of electronic assemblies. The methods are self-
contained, with sufficient detail and description so as to achieve uniformity and reproducibility
in the procedures and test methodologies.
It was decided by TC 91 that the contents of IEC 61189-5 and IEC 61189-6 be merged into a
series of documents in the following way:
IEC 61189-5-1, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-1: General test methods for materials and
assemblies – Guidance for printed board assemblies
IEC 61189-5-2:2015, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-2: General test methods for materials and
assemblies – Soldering flux for printed board assemblies
IEC 61189-5-3:2015, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-3: General test methods for materials and
assemblies – Soldering paste for printed board assemblies
IEC 61189-5-4:2015, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-4: General test methods for materials and
assemblies – Solder alloys and fluxed and non-fluxed solid wire for printed board assemblies
IEC 61189-5-501:—, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-501: General test methods for materials
and assemblies – Surface insulation resistance (SIR) testing of solder fluxes
IEC 61189-5-502:—, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-502: General test methods for materials
and assemblies – SIR testing of assemblies
IEC 61189-5-503:—, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-503: General test methods for materials
and assemblies – Conductive Anodic Filaments (CAF) testing of circuit boards
IEC 61189-5-504:—, Test methods for electrical materials, printed boards and other
interconnection structures and assemblies – Part 5-504: General test methods for materials
and assemblies – Process ionic contamination testing
____________
Under consideration.
The tests shown in this standard are grouped according to the following principles:
P: preparation/conditioning methods
V: visual test methods
D: dimensional test methods
C: chemical test methods
M: mechanical test methods
E: electrical test methods
N: environmental test methods
X: miscellaneous test methods including process control tests for the assembly process
To facilitate reference to the tests, to retain consistency of presentation and to provide for
future expansion, each test is identified by a number (assigned sequentially) added to the
prefix (group code) letter showing the group to which the test method belongs.
The test method numbers have no significance with respect to an eventual test sequence.
This responsibility rests with the relevant specification that calls for the method being
performed. The relevant specification, in most instances, also describes pass/fail criteria.
The letter and number combinations are for reference purposes to be used by the relevant
specification. Thus, "5-2C01" represents the first chemical test method described in
IEC 61189-5-2.
In short, in this example, 5-2 is the number of the part of IEC 61189, C is the group of
methods, and 01 is the test number.
A list of all test methods included in the above-mentioned documents, is given in Annex A.
This annex will be reissued whenever new tests are introduced.

– 8 – IEC 61189-5-1:2016 © IEC 2016
TEST METHODS FOR ELECTRICAL MATERIALS,
PRINTED BOARDS AND OTHER INTERCONNECTION
STRUCTURES AND ASSEMBLIES –
Part 5-1: General test methods for materials and assemblies –
Guidance for printed board assemblies

1 Scope
This part of IEC 61189 is a catalogue of test methods representing methodologies and
procedures that can be applied to test printed board assemblies.
This part of IEC 61189 contains the types of content of the IEC 61189-5 series, as well as
guidance documents and handbooks for printed board assemblies.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their
content constitutes requirements of this document. For dated references, only the edition
cited applies. For undated references, the latest edition of the referenced document (including
any amendments) applies.
There are no normative references in this document.
3 Accuracy, precision and resolution
3.1 General
Measurement errors and uncertainties are inherent in all measurement processes. The
information given below enables valid estimates of the amount of error and uncertainty to be
taken into account.
Test data serve a number of purposes which include
• monitoring of a process;
• enhancing of confidence in quality conformance;
• arbitration between customer and supplier.
In any of these circumstances, it is essential that confidence can be placed upon the test data
in terms of
• accuracy: calibration of the test instruments and/or system;
• precision: the repeatability and uncertainty of the measurement;
• resolution: the suitability of the test instrument and/or system.
3.2 Accuracy
The regime by which routine calibration of the test equipment is undertaken shall be clearly
stated in the quality documentation of the supplier or agency conducting the test and shall
meet the requirements of ISO 9001 or equivalent (see Bibliography).

The calibration shall be conducted by an agency having accreditation to a national or
international measurement standards institute. There should be an uninterrupted chain of
calibration to a national or international standard.
Where calibration to a national or international standard is not possible, round-robin
techniques may be used and documented to enhance confidence in measurement accuracy.
The calibration interval shall normally be one year. Equipment consistently found to be
outside acceptable limits of accuracy shall be subject to shortened calibration intervals.
Equipment consistently found to be well within acceptable limits may be subject to relaxed
calibration intervals.
A record of the calibration and maintenance history shall be maintained for each instrument.
These records should state the uncertainty of the calibration technique (in ±% deviation) in
order that uncertainties of measurement can be aggregated and determined.
A procedure shall be implemented to resolve any situation where an instrument is found to be
outside calibration limits.
3.3 Precision
The uncertainty budget of any measurement technique is made up of both systematic and
random uncertainties. All estimates shall be based upon a single confidence level, the
minimum being 95 %.
Systematic uncertainties are usually the predominant contributor and will include all
uncertainties not subject to random fluctuation. These include
• calibration uncertainties;
• errors due to the use of an instrument under conditions which differ from those under
which it was calibrated;
• errors in the graduation of a scale of an analogue meter (scale shape error).
Random uncertainties result from numerous sources but can be deduced from repeated
measurement of a standard item. Therefore, it is not necessary to isolate the individual
contributions. These may include
• random fluctuations such as those due to the variation of an influence parameter.
Typically, changes in atmospheric conditions reduce the repeatability of a measurement;
• uncertainty in discrimination, such as setting a pointer to a fiducial mark or interpolating
between graduations on an analogue scale.
Aggregation of uncertainties: Geometric addition (root-sum-square) of uncertainties may be
used in most cases. An interpolation error is normally added separately and may be accepted
as being 20 % of the difference between the finest graduations of the scale of the instrument.
2 2
U = ± (U + U ) + U
t s r i
where
U is the total uncertainty;
t
U is the systematic uncertainty;
s
U is the random uncertainty;
r
U is the interpolation error.
i
– 10 – IEC 61189-5-1:2016 © IEC 2016
Determination of random uncertainties: Random uncertainty can be determined by repeated
measurement of a parameter and subsequent statistical manipulation of the measured data.
The technique assumes that the data exhibits a normal (Gaussian) distribution.
t × σ
U =
r
n
where
U is the random uncertainty;
r
n is the sample size;
t is the percentage point of the t distribution as shown in Table 1;
σ is the standard deviation (σ ).
n–1
3.4 Resolution
It is paramount that the test equipment used is capable of sufficient resolution. Measurement
systems used should be capable of resolving 10 % (or better) of the test limit tolerance.
It is accepted that some technologies will place a physical limitation upon resolution (for
example, optical resolution).
3.5 Report
In addition to requirements detailed in the test specification, the report shall detail
a) the test method used;
b) the identity of the sample(s);
c) the test instrumentation;
d) the specified limit(s);
e) an estimate of measurement uncertainty and resultant working limit(s) for the test;
f) the detailed test results;
g) the test date and operators’ signature.
3.6 Student’s t distribution
Table 1 gives values of the factor t for 95 % and 99 % confidence levels, as a function of the
number of measurements.
Table 1 – Student’s t distribution
Sample t value t value Sample t value t value
size 95 % 99 % size 95 % 99 %
2 12,7 63,7 14 2,16 3,01
3 4,3 9,92 15 2,14 2,98
4 3,18 5,84 16 2,13 2,95
5 2,78 4,6 17 2,12 2,92
6 2,57 4,03 18 2,11 2,9
7 2,45 3,71 19 2,1 2,88
8 2,36 3,5 20 2,09 2,86
9 2,31 3,36 21 2,08 2,83
10 2,26 3,25 22 2,075 2,82
11 2,23 3,17 23 2,07 2,81
12 2,2 3,11 24 2,065 2,8
13 2,18 3,05 25 2,06 2,79
3.7 Suggested uncertainty limits
The following target uncertainties are suggested:
a) Voltage < 1 kV: ± 1,5 %
b) Voltage > 1 kV: ± 2,5 %
c) Current < 20 A: ± 1,5 %
d) Current > 20 A: ± 2,5 %
Resistance
e) Earth and continuity: ± 10 %
f) Insulation: ± 10 %
g) Frequency: ± 0,2 %
Time
h) Interval < 60 s: ± 1 s
i) Interval > 60 s: ± 2 %
j) Mass < 10 g: ± 0,5 %
k) Mass 10 g to 100 g: ± 1 %
l) Mass > 100 g: ± 2 %
m) Force: ± 2 %
n) Dimension < 25 mm: ± 0,5 %
o) Dimension > 25 mm: ± 0,1 mm
p) Temperature < 100 °C: ± 1,5 %
q) Temperature > 100 °C: ± 3,5 %
r) Humidity (30 – 75) % RH: ± 5 % RH
Plating thicknesses
s) Backscatter method: ± 10 %
– 12 – IEC 61189-5-1:2016 © IEC 2016
t) Microsection: ± 2 µm
u) Ionic contamination: ± 10 %
4 Catalogue of approved test methods
This standard provides specific test methods in complete detail to permit implementation with
minimal cross-referencing to other specific procedures. The use of generic conditioning
exposures is accomplished in the methods by reference, for example, to those described in
IEC 61189-1 and IEC 60068-1, and, when applicable, is a mandatory part of the test method
standard.
Each method has its own title, number and revision status to accommodate updating and
improving the methods as industry requirements change or demand new methodology. The
methods are organized in test method groups and individual tests.
5 List of contents of the IEC 61189-5 series
The types of content of existing and planned standards in the IEC 61189-5 series is described
in Annex A.
NOTE The details of the standards "under consideration" are not yet available.

Annex A
(informative)
Tests
Table A.1 gives a summary of the existing tests and of the tests under development.
Table A.1 – General test methods for materials and assemblies
IEC standard Designation Test
IEC 61189-5-2 C: Chemical test methods
5-2C01 Corrosion, flux
5-2C02 Determination of acid value of liquid soldering flux potentiometric and visual
titration methods
5-2C03 Acid number of rosin
5-2C04 Determination of halides in fluxes, silver chromate method
5-2C05 Solids content, flux
5-2C06 Quantitative determination of halide content in fluxes (chloride and bromide)
5-2C07 Qualitative analysis of fluorides and fluxes by spot test
5-2C08 Quantitative determination of fluoride concentration in fluxes
5-2C09 Specific gravity
5-2C10 Flux induced corrosion (copper mirror method)
X: Miscellaneous test methods
5-2X01 Liquid flux activity, wetting balance method
5-2X02 Spread test, liquid or extracted solder flux, solder paste and extracted cored
wires or preforms
5-2X03 Flux residues – Tackiness after drying

IEC 61189-5-3 X: Miscellaneous test methods
5-3X01 Paste flux viscosity – T-Bar spindle method
5-3X02 Spread test, extracted solder flux, paste flux and solder paste
5-3X03 Solder paste viscosity – T-Bar spin spindle method (applicable for 300 Pa•s to
1 600 Pa•s)
5-3X04 Solder paste viscosity – T-Bar spindle method (applicable to 300 Pa•s)
5-3X05 Solder paste viscosity – Spiral pump method (applicable for 300 Pa•s to
1 600 Pa•s)
5-3X06 Solder paste viscosity – Spiral pump method (applicable to 300 Pa•s)
5-3X07 Solder paste – Slump test
5-3X08 Solder paste – Solder ball test
5-3X09 Solder paste – Tack test
5-3X10 Solder paste – Wetting test
5-3X11 Determination of solder powder particle size distribution – Screen method for
types
5-3X12 Solder powder particle size distribution – Measuring microscope method
5-3X13 Solder powder particle size distribution – Optical image analyser method
5-3X14 Solder powder particle size distribution – Measuring laser diffraction method
5-3X15 Determination of maximum solder powder particle size
5-3X16 Solder paste metal content by weight

– 14 – IEC 61189-5-1:2016 © IEC 2016
IEC standard Designation Test
IEC 61189-5-4 C: Chemical test methods
5-4C01 Determination of the percentage of flux on/in flux-coated and/or flux-cored
solder
X: Mechanical test methods
5-4X01 Spread test, extracted cored wires or preforms
5-4X02 Spitting test of flux-cored wire solder
5-4X03 Solder pool test
IEC 61189-5-501 Under consideration

IEC 61189-5-502 Under consideration

IEC 61189-5-503 Under consideration

IEC 61189-5-504 Under consideration

Annex B
(informative)
Guidance documents and handbooks
B.1 General
The documents listed in Clauses B.2 to B.23 relate to the specific soldering materials or test
methods employed.
B.2 Handbook and guide to supplement IPC-J-STD-001
IPC-J-STD-001 and IPC-HDBK-001 do not exclude any acceptable process used to make the
electrical connections, as long as the methods used will produce completed solder joints
conforming to the acceptability requirements of the IPC-J-STD-001.
This handbook describes materials, methods, and verification criteria that, when applied as
recommended or required, will produce quality soldered electrical and electronic assemblies.
The intent of this handbook is to explain the ‘‘how-to,’’ the ‘‘why,’’ and fundamentals for these
processes, in addition to implementing control over processes rather than depending on end-
item inspection to determine product quality.
B.3 Guidelines for Electrically Conductive Surface Mount Adhesives (IPC-3406)
This document covers guidelines for selecting electrically conductive adhesives for use in
assembly of components to printed circuit boards (PCB) or similar wiring inter-connect
systems. The focus is on the use of adhesives as solder alternatives. The process discussion
attempts to stay within the bounds of the existing solder assembly infrastructure as much as
possible. Both major types of adhesives, isotropic (conducting equally in all directions) and
anisotropic (unidirectional conductivity), are covered. The two major divisions of polymer
adhesives, thermosets and thermoplastics, are described.
B.4 Users Guide for Cleanliness of Unpopulated Printed Boards (IPC-5701)
If you are in the electronics industry, sooner or later you have to, will, or should deal with the
issue of the cleanliness of the unpopulated printed circuit boards (bare boards). Residues on
circuit boards are directly related to the reliability of the produced hardware and can result in
serious failures if not monitored and controlled.
This document is the product of the IPC Bare Board Cleanliness Assessment Task Group and
was drafted to provide individuals who deal with these issues some guidance on how the
issues should be approached and specified in purchase documents.
B.5 Guidelines for OEM’s in Determining Acceptable Levels of Cleanliness of
Unpopulated Printed Boards (IPC-5702)
Every electronics manufacturer, whether an original equipment manufacturer (OEM) or
contract manufacturer (CM), will be faced with determining if the unpopulated printed boards
used in the finished assembly have an adequate level of cleanliness. The question of ‘‘how
clean is clean enough’’ has been asked repeatedly in the last decade in many IPC committees.
This is a very complex topic, with many critical considerations. For this reason there is not an
unique methodology that determines acceptability. This document was developed as guidance
for the individual(s) responsible for determining these criteria for their company.

– 16 – IEC 61189-5-1:2016 © IEC 2016
IPC-5701 covers many aspects of how cleanliness is measured on printed boards, as well as
many critical factors to consider when specifying board cleanliness in purchasing documents.
This reference, and associated technical papers, show the many inadequacies of current test
methodologies, as well as explaining why there are no ‘‘golden numbers’’ for cleanliness.
What is acceptably clean for one segment of the industry may be unacceptable for more
demanding segments of the industry (e.g., medical or aerospace).
B.6 Surface Insulation Resistance Handbook (IPC-9201)
This document is intended to cover the broad spectrum of temperature-humidity (TH) testing,
associated terminology, and suggested techniques for proper surface insulation resistance
testing as defined in IEC 61189-5-5, Test Methods 5E01 and 5E02.
B.7 Material and Process Characterisation / Qualification Test Protocol for
Assessing Electrochemical Performance (IPC-9202)
This material and process characterization/qualification test records changes in surface
insulation resistance (SIR) on a representative sample of a printed circuit assembly (PCA). It
quantifies any deleterious effects that might arise from solder flux or other process residues
left on external surfaces after soldering, which can cause unwanted electro-chemical
reactions that grossly affect reliability.
It uses test vehicles that are intended to be representative of the electronic circuits that are in
production. It is a test yielding both quantitative and qualitative data.
This test may be used for Process Qualification, demonstrating that a proposed manufacturing
process or process change can produce hardware with acceptable end-item performance
related to cleanliness. Changes may involve any assembly process step, or a change in the
printed board supplier, solder mask or metallization, soldering material supplier, conformal
coating, etc. The test vehicle construction will vary depending upon the type of change being
evaluated.
B.8 User Guide for the IPC/IEC B52 Process Qualification Test Vehicle
(IPC-9203)
The electronics manufacturing process is often very complex, with dozens of variables that
impact the quality and reliability of the manufactured assemblies in the end use environment.
Two of the important variables for consideration are the kinds of residues that remain on the
electronic assembly and the effects that these residues have on reliability. These two
variables are most often referred to in discussions on assembly “cleanliness”.
Whilst there are several different ways to measure residues and their effects on electrical
performance, the two most common approaches in the industry are ionic cleanliness testing,
for determination of ionic residues, and surface insulation resistance (SIR) testing, for the
evaluation of electrochemical failures in humid environments.
This document focuses on the IPC-B-52 standard test assembly and how it is used as an
evaluation tool for electronics manufacturing processes from a “cleanliness” perspective.
B.9 PWB Assembly Soldering Process Guideline for Electronic Components
(IPC-9502)
This document describes manufacturing solder process limits that components subjected to
IPC-9501, IPC-9503, IPC-9504 and J-STD-020 would survive. It does not include optimum
conditions for assembly, but rather guides to assure components are not damaged.

This document applies to both surface-mount (SM) and through-hole (TH) components that
are wave soldered, reflowed or hand soldered. This document is intended to complement
other industry documents, listed in applicable documents.
B.10 Aqueous Post Solder Cleaning Handbook (IPC-AC-62A)
This handbook addresses aqueous cleaning of electrical/electronic parts and application tools
after soldering.
The content of the text is intended to provide a basic understanding of the subject and to
serve as a guide to users or prospective users of aqueous cleaning technology, allowing
selection or improvement of aqueous cleaning processes.
B.11 Guidelines for Cleaning of Printed Boards and Assemblies (IPC-CH-65A)
This manual is a road map for current and developing cleaning issues, rather than to function
as a highly detailed document for all areas touched upon. In areas of cleaning where recent
detailed IPC manuals already exist, the relevant sections in IPC-CH-65A will contain only
sufficient information to make the reader reasonably knowledgeable. This guideline manual
refers the reader to appropriate existing IPC documents (where they exist) for in-depth
information on the particular subject. An example of such a reference IPC manual is IPC-AC-
62, Aqueous Cleaning Handbook. It is only where existing IPC documents are not available
that IPC-CH-65A will expand information beyond the basics in order to cover what is currently
known about the subject. A benefit of this approach is that the manual does not become
unwieldy and tends to foster a user-friendly environment.
Both bare board fabrication and assembly cleanliness issues are addressed. The fabrication
and assembly sections are separated for ease of access. In the original IPC-CH-65, these
sections were very much intertwined. However, it was recognized that for a subject such as
the required cleanliness of finished bare boards, basically redundant teachings are required
for both the fabrication and assembly sections.
B.12 Handbook (IPC-J-STD-005)
This handbook is a companion to the solder paste standard J-STD-005 and should be
considered to be a guide to help assess the applicability of a solder paste for its use in
surface-mount technology (SMT) processes. This document also suggests some test methods
that can help with designing and testing solder pastes. It is intended for use by both vendors
and users of solder paste.
Solder pastes are unique materials, whose performance in a surface-mount process depends
on a variety of variables, many of them interacting. J-STD-005 provides test methods for
classification of solder paste based on the use of a variety of testing techniques. However,
these solder paste classifications do not have a direct correlation to identify the type and
characteristics of a specific solder paste that is needed in any given SMT assembly process.
This document has been written as a guide to assess the applicability of a solder paste for a
specific process, given the tremendous number of permutations of different materials,
atmospheres and process variables currently available.
Where appropriate, references are given to papers and documents with further information.
Due to the sheer number of possible interacting factors, specific solder paste selection criteria
cannot be given. The solder paste selected and the assembly process used will need to form
solder connections that meet the requirements of industry standards such as J-STD-001
and/or IPC-A-610.
– 18 – IEC 61189-5-1:2016 © IEC 2016
B.13 Acceptability of Electronic Assemblies (IPC-HDBK-610)
This handbook is a companion reference to IPC-A-610C and IPC-A-610C Amendment 1 and
was prepared using them. The amendment provides additional criteria and clarification
statements. The amendment is included with this handbook following Appendix C and can be
downloaded free of charge from the IPC website at the following link:
http://www.ipc.org/TOC/IPC-HDBK-610-w-Amend-1.pdf.
The intent of this handbook is to explain the technical rationale for selected acceptability,
process indicator and defect criteria and to provide information regarding assembly
technology. Additional information is provided to give a broader understanding of the process
considerations needed for the production of accept
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