IEC TR 62433-4-1:2025

IEC TR 62433-4-1 ®
Edition 1.0 2025-08
TECHNICAL
REPORT
EMC IC modelling -
Part 4-1: Use of ICIM-CI model to predict the IC conducted immunity in a PCB
ICS 31.200  ISBN 978-2-8327-0663-3

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CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms, definitions and abbreviations . 5
3.1 Terms and definitions . 5
3.2 Abbreviated terms. 6
4 Philosophy . 7
5 ICIM-CI model extraction flow . 7
5.1 General . 7
5.2 Failure criteria definition . 9
5.3 PDN extraction . 10
5.3.1 General. 10
5.3.2 PDN extraction from SYZ-parameters measurements . 11
5.3.3 PDN extraction from existing models . 13
5.3.4 PDN extraction from package geometry import and simulation model
generator . 14
5.4 Conducted immunity characterization. 15
5.5 IB extraction . 18
5.6 Validation of the ICIM-CI model . 23
5.7 Final ICIM-CI model . 24
6 Use of ICIM-CI model for immunity prediction on an application PCB . 25
6.1 General . 25
6.2 Calculation of the power flowing into the under-test IC pin . 26
Annex A (informative) Example of ICIM-CI model written as SPICE subckt . 29
A.1 General . 29
A.2 Example . 29
Annex B (informative) Example of conducted immunity calculation applied to a LIN
transceiver used in an automotive application . 33
B.1 General . 33
B.2 LIN driver ICIM-CI model . 33
B.3 Application board modelling . 34
B.4 Conducted immunity calculation . 36
B.4.1 Calculation without non-linear element . 36
B.4.2 Calculation with non-linear element . 37
Bibliography . 39

Figure 1 – Example of ICIM-CI model structure . 8
Figure 2 – ICIM-CI model extraction flow proposal . 8
Figure 3 – Pin description of the IC under test . 9
Figure 4 – Example of PCB dedicated to S-parameters measurement . 11
Figure 5 – Example of reflection coefficient measurement performed on the IC
under test . 12
Figure 6 – Example of LIN pin impedances depending on state . 12
Figure 7 – Example of transmission coefficient measurement performed on the IC

under test . 13
Figure 8 – Structure of IBIS model . 14
Figure 9 – Example of packaging extraction tool . 14
Figure 10 – Example of parasitic elements computation with an advanced packaging
extraction tool . 15
Figure 11 – Example of DPI test setup . 15
Figure 12 – Example of PCB dedicated to DPI test . 16
Figure 13 – Example of a configuration for LIN driver DPI measurement . 17
Figure 14 – Example of incident power at IB extraction board LIN input during DPI
measurement of the initial configuration for each OO . 17
Figure 15 – Example of block diagram for DPI setup modelling . 19
Figure 16 – Example of DPI SPICE modelling to calculated power transmitted to VBAT
pin during a 0 dBm power injection at IB extraction board input . 20
Figure 17 – Example of IB extraction board trace modelling using SPICE subcircuit
model . 20
Figure 18 – Example of transmitted power and voltage magnitude calculated at VBAT
pin of the IC under test during DPI SPICE simulation performed at 0 dBm . 21
Figure 19 – Example of comparison incident vs transmitted power for a DPI on + 12 V
board pin . 22
Figure 20 – Example of transmitted power calculated at LIN pin input during DPI
SPICE simulation performed at 0 dBm: validation vs IB extraction configuration . 23
Figure 21 – Example of incident power calculated at LIN pin input inducing a fault on
LIN pin during DPI SPICE validation simulation: calculation vs measurement . 24
Figure 22 – ICIM-CI XML writer . 25
Figure 23 – Example of white box construction of a DPI setup modelling at
application level . 26
Figure 24 – Example of transmitted power calculation at application board . 27
Figure 25 – Example of voltage V and current I calculation . 27
Figure 26 – Example of fault prediction . 28
Figure A.1 – Example of ICIM-CI model written as SPICE subcircuit . 32
Figure B.1 – Example of an automotive application board . 33
Figure B.2 – LIN driver ICIM-CI model . 34
Figure B.3 – Example of an automotive application board schematic. 35
Figure B.4 – Example of an automotive application board 3D modelling . 35
Figure B.5 – Example of conducted immunity calculation modelling . 36
Figure B.6 – Example of comparison of the calculated transmitted power with the IB
and the RF power injection measurement – without non-linear element- . 37
Figure B.7 – Example of comparison of the calculated transmitted power with the IB
and the RF power injection measurement – with non-linear elements- . 37
Figure B.8 – Example of current and voltage calculation during a transient analysis . 38
Figure B.9 – Example of calculated current and voltage at 10 MHz (Nyquist sampling) . 38

Table 1 – Examples of OO, failure criteria and DI for different types of IC . 9
Table 2 – Examples of OO, failure criteria and DI for the IC under test . 10
Table B.1 – OO, failure criteria and DI for the LIN transceiver under test . 34

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
EMC IC modelling -
Part 4-1: Use of ICIM-CI model to predict
the IC conducted immunity in a PCB

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
respect thereof. As of the date of publication of this document, IEC [had/had not] received notice of (a) patent(s),
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https://patents.iec.ch. IEC shall not be held responsible for identifying any or all such patent rights.
IEC TR 62433-4-1 has been prepared by subcommittee 47A: Integrated circuits, of IEC
technical committee 47: Semiconductor devices. It is a Technical Report.
The text of this Technical Report is based on the following documents:
Draft Report on voting
47A/1191/DTR 47A/1197/RVDTR
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this Technical Report is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts of the IEC 62433 series, published under the general title EMC IC modelling,
can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
1 Scope
This part of IEC 62433-4 provides an overview of good practices to extract an ICIM-CI model
from measurements and to build a numerical model of the PCB in which the ICIM-CI model is
used to predict RF immunity of an IC in its application PCB.
This document also discusses factors which can be considered to obtain proper results in an
ICIM-CI model extraction and use of the actual model at the PCB level.
2 Normative references
There are no normative references in this document.
3 Terms, definitions and abbreviations
3.1 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
– IEC Electropedia: available at https://www.electropedia.org/
– ISO Online browsing platform: available at https://www.iso.org/obp
3.1.1
PDN
Passive Distribution Network
block that describes the impedance network of one or more ports of the integrated circuit
[SOURCE: IEC 62433-4:2016, 3.1.13]
3.1.2
IB
Immunity Behaviour
block that describes the internal immunity behaviour of the IC
[SOURCE: IEC 62433-4:2016, 3.1.14]
3.1.3
DI
Disturbance Input
input terminal for the injection of RF disturbances
Note 1 to entry: It could be any pin of IC, an input, supply or an output.
[SOURCE: IEC 62433-4:2016, 3.1.9]
3.1.4
DO
Disturbance Output
terminal whose load influences the impedance of DI terminal, and/or the transfer characteristics
of PDN, and that outputs a part of the disturbance received on the DI terminals
[SOURCE: IEC 62433-4:2016, 3.1.10]
3.1.5
OO
Observable Output
output terminal where the immunity criteria are monitored during the test
[SOURCE: IEC 62433-4:2016, 3.1.11]
3.1.6
GND
Ground terminal
terminal that is used as reference for return path
[SOURCE: IEC 62433-4:2016, 3.1.12]
3.1.7
internal terminal
terminal of an integrated circuit macro-model's component which interfaces the component to
other components of the integrated circuit macro-model
[SOURCE: IEC 62433-4:2016, 3.1.5]
3.1.8
external terminal
terminal of an integrated circuit macro-model which interfaces the model to the external
environment of the integrated circuit
[SOURCE: IEC 62433-4:2016, 3.1.4]
3.2 Abbreviated terms
ADC Analog to digital converter
CAD Computer-aided design
CAN Controller area network
DPI Direct RF power injection
DUT Device under test
EM Electromagnetic
IBIS Input/output Buffer Information Specification
JTAG Join test action group
LDO Low dropout
LED Light-emitting diode
LIN Local interconnect network
PCB Printed circuit board
PWB Printed wiring board
PWM Pulse width modulation
RFIP Radio Frequency Injection Probe
SMA Sub-miniature A-version
SOLT Short-Open-load-Thru
S-Parameter Scattering parameter
SPICE Simulation program with integrated circuit emphasis
TL Transmission line
TRL Thru Reflect Line
VNA Vector network analyser
4 Philosophy
This document proposes an overview of methods:
– to extract an ICIM-CI model,
– to calculate the current, voltage or power conducted into an IC pin during a direct power
injection (DPI) test according to IEC 62132-4 [1] performed at test board level,
– to compare the calculated current, voltage or power to the Immunity Behaviour (IB) data of
the ICIM-CI model,
– to predict the immunity level of an IC in a PCB.
The use of ICIM-CI model allows the prediction of the RF immunity behaviour of an IC at PCB
level. The simulation results of this model are, for example, used to predict the RF immunity of
a second source IC without performing requalification test at PCB level.
5 ICIM-CI model extraction flow
5.1 General
The ICIM-CI model consists of a set of data describing two parts:
– PDN: the Passive Distribution Network describes the path which conducts the disturbances
from the external environment to the internal IC blocks. The PDN is a multi-port circuit. It is
composed of four different terminals:
• DI: Terminals to which disturbances are applied,
• DO: Terminals that can influence the impedance of the DI terminals and consequently
receive a part of the disturbance applied on the DI terminals,
• GND: PDN has one or more ground terminals (such as digital ground, analogue ground),
• Internal terminals: Terminals that can influence the impedance of the DI terminals and
are internal to the IC (at chip-level).
– IB: The Immunity Behaviour describes how the IC reacts to the applied disturbances
(referenced to one ground terminal of the PDN). The immunity criterion is set on terminals
that are called Observable Output (OO). These OO could be associated or not to the various
DI, depending on the configuration of the IC.
NOTE 1 DI, DO, OO and GND terminals are external terminals and are interfaced at pin level. These pins connect
to the external environment of the IC.
NOTE 2 OO terminals link the PDN to the IB. These terminals are used to obtain the IB by monitoring the immunity
criterion. In Figure 1, they are virtually represented (internally) on the PDN of the ICIM-CI macro-model.
Figure 1 illustrates an example of ICIM-CI model structure.
___________
Numbers in square brackets refer to the Bibliography.
Figure 1 – Example of ICIM-CI model structure
The ICIM-CI model extraction flow is described in Clause 7 of IEC 62433-4:2016 [2]. The
validation of the extracted model is described in Clause 8 of IEC 62433-4:2016. The flow
described in Figure 2 groups these two steps to arrive at a final model. This flow is presented
in [1] and will be described in detail in the following subclauses. Some ICIM-CI model extraction
examples could be found in [4], [5], [6], [7] and [8].

Figure 2 – ICIM-CI model extraction flow proposal
NOTE RFIP technique [9] is described in Annex G of IEC 62433-4:2016. This method allows to obtain the voltage
and the current at the IC pin where the power is injected.
5.2 Failure criteria definition
The failure criteria could be multiple. They are based on requirements fixed at application level.
Failure criteria are very dependent of the type of the IC. Table 1 gives some examples of OO,
failure criteria and DI for different types of IC.
Table 1 – Examples of OO, failure criteria and DI for different types of IC
IC type OO Failure criterion DI pin
Communication Bus RX, TX, Signal tolerance in time domain Communication lines, Power
transceivers communication
lines
Voltage regulator Output Tolerance of output voltage Input, output (if external)
Reset Reset generation
Power components Output Tolerance of output voltage or Input, output if external
tolerance in time domain if
switched
Logic gate circuits Output State change Power, Input
Analogue circuits Output Tolerance in time domain Input pin
ADC Output conversion error Power, input
Sensors Output Tolerance in time domain Power, output, input when present
Microcontroller Memory data corruption Power lines, input, output
Reset Activation
Output Tolerance in time domain

The IC under test which will be used in this document to illustrate the ICIM-CI extraction flow is
a LIN transceiver embedding a voltage regulator. Figure 3 describes the pins of the IC under
test.
Key
1 V : Battery supply
BAT
2 EN: Enable input
3 GND: ground
4 LIN: LIN bus line
5 RXD: LIN received data output
6 TXD: LIN transmitted data input
7 RSTN: Reset output (active low)
8 V : Voltage regulator output
CC
Figure 3 – Pin description of the IC under test
The pins selected for conducted immunity test and for the PDN extraction are to be identified
carefully. Typically, the following physical IC pins are considered as DI:
– IC pins with a direct access to the PCB connector,
– IC pins with an access to the PCB connector through filtering components or devices as
supply lines,
– IC pins sensitive to external RF disturbance such as analogue I/O pins (current sensing,
capacitive sensor, etc).
Typically, the following physical IC pins are considered as DO:
– IC pins which have an influence on the disturbance propagation path identified during the
application review and IC functional block diagram analysis.
Table 2 gives some examples of OO, failure criteria, failure monitoring, DI and DO for the IC
under test. OO, DI and DO are referenced to the same ground pin GND.
Table 2 – Examples of OO, failure criteria and DI for the IC under test
OO Nominal behaviour Failure Failure DI DO
criteria monitoring
LIN PWM with same ± 5 us Mask on V , LIN V
BAT CC
characteristics (frequency, oscilloscope
± 2,5 V
duty cycle) as TX signal
with a magnitude of 12 V.
RX PWM with same ± 5 us Mask on V , LIN V
BAT CC
characteristics (frequency, oscilloscope
± 1 V
duty cycle) as TX signal
with a magnitude of 5 V.
VCC 5 V DC ± 0,2 V Mean Value V
BAT
RSTN 5 V DC ± 0,2 V Mean Value V
BAT
5.3 PDN extraction
5.3.1 General
The PDN is constituted by passive elements representing the impedance of the disturbance
path. This path is mainly constituted by the parasitic RLC elements of the package including
the assembly of the die on a lead frame or on a substrate through a set of bonding wires.
The PDN describes the linear behaviour of the IC. The non-linear effects are not considered in
the PDN of the ICIM-CI macro-model. Therefore, impedance measurements are carried out in
the typical operating conditions in a steady state mode. The proposed PDN of ICIM-CI model is
limited to a level so that the protection devices are not triggered. The activation of internal
protection devices would induce non-linearity in the model definition, which is not considered
in the PDN. However, non-linear effects are inherently considered in the IB.
The PDN is extracted with mandatory external components as specified by the manufacturer.
There are several methods to extract the PDN of an IC:
– PDN extraction from SYZ-parameters measurements;
– PDN extraction from available simulation models;
– PDN extraction from package geometry.
5.3.2 PDN extraction from SYZ-parameters measurements
S, Y or Z-parameters measurements are achieved with a VNA (Vector Network Analyser) on a
PCB dedicated to this specific measurement or shared with the PCB developed for IB extraction
as illustrated in Figure 4. In lower frequencies, impedance analyser could be used for more
accurate measurements.
Key
1 V S-parameter port
BAT
2 V S-parameter port
CC
3 LIN S-parameter port
Figure 4 – Example of PCB dedicated to S-parameters measurement
Appropriate calibration techniques e.g. SOLT, TRL [10] are used to perform the de-embedding
of the external circuitry including coupling/decoupling network.
The S-parameters measurement is performed with a powered IC to account for potential effects.
The S-parameters measurement is performed with a sufficient power to get a satisfying dynamic
range and below a limit to avoid non-linear effects. This power value varies from a low-level e.g.
−40 dBm to 0 dBm or a value where non-linearities appears. As indicated in the 8.2 of
IEC 62433-4:2016, the comparison of the calculated transfer function with the result of a
conducted immunity measurement will validate the non-linearity of the PDN.
General rules concerning the measurement method to use according to the impedance to
measure which are described in the Annex F of IEC 62433-4:2016 are applicable.
In our example, S-parameters measurements are performed on V , LIN and V pins with
CC BAT
respect to GND pin from 1 MHz to 1 GHz using 3-port measurement. Figure 5 illustrates an
example of the reflection coefficient measurement performed on the IC under test. This figure
shows that the disturbance power could easily enter the V and V pins between 1 to
BAT CC
100 MHz while it is mainly reflected at the LIN pin.
Figure 5 – Example of reflection coefficient measurement
performed on the IC under test
The impedances could be independent or dependent on the functional states. In the dependent
functional mode, models for each functioning point are extracted. For example, in the case of
LIN, two PDN models have been extracted, one for dominant and one for recessive as shown
in Figure 6. This point is considered in the simulation at application level.

Figure 6 – Example of LIN pin impedances depending on state
Figure 7 illustrates an example of the transmission coefficients measurement between the pins
V and V of the IC under test. This figure shows that a non-negligible part of disturbance
BAT CC
applied to V pin is transmitted to V and vice-versa. It is important to note that, as 3-port
BAT CC
S-parameter measurement was done, the effect of the other four floating pins (EN, TX, RX and
RSTN) is assumed to be not significant.
Figure 7 – Example of transmission coefficient measurement performed
on the IC under test
The resulting S, Y or Z-parameters file could be attached into the pdn section of the ICIM-CI
model using respectively the S, Y and Z type attribute. The pdn section of the ICIM-CI model
also accepts SPICE subckt files using the “ckt” type attribute.
Some commercial tools allow to convert S-parameters file into a subckt file using a vector fitting
technique. This conversion could be useful for a use into an electrical circuit simulator which
does not accept SnP data format file.
The field “data_files” of the keyword “lead” allows to attach an external network file into the
ICIM-CI model.
In our example, the S-parameters SnP data format file is called LIN_driver.s3p. The pdn section
of the ICIM-CI is written:




LIN_driver.s3p



5.3.3 PDN extraction from existing models
ICIM_CI model shares the same PDN with the ICEM-CE model. Consequently, ICEM-CE PDN
could be used as ICIM-CI PDN.
The details of IBIS [11] model can be insufficient for precise conducted immunity modelling. As
showed in Figure 8, IBIS model is mainly limited to the package parasitic elements of the lead
frame and the bounding wire and input/output capacitance.
a) Input b) Output
Key
1 Package parasitic elements
2 ESD protection
Figure 8 – Structure of IBIS model
IBIS model is dedicated to signal integrity purpose and, with some limitations, to transient
immunity. Furthermore, the transmission parameters between pins are not represented which
limits its use for RF immunity purpose.
5.3.4 PDN extraction from package geometry import and simulation model generator
Commercial or freeware tools [12] enable the determination of the parasitic elements of the
package from a geometric description as illustrated in Figure 9 through a package simulation.
An X-ray machine could be used to precisely determine the required data. Package and
geometric data needed to build a PDN model could also be provided by IC manufacturer CAD
solutions.
a) Package model generation b) Model viewer

Figure 9 – Example of packaging extraction tool
These tools calculate parasitic elements of the packaging including the mutual inductance
between pins as shown in Figure 10. The obtained model is limited to the package and gives
no information about the die itself.

Figure 10 – Example of parasitic elements computation
with an advanced packaging extraction tool
5.4 Conducted immunity characterization
The conducted immunity characterization could be typically done using the DPI measurement
method defined in IEC 62132-4. An example of DPI test setup is shown in Figure 11. During the
test, a directional coupler allows to measure the power transmitted to the IB extraction board
(Figure 12).
Key
1 RF signal generator
2 RF amplifier
3 Bidirectional coupler
4 Power meter
5 IB extraction board
6 IC under test
7 Oscilloscope
Figure 11 – Example of DPI test setup
a) Top layer b) Bottom layer
Key
1 V supply 5 LIN monitor
BAT
2 V DPI 6 RSTN monitor
BAT
3 LIN DPI 7 RX monitor
4 V monitor 8 TX excitation
CC
Figure 12 – Example of PCB dedicated to DPI test
NOTE In Figure 12, dashed white rectangles highlight the monitoring, supply or DPI lines which are detailed in
Figure 17.
DPI test could be automated. All parameters of the DPI setup are modifiable. In this example,
OO is measured on pins LIN, V , RSTN and RX as illustrated in Figure 13.
CC
The conducted immunity characterization will be performed in different configurations to be able
to validate the ICIM-CI model. Typically, a configuration could be defined without any filtering
components on the lines for IB extraction and configurations could be defined with several
combinations of filtering components for model validation.
An example of a configuration is given in Figure 13. Power, TX, and RX lines are protected by
ferrite beads and chokes placed on the PCB. For supply pins on which DPI is applied, the
frequency characteristics of the bias tee or any other protection is measured or simulated to
guarantee their impedance is always higher than the impedance of the pin. For IO pins on which
DPI is applied or which are monitored or on which a control signal is applied, this condition on
impedance is not mandatory, but impedance is measured and characterized.
As the excitation on TX and LIN pins is a PWM signal with a frequency of 1 kHz, these
protections have a limited influence on the functionality to be tested.
Key
Components Connections and supplies
R1, R2, R3, R4, R5 resistor R= 100 kΩ 1 V supply 6 RSTN monitor
BAT
R6 resistor R = 100 Ω 2 V DPI 7 RX monitor
BAT
C1, C2, C3, C4 capacitor C = 1 nF 3 LIN DPI 8 TX excitation
C5 capacitor C = 470 nF 4 V monitor 9 VCC S-parameters
CC
port
L1, L2, L3, L4 ferrite bead, choke 5 LIN monitor

Figure 13 – Example of a configuration for LIN driver DPI measurement
The DPI measurement is performed with a maximal injection power of 35 dBm. This power
corresponds to the forward or incident power measured at RF amplifier 50 Ω output. Figure 14
shows an example of incident power measured at the IB extraction board LIN input.

Figure 14 – Example of incident power at IB extraction board LIN input during DPI
measurement of the initial configuration for each OO
5.5 IB extraction
As indicated in 5.4 of IEC 62433-4:2016, the IB is valid in the conditions in which it has been
established as power supply voltage range, applicable frequency range, temperature range,
applicable load conditions on DI and/or DO pins and immunity test criteria applied on the OO
pin. In [13], the model is built for several loads placed on the bandgap output.
In ICIM-CI model, the IB describes the behaviour of an OO when a disturbance is applied to
one or more DI(s). When a failure criterion is determined e.g. in terms of magnitude level or
time deviation on an OO, the level of the disturbance applied to the DI to reach that criterion is
recorded. Depending on the IC under test, the cause of the failure could be an excessive voltage,
current or power flowing at DI pin. IB contains the voltage, current or power threshold between
the nominal and disturbed operation. These thresholds are measured at the DI pin and not at
the input pin of the board used for the measurement. In examples given in this document, power
threshold has been used.
However, the incident power measured during the DPI measurement is not the power
transmitted to the IC pin that induces failure: the power of interest is the power transmitted to
the IC pin. The transmitted power to the pin is calculated from an AC analysis based on a
numerical simulation performed at constant power e.g. 0 dBm injection as illustrated in
Figure 15.
The modelling includes:
– IC under test represented by its PDN,;
– PWB traces represented by an equivalent circuit model;
– passive components present on the path such as coupling and decoupling capacitors, bias
tee. These components are represented by their RF equivalent circuit model;
– loads on the DI and/or DO represented by their RF equivalent circuit model;
– AC source representing the DPI source.
DC power supplies are not required for an AC analysis.
The DPI generator is a constant power source. This source could be represented by an AC
voltage source with a 50 Ω internal resistance. The relation between the AC voltage source V
and the power P is given by the Formula (1):
Vp=2×× P Z (1)
where
V is the peak voltage of the AC source, expressed in Volts;
p
P is the power of the AC source, expressed in Watts;
Z is the internal impedance of the AC source, expressed in Ohms.
Key
1 AC source
2 PCB trace
3 IC under test
4 Load
I current
V voltage
Figure 15 – Example of block diagram for DPI setup modelling
For one DI input, this SPICE modelling allows to calculate the real and imaginary parts of the
current I flowing into the DI pin and the voltage V referenced to the PCB ground present at the
DI pin input during the constant power injection. These current and voltage allow calculating
the transmitted power for 0 dBm injection P at the pin input according to the formula (2):
t,0dBm
* * *
P  VI×+×I V R eeeVI ×
( ) ( )
t,OdBm (2)
where
P is the power transmitted to the DI pin during a DPI at 0 dBm, expressed in Watts;
t,0dBm
V is the complex voltage at the DI pin during a DPI at 0 dB, expressed in Volts;
*
V is the conjugate of the complex voltage at the DI pin during a DPI at 0 dB, expressed
in Volts;
I is the complex current at the DI pin during a DPI at 0 dB, expressed in Amperes.
*
I is the conjugate of the complex current at the DI pin during a DPI at 0 dB, expressed
in Amperes.
Figure 16 shows an example of DPI spice modelling to calculate the power transmitted to VBAT
pin during a 0 dBm power injection on the + 12 V board input. The equivalent voltage source is
447 mV peak to represent a constant 0 dBm power generator.
= =
Figure 16 – Example of DPI SPICE modelling to calculated power transmitted to VBAT
pin during a 0 dBm power injection at IB extraction board input
In the modelling illustrated in Figure 16, the IB extraction board traces are represented by a
subcircuit obtained from a simple transmission line modelling. Figure 17 shows the different
traces of the PCB presented in Figure 12 inside the white dashed rectangles:
– on the disturbance line: MMCX is the disturbance input connector, CS1 and CS2 are the
two subcircuit nodes of the coupling capacitor and ICPIN is the DI pin of the IC,
– on the monitoring or supply line: SMA is the monitoring input connector, BT4 and BT3 are
the two subcircuit nodes to place up to 3 chokes or ferrite beads, BT2 and BT1 are the two
subcircuit nodes to place up to 2 chokes or ferrite beads, CAP is the subcircuit node to place
a decoupling capacitor to the ground.

a) Monitoring or supply line b) DPI input line c) PCB traces SPICE
subcircuit
Figure 17 – Example of IB extraction board trace modelling
using SPICE subcircuit model
Figure 18 shows an example of the calculation of the power and voltage transmitted to the IC
VBAT pin during the DPI SPICE simulation shown in Figure 16. Figure 18 shows that a part of
the power is lost into the bias tee mainly in the lowest frequencies.
Figure 18 – Example of transmitted power and voltage magnitude calculated at VBAT
pin of the IC under test during DPI SPICE simulation performed at 0 dBm
The power transmitted to the DI pin expressed in dBm P (OO) during the DPI test with an
tdBm,DI
incident power P (OO) inducing a failure on an OO pin can be then calculated as:
incdBm,DI
P OO P OO+ P
( ) ( )
tdBm,DI incdBm,DI t,,OdBm DI (3)

where
P (OO) is the power transmitted to the DI pin inducing a failure on an OO pin during
tdBm,DI
the DPI, expressed in dBm;
P (OO) is the incident power inducing a failure on an OO pin during the DPI, expressed
incdBm,DI
in dBm;
P is the power transmitted to the DI pin during a DPI at 0 dBm, expressed in dBm.
t,0dBm,DI
In our example, for a DPI injection on VBAT pin, four transmitted powers P are obtained:
t
– P (VCC) the power transmitted to VBAT pin producing a failure on V ;
t,VBAT CC
– P (LIN) the power transmitted to VBAT pin producing a failure on LIN;
t,VBAT
– P (RX) the power transmitted to VBAT pin producing a failure on RX;
t,VBAT
– P (RSTN) the power transmitted to VBAT pin producing a failure on RSTN.
t,VBAT
For the DPI injection on LIN pin, two transmitted powers P are obtained:
t
– P (LIN) the power transmitted to LIN pin producing a failure on LIN;
t,LIN
– P (RX) the power transmitted to LIN pin producing a failure on RX.
t,LIN
Then, it is also possible, for each DI pin e.g. LIN, to combine the failures from several OO, e.g.
RX and LIN by keeping the lowest transmitted power at each frequency point.
– P (LIN,RX) the power transmitted to LIN pin producing a failure on LIN or RX.
t,LIN
=
Figure 19 illustrates the comparison between incident and transmitted power during a DPI
measurement on the IB extraction board + 12 V pin corresponding to the VBAT IC pin. pin.
P (LIN) is the incident power at the IB extraction board + 12 V pin producing a failure on
inc,VBAT
LIN and and P (RX) is the incident power at the IB extraction board + 12 V pin producing
inc,VBAT
a failure on RX.
Figure 19 – Example of comparison incident vs transmitted power
for a DPI on + 12 V board pin
The resulting transmitted power files could be attached into the Ib section of the ICIM-CI model
using the DPI type attribute. The field “data_files” of the keyword “lead” allows to attach an
external network fil
...