IEC 60749-37:2008

IEC 60749-37
Edition 1.0 2008-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –
Part 37: Board level drop test method using an accelerometer

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques et climatiques –
Partie 37: Méthode d’essai de chute au niveau de la carte avec utilisation d’un
accéléromètre
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IEC 60749-37
Edition 1.0 2008-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –
Part 37: Board level drop test method using an accelerometer

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques et climatiques –
Partie 37: Méthode d’essai de chute au niveau de la carte avec utilisation
d’un accéléromètre
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
R
CODE PRIX
ICS 31.080.01 ISBN 2-8318-9569-3

– 2 – 60749-37 © IEC:2008
CONTENTS
FOREWORD.3
INTRODUCTION.5

1 Scope and object.6
2 Normative references .6
3 Terms and definitions .6
4 Test apparatus and components.7
4.1 Test apparatus .7
4.2 Test components.8
4.3 Test board.8
4.4 Test board assembly .8
4.5 Number of components and sample size .9
5 Test procedure .9
5.1 Test equipment and parameters .9
5.2 Pre-test characterization .10
5.3 Drop testing.12
6 Failure criteria and failure analysis .12
7 Summary.14

Annex A (informative) Preferred board construction, material, design and layout .15

Bibliography.19

Figure 1 – Typical drop test apparatus and mounting scheme for PCB assembly .10
Figure 2 – Typical shock test half-sine pulse graphic and formulae .11
Figure 3 – Fundamental mode of vibration of PCB supported with four screws.14
Figure A.1 – Recommended test board size and layout.18

Table 1 – Quantity of test boards and components required for testing .9
Table 2 – Component locations for test boards .13
Table A.1 – Test board stack-up and material .15
Table A.2 – Mechanical property requirements for dielectric materials .16
Table A.3 – Recommended test board pad sizes and solder mask openings .17
Table A.4 – X, Y locations for components’ centre .18

60749-37 © IEC:2008 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 37: Board level drop test method using an accelerometer

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
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6) All users should ensure that they have the latest edition of this publication.
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60749-37 has been prepared by IEC technical committee 47:
Semiconductor devices.
This standard cancels and replaces IEC/PAS 62050 published in 2004. This first edition
constitutes a technical revision.
The text of this standard is based on the following documents:
FDIS Report on voting
47/1937/FDIS 47/1948/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

– 4 – 60749-37 © IEC:2008
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 60749 series, under the general title Semiconductor devices –
Mechanical and climatic test methods, can be found in the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
60749-37 © IEC:2008 – 5 –
INTRODUCTION
Handheld electronic products fit into the consumer and portable market segments. Included in
handheld electronic products are cameras, calculators, cell phones, cordless phones, pagers,
palm size PCs, personal computer memory card international association (PCMCIA) cards,
smart cards, personal digital assistants (PDAs) and other electronic products that can be
conveniently stored in a pocket and used while held in user’s hand.
These handheld electronic products are more prone to being dropped during their useful
service life because of their size and weight. This dropping event can not only cause
mechanical failures in the housing of the device but also create electrical failures in the
printed circuit board (PCB) assemblies mounted inside the housing due to transfer of energy
through PCB supports. The electrical failures may result from various failure modes such as
cracking of the circuit board, track cracking on the board, cracking of solder interconnections
between the components and the board, and component cracks. The primary driver of these
failures is excessive flexing of the circuit board due to input acceleration to the board created
from dropping the handheld electronic product. This flexing of the board causes relative
motion between the board and the components mounted on it, resulting in component,
interconnect or board failures. The failure is a function of the combination of the board design,
construction, material, thickness and surface finish; interconnect material and standoff height
and component size.
Correlation between test and field conditions is not yet fully established. Consequently, the
test procedure is presently more appropriate for relative component performance than for use
as a pass/fail criterion. Rather, results should be used to augment existing data or establish a
baseline for potential investigative efforts in package/board technologies.
The comparability between different test sites, data acquisition methods, and board
manufacturers has not been fully demonstrated by existing data. As a result, if the data are to
be used for direct comparison of component performance, matching studies must first be
performed to prove that the data are in fact comparable across different test sites and test
conditions.
This method is not intended to substitute for full characterization testing, which might
incorporate substantially larger sample sizes and increased number of drops. Due to limited
sample size and number of drops specified here, it is possible that enough failure data may
not be generated in every case to perform full statistical analysis.

– 6 – 60749-37 © IEC:2008
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 37: Board level drop test method using an accelerometer

1 Scope and object
This part of IEC 60749 provides a test method that is intended to evaluate and compare drop
performance of surface mount electronic components for handheld electronic product
applications in an accelerated test environment, where excessive flexure of a circuit board
causes product failure. The purpose is to standardize the test board and test methodology to
provide a reproducible assessment of the drop test performance of surface-mounted
components while producing the same failure modes normally observed during product level
test.
The purpose of this standard is to prescribe a standardized test method and reporting
procedure. This is not a component qualification test and is not meant to replace any system
level drop test that may be needed to qualify a specific handheld electronic product. The
standard is not meant to cover the drop test required to simulate shipping and handling-
related shock of electronic components or PCB assemblies. These requirements are already
addressed in test methods such as IEC 60749-10. The method is applicable to both area
array and perimeter-leaded surface mounted packages.
This test method uses an accelerometer to measure the mechanical shock duration and
magnitude applied which is proportional to the stress on a given component mounted on a
standard board. The test method described in the future IEC 60749-40 uses strain gauge to
measure the strain and strain rate of a board in the vicinity of a component. The detailed
specification states which test method is to be used.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60749-10:2002, Semiconductor devices – Mechanical and climatic test methods –
Part 10: Mechanical shock
IEC 60749-20, Semiconductor devices – Mechanical and climatic test methods – Part 20:
Resistance of plastic-encapsulated SMDs to the combined effect of moisture and soldering
heat
IEC 60749-20-1, Semiconductor devices – Mechanical and climatic test methods – Part 20-1:
Handling, packing, labelling and shipping of surface-mount devices sensitive to the combined
effect of moisture and soldering heat
3 Terms and definitions
For purposes of this document, the following terms and definitions apply.
———————
Under consideration.
In preparation.
60749-37 © IEC:2008 – 7 –
3.1
component
packaged semiconductor device
3.2
single-sided PCB assembly
printed circuit board assembly with components mounted on only one side of the board
3.3
double-sided PCB assembly
printed circuit board assembly with components mounted on top and bottom sides of the
board
3.4
handheld electronic product
product that can conveniently be stored in a pocket (of sufficient size) and used when held in
user’s hand
NOTE Handheld electronic products include cameras, calculators, cell phones, pagers, palm-size PCs (formerly
called ‘pocket organizers’), personal computer memory card international association (PCMCIA) cards, smart
cards, mobile phones, personal digital assistants (PDAs) and other communication devices.
3.5
peak acceleration
maximum acceleration during the dynamic motion of the test apparatus
3.6
pulse duration
acceleration interval
time interval between the instant when the acceleration first reaches 10 % of its specified
peak level and the instant when the acceleration first returns to 10 % of the specified peak
level after having reached that peak level
3.7
table drop height
free-fall drop height of the drop table needed to attain the prescribed peak acceleration and
pulse duration
3.8
event
electrical discontinuity of resistance greater than 1 000 Ω lasting for 1 μs or longer
3.9
event detector
continuity test instrument capable of detecting electrical discontinuity of resistance greater
than 1 000 Ω lasting for 1 μs or longer
4 Test apparatus and components
4.1 Test apparatus
The shock-testing apparatus shall be capable of providing shock pulses up to a peak
–2
with a pulse duration between 0,3 ms and 8,0 ms to the body of
acceleration of 2 900 m·s
–1 –1
the device and a velocity change of 710 mm·s to 5 430 mm·s .
The acceleration pulse shall be a half-sine waveform with an allowable deviation from
specified acceleration level not greater than ±20 % of the specified peak acceleration. This is
determined by a transducer having a natural frequency 5 times the frequency of the shock
pulse being established and measured through a low pass filter having a band width

– 8 – 60749-37 © IEC:2008
preferably at least 5 times the frequency of the shock pulse being established. It is very
important that the transducer resonance does not approach the measured value. Filtering
should not be used in lieu of good measurement set-up and procedure practices. The pulse
duration shall be measured between the points at 10 % of the peak acceleration during rise
time and 10 % of the peak acceleration during decay time. Absolute tolerances of the pulse
duration shall be ±30 % of the specified duration. It is recommended that the test velocity
change should be ±10 % of the specified level.
4.2 Test components
This standard covers all area arrays and perimeter-leaded surface-mountable packaged
semiconductor devices such as ball grid arrays (BGA), land grid arrays (LGA), chip scale
packages (CSP), thin small outline packages (TSOP) and quad flat no-lead packages (QFN)
typically used in handheld electronic product. All components used for this testing must be
daisy-chained. The daisy chain should either be made at the die level or by providing daisy
chain links at the lead-frame or substrate level. In case of non-daisy chain die, a mechanical
dummy die shall be used inside the package to simulate the actual structure of the package.
The die size and thickness should be similar to the functional die size to be used in
application. The component materials, dimensions and assembly processes shall be
representative of typical production device.
4.3 Test board
Since the drop test performance is a function of the test board used for evaluation, this
standard describes a preferred test board construction, dimensions, and material that is
representative of those used in handheld electronic products. If another board
construction/material better represents a specific application, the test board construction,
dimensions and material should be documented. The test data generated using such a board
shall be correlated at least once by generating the same data on the same component using
the preferred board defined in this document (see Annex A for recommendations).
4.4 Test board assembly
Prior to board assembly, all devices shall be inspected for missing balls or bent leads. Board
thickness, warpage and pad sizes shall also be measured using a sampling plan. A visual
inspection shall be performed on all boards for solder mask registration, contamination and
daisy chain connection. It is recommended that boards should be inspected and accepted in
accordance with a relevant national or international standard. One board shall also be used to
measure the mechanical properties (modulus and glass transition temperature, T ) of the
g
board at the component location using dynamic mechanical analysis (DMA) and
thermomechanical analysis (TMA) methods. It is highly recommended that the coefficient of
thermal expansion (CTE) of the board be also measured in X, Y and Z direction. The
mechanical property measurements are not required for every board lot, unless the fabrication
process, material or vendor is changed from lot to lot.
The components shall be baked according to IEC 60749-20 and the future IEC 60749-20-1
prior to board assembly. The test boards shall be assembled using best known methods of
printed circuit assembly process, representative of production methods. At least one board
shall be used to adjust the board mounting process such as paste printing, placement and
reflow profile. All assemblies shall be single-sided only, unless the component is anticipated
for use in mirror-sided board assemblies. In that case, the components shall be mounted on
each side of the board.
A 100 % X-ray inspection is recommended on assembled units to check for voids, short-
circuits and other abnormalities. Electrical continuity test shall also be performed on all
mounted units to detect any open-circuits or short-circuits.

60749-37 © IEC:2008 – 9 –
4.5 Number of components and sample size
The board design recommended in Annex A allows up to 15 locations for component mounting
and it is preferred that components be mounted on all 15 locations. Since the drop
performance is a function of component location on the board, testing with components
mounted on all 15 locations will provide useful information to the users of this data in proper
layout of their product board. With the board supported at four corners, these locations cover
the worst case board curvature (U8 location), the effect of proximity to support locations (U1,
U5, U11, and U15 locations) and various locations in between. Because of various designs for
tests, and designs for failure analysis practices used in the industry, it is recognized that
populating boards with all 15 locations may not leave enough room between components for a
large number of test points to properly identify the exact failure location. Therefore, options
are provided for mounting just 1 or 5 components on the board using the following locations:
– 1-component configurations: location U8
– 5-component configurations: locations U2, U4, U8, U12, and U14
Table 1 – Quantity of test boards and components required for testing
Number of boards
Number of
Total number of
components
Side A assembly Side B assembly
components
per board
(via in pad) (not via in pad)
15 4 4 120
5 4 4 40
1 10 10 20
Since the number and size of the components mounted on the board may influence the
dynamic response of the test board assembly during drop, it is required that additional data
are provided whenever these 1-component or 5-component configurations are employed. The
additional data shall directly compare the effect of optional component mounting (1- or 5-
component) to the preferred 15-component mounting configuration. This comparison shall be
provided for a component similar in size (within 20 % in both length and width) to the
component, which has been tested using 1- or 5-component per board configuration only.
Depending on the number of components mounted per board, Table 1 shall be used to
determine the minimum quantity of assembled boards required for testing and the total
number of components to be tested. Sample sizes greater than specified in Table 1 can be
used to generate statistically sufficient data. In case of rectangular components, the longer
side of the component should be parallel to the longer side of the board when mounted.
5 Test procedure
5.1 Test equipment and parameters
The shock testing apparatus shall be mounted on a sturdy laboratory table or equivalent base
and levelled before use. Means shall be provided in the apparatus (such as an automatic
braking mechanism) to eliminate bounce and to prevent multiple shocks to the board. Figure 1
shows the typical drop test apparatus where the drop table travels down on guide rods and
strikes the rigid fixture. The rigid fixture typically is covered with some form of material to
achieve the desirable pulse and acceleration levels. The bottom of the drop table is usually
rounded slightly to ensure a very small area of contact with the strike surface.

– 10 – 60749-37 © IEC:2008
PCB assembly
Guide rods
Stand-offs
Accelerometer
Base plate
Base plate
Drop table
Drop table
Strike surface
Rigid base
IEC  001/08
Figure 1 – Typical drop test apparatus and mounting scheme for PCB assembly
A base plate with suitable standoffs (e.g. 6 mm hexagonal outside diameter / M3 × 0,5 inside
diameter, 10 mm long) shall be rigidly mounted on the drop table. The thickness and mounting
locations of the base plate shall be selected such that there is no relative movement between
the drop table and any part of base plate during drop testing. This plate will serve as the
mounting structure for the PCB assemblies. This is pictorially shown in Figure 1. The PCB
assembly shall be mounted to the base plate standoffs using four screws, one at each corner
of the board. The board shall be mounted using four suitable precision shoulder screws (e.g.
M3 × 0,5). Test data suggests that the variations in response acceleration and strain are
reduced significantly dependant upon the choice of screw. Since the length of shoulder is
nominal, a number of washers should be placed between the screw head and the top surface
of the board (nominal 1,0 mm thick) to avoid any gap between the top of the standoffs and the
bottom surface of the board. Due to tolerance stack up, a small gap is still possible but this
gap shall not exceed 50 µm. The use of shoulder screw eliminates the need to re-tighten
screws between drops. The screws shall be tightened in a diagonal pattern in the order of
SW, NE, SE, and NW corners of the board. The screw shall be tightened until the shoulder of
the screw bottoms out against the standoff. The number of washers used shall be the same
for all four screws. A custom board jig may be used instead of mounting the board directly to
the plate.
Experience with different board orientations has suggested that the horizontal board
orientation with components facing down results in maximum PCB flexure and, thus, the worst
orientation for failures. Therefore, this standard requires that the board shall be horizontal in
orientation with components facing in downward direction during the test. Drop testing using
other board orientations is not required but may be performed if deemed necessary. However,
this is an additional test option and not a replacement for testing in the required orientation.
–2
, 0,5 ms duration, half-sine pulse), as
This standard requires test condition B (1 500 m·s
listed in Table 1 of IEC 60749-10, as the input shock pulse to the printed circuit assembly.
This is the applied shock pulse to the base plate and shall be measured by accelerometer
mounted at the centre of base plate or close to the support posts for the board. Other shock
–2
conditions, such as 2 900 m·s , 0,3 ms duration, in addition to the required condition can
also be used.
5.2 Pre-test characterization
A set-up board with components mounted on it shall be used to adjust and characterize the
drop test parameters and board response. A lightweight accelerometer should be attached
with beeswax (or equivalent adhesive) on top of the component located at position U8 to

60749-37 © IEC:2008 – 11 –
characterize the output acceleration response of the PCB assembly. It should be noted,
however, that any additional mass will add significant dynamic weight to the board and may
alter its dynamic response. Therefore, it is recommended that this characterization should
only be carried out on a set-up board. In addition, a 45 ° rectangular rosette strain gauge shall
be mounted on this set-up board underneath position U8 on the other side (non-component)
side of the board to characterize strains in the X and Y directions as well as the principal
strain and principal strain angle. Both the accelerometer and the strain gauge shall be
connected to a data acquisition system capable of measuring at a scan frequency of 20 kHz
and greater with a 16 bit signal width. Additional strain gauges may also be mounted at
different locations on the board to fully characterize the strain response of the assembly.
The board assembly shall then be mounted on the drop test fixture using four screws. The
screws shall be tightened in diagonal pattern in the order of SW, NE, SE, and NW corners of
the board. An additional accelerometer may also be mounted on the board assembly at or
close to one of the support locations to ensure that the input pulse to the base plate is
transmitted to the PCB without any distortion. The drop table shall then be raised to the height
required to meet test condition B of Table 1 of IEC 60749-10 and dropped on to the strike
surface while measuring the G level, pulse duration, and pulse shape.
Multiple drops might be required whilst adjusting the drop height and strike surface to achieve
–2
the specified acceleration levels and pulse duration (1 500 m·s , 0,5 ms half-sine pulse). It
should be noted that the peak acceleration and the pulse duration is a function of not only the
drop height but also the strike surface. Depending on the strike surface, the same drop height
could result in different acceleration levels and pulse durations. Theoretically, the drop height
needed to achieve the appropriate acceleration levels can be determined from Equations (1)
and (2) and the associated Figure 2, where H is the drop height and C is the rebound co-
efficient (1,0 for no rebound, 2,0 for full rebound). However, this equation does not include the
strike surface effect.
Experiments with different strike surface may be needed to achieve the desired peak value
and duration.
⎛ ⎞
πt
⎜ ⎟
A(t ) = A sin (1)
⎜ ⎟
t
w
⎝ ⎠
2A t
⎛ ⎞
0 w
2gH = A sin⎜ ⎟ (2)
⎜ ⎟
C π
⎝ ⎠
A
t
w
Time  (s)
IEC  002/08
Figure 2 – Typical shock test half-sine pulse graphic and formulae
Acceleration  (g)
– 12 – 60749-37 © IEC:2008
Once the specified drop parameters (acceleration level, duration and pulse shape) are
achieved, the PCB response acceleration and strain shall be measured. The strain rate shall
also be calculated by dividing the change in strain value by the time interval during which this
change occurred. The characterized board response (acceleration, strain and strain rate) and
its variation shall be documented and provided with the test data. Although it is recommended
that this characterization be performed for previously untested components, this may not be
required if such characterization data are available for a similar sized component.
5.3 Drop testing
With test parameters adjusted and PCB response characterized, the PCB assemblies shall be
prepared for drop testing. This involves soldering cables to the plated though holes on one
end of the board, mounting the board on the drop fixture with components facing down, and
connecting cables to the event detector/data logger. Since the dynamic response of the board
can be affected by the mass and stiffening of the connector, it is recommended that no
connectors are used and wires are directly soldered to the board.
The event detector’s threshold resistance shall be set to no more than 1 000 Ω. Proper strain
relief should also be provided to cables/wires to avoid a failure at wires to board
interconnects. All cables shall be cleared from the drop path. The initial resistance of all nets
for each assembly shall be measured and logged before conducting the first drop. The drop
test shall be conducted by releasing the drop table from the pre-established height. The
electrical resistance of each net shall be measured in situ during each drop and all failures
shall be logged. The board shall be dropped a required maximum number of times or until a
percentage of all devices has failed, whichever is earlier. The maximum number of drops or
percentage of devices failing shall be consistent with the application. The maximum number
of drops shall be irrespective of single or double-sided assembly. In the event that a shock
condition in addition to the required condition B is used to conduct the test, the maximum
number of drops shall be determined using the acceleration factor between the two conditions
for similar sized components. This acceleration factor shall be reported with the test data.
During the test, the shock pulse shall be measured for each drop to ensure that the input
pulse remains within the specified tolerance. Adjustments in drop height or replacement of
strike surface shall be made if the pulse deviates from that specified.
Depending on number of components per board, Table 1 shall be used to determine the
number of boards to be tested per component type.
6 Failure criteria and failure analysis
In-situ electrical monitoring of daisy chain nets for failure is required during each drop. The
electrical continuity of all nets should either be detected by an event detector or by a high-
speed data acquisition system. The event detector should be able to detect any intermittent
discontinuity of resistance greater than 1000 Ω lasting for 1 μs or longer. The high-speed data
acquisition system should be able to measure resistance with a sampling rate of 50,000
samples per second or greater.
Depending on the monitoring system used, the failure is defined as follows:
– event detector: the first event of intermittent discontinuity as defined above followed by 3
additional such events during 5 subsequent drops.
– high speed data acquisition: the first indication of resistance value of 100 Ω or 20 %
increase in resistance from the initial resistance if initial resistance is greater than 85 Ω
followed by 3 additional such indications during 5 subsequent drops.
A visible partial separation of component from the test board, even without a significant
increase in resistance or intermittent discontinuity, shall also be considered as a failure. This
can occur if the PCB tracks come off the board with the component while maintaining
electrical continuity.
60749-37 © IEC:2008 – 13 –
As wires soldered to the board for electrical continuity test can also come off during the test, it
is highly recommended that all electrical connections be checked once a failure is indicated to
ensure that the failure is due to a component to board interconnection failure.
All failures after each drop shall be logged. A sufficient number of components from the test
lot shall be subjected to failure analysis to determine the root cause and to identify failure
mechanism. The selection of components should cover different locations on the board.
Different methods and equipment, such as visual inspection, cross-section, dye and pry,
chemical etching, scanning electron microscopy, and scanning acoustic tomography can be
employed to determine the root cause of failure. The failure site shall be clearly identified as
‘component failure’, ‘interconnect failure’ or ‘board failure’. For the purpose of this standard,
the “interconnect failure” is defined as any failure
a) on the package pad – joint interface or intermetallics,
b) through the joint material,
c) on the PCB pad joint interface or intermetallics.
The above criteria may always be overridden by an applicable procurement document.
Data analysis shall be conducted showing mean and standard deviation of failure data
according to component groupings. Weibull and/or log normal analysis result should also be
included if sufficient quantities have failed for such analyses. Because of symmetric
component design and support locations, grouping (see Table 2) can be used for data
analysis for boards mounted with 15 components (refer to Figure A.1).
Table 2 – Component locations for test boards
Component Sample size
Number of
locations on the
Group components
Side A Side B
board
in the group
assembly assembly
A 4 U1, U5, U11, U15 8 8
B 4 U2, U4, U12, U14 8 8
C 2 U6, U10 4 4
D 2 U7, U9 4 4
E 2 U3, U13 4 4
F 1 U8 2 2
Failure data for components in group E and F can also be combined into one group as the
PCB curvature underneath these components is expected to be very similar during the
fundamental mode of vibration, as shown in Figure 3. The fundamental mode results in
maximum displacements and is typically most damaging. Similarly, a larger group containing
components in groups B and D may also exist. It is recommended first to analyse the
component reliability data at individual locations without assuming any grouping. The failure
data can only be pooled together when they have been proved to be statistically equivalent.

– 14 – 60749-37 © IEC:2008
S3 S4
U11 U12 U13 U14 U15
U6 U7 U8 U9 U10
U1 U2 U3 U4 U5
S1 S2
IEC  003/08
Figure 3 – Fundamental mode of vibration of PCB supported with four screws
For the cases where component design is not symmetric about the X- and Y-axis, the above
grouping may not work. This may require additional boards to be tested to achieve the sample
sizes given above.
7 Summary
All test reports shall include the following information:
a) Package and PCB assembly weight.
b) Package geometrical details including body size, lead size, ball size, layer thickness and
die size.
c) Package materials including mould compound, die attach, substrate.
d) Board geometry, material and material properties such as thickness, pad size, modulus
and T
g.
e) Board assembly details including stencil thickness, apertures, stencil material, solder alloy
and paste, reflow profile and other board assembly process details.
f) Test details: drop height, strike surface, shock pulse profile.
g) Board response (acceleration, strain and strain rate).
h) Initial resistance of daisy chain nets.
i) Failure detection equipment and failure criteria.
j) Test results including the number of drops to failure for each location on each test board,
failure mechanisms and representative pictures.
k) Data analysis showing mean and standard deviation of failure data according to
component groupings.
60749-37 © IEC:2008 – 15 –
Annex A
(informative)
Preferred board construction, material, design and layout

A.1 Preferred board construction, material and design
The preferred test board should use built-up multilayer technology incorporating microvias
using 1+6+1 stack-up. This is recommended because typical PCB assemblies used in
handheld electronic systems are constructed using high density, build-up technology. The test
board should have a nominal thickness of 1,0 mm. Table A.1 provides the thickness, copper
coverage and material for each layer. The dielectric materials should meet the mechanical
properties requirements given in Table A.2. The PCB should have organic solderability
preservatives (OSP) as surface finish to avoid any copper oxidation before component
mounting. The glass transition temperature, T , of each dielectric material, as well as of the
g
composite board, should be 125 °C or greater. The modulus and T of the dielectric materials
g
should be specified. The composite values (modulus and T ) should be measured on at least
g
one representative test board at the component mounting location. The boards should be
symmetrical in construction about the mid-plane of the board, except for the minor differences
in the top and bottom two layers.
Table A.1 – Test board stack-up and material
Thickness Copper coverage
Board layer Material
μm %
a
Solder mask 20 LPI
Layer 1 35 Pads + tracks Copper
b
Dielectric 1-2 65 RCC
Layer 2 35 40 % including daisy chain links Copper
Dielectric 2-3 130 FR4
Layer 3 18 70 % Copper
Dielectric 3-4 130 FR4
Layer 4 18 70 % Copper
Dielectric 4-5 130 FR4
Layer 5 18 70 % Copper
Dielectric 5-6 130 FR4
Layer 6 18 70 % Copper
Dielectric 6-7 130 FR4
Layer 7 35 40 % Copper
b
Dielectric 7-8 65 RCC
Layer 8 35 Pads + tracks + daisy chain links Copper
a
Solder mask 20 LPI
a
Liquid photo-imageable.
b
Resin-coated copper.
...