IEC 60749-37:2022

IEC 60749-37 ®
Edition 2.0 2022-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –
Part 37: Board level drop test method using an accelerometer

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques et climatiques –
Partie 37: Méthode d'essai de chute au niveau de la carte avec utilisation d'un
accéléromètre
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IEC 60749-37 ®
Edition 2.0 2022-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Mechanical and climatic test methods –

Part 37: Board level drop test method using an accelerometer

Dispositifs à semiconducteurs – Méthodes d’essais mécaniques et climatiques –

Partie 37: Méthode d'essai de chute au niveau de la carte avec utilisation d'un

accéléromètre
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-5837-8

– 2 – IEC 60749-37:2022 © IEC 2022
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Test apparatus and components . 7
4.1 Test apparatus . 7
4.2 Test components . 8
4.3 Test board . 8
4.4 Test board assembly . 8
4.5 Number of components and sample size . 9
5 Test procedure . 9
5.1 Test equipment and parameters . 9
5.2 Pre-test characterization . 11
5.3 Drop testing . 12
6 Failure criteria and failure analysis . 13
7 Summary . 14
Annex A (informative)  Preferred board construction, material, design and layout . 15
A.1 Preferred board construction, material and design . 15
A.2 Preferred test board size, layout, and component locations . 17
Bibliography . 20

Figure 1 – Drop test apparatus detail . 10
Figure 2 – Calculation of velocity change . 11
Figure 3 – Typical shock test half-sine pulse graphic and formulae . 12
Figure A.1 – Board footprint and BGA layout . 18
Figure A.2 – Test vehicle with 4 component placement (top side – left) and
1 component at center location (bottom side – right). . 19

Table 1 – Quantity of test boards and components required for testing . 9
Table A.1 – Test board stack-up and material . 15
Table A.2 – Mechanical property requirements for dielectric materials . 16
Table A.3 – Recommended test board pad sizes and solder mask openings . 17

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 37: Board level drop test method using an accelerometer

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
IEC 60749-37 has been prepared by IEC technical committee 47: Semiconductor devices. It is
an International Standard.
This second edition, based on JEDEC document JESD22-B111A, cancels and replaces the first
edition published in 2008. lt is used with permission of the copyright holder, JEDEC Solid State
Technology Association. This edition constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) correction of a previous technical error concerning test conditions;
b) updates to reflect improvements in technology.

– 4 – IEC 60749-37:2022 © IEC 2022
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2651/CDV 47/2719/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/standardsdev/publications.
A list of all parts of the IEC 60749 series, under the general title Semiconductor devices –
Mechanical and climatic test methods, can be found in the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

INTRODUCTION
Handheld electronic products fit into the consumer and portable market segments. Included in
handheld electronic products are cameras, calculators, cell phones, cordless phones, pagers,
palm size PCs, personal computer memory card international association (PCMCIA) cards,
smart cards, personal digital assistants (PDAs) and other electronic products that can be
conveniently stored in a pocket and used while held in user’s hand.
These handheld electronic products are more prone to being dropped during their useful service
life because of their size and weight. This dropping event can not only cause mechanical failures
in the housing of the device but also create electrical failures in the printed circuit board (PCB)
assemblies mounted inside the housing due to transfer of energy through PCB supports. The
electrical failures sometimes result from various failure modes such as cracking of the circuit
board, track cracking on the board, cracking of solder interconnections between the
components and the board, and component cracks. The primary driver of these failures is
excessive flexing of the circuit board due to input acceleration to the board created from
dropping the handheld electronic product. This flexing of the board causes relative motion
between the board and the components mounted on it, resulting in component, interconnect or
board failures. The failure is a function of the combination of the board design, construction,
material, thickness and surface finish; interconnect material and standoff height and component
size.
Correlation between test and field conditions is not yet fully established. Consequently, the test
procedure is presently more appropriate for relative component performance than for use as a
pass/fail criterion. Rather, results can be used to augment existing data or establish a baseline
for potential investigative efforts in package/board technologies.
The comparability between different test sites, data acquisition methods, and board
manufacturers has not been fully demonstrated by existing data. As a result, if the data are to
be used for direct comparison of component performance, matching studies will first be
performed to prove that the data are in fact comparable across different test sites and test
conditions.
This method is not intended to substitute for full characterization testing, which could
incorporate substantially larger sample sizes and increased number of drops. Due to limited
sample size and number of drops specified here, it is possible that enough failure data are not
generated in every case to perform full statistical analysis.

– 6 – IEC 60749-37:2022 © IEC 2022
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –

Part 37: Board level drop test method using an accelerometer

1 Scope
This part of IEC 60749 provides a test method that is intended to evaluate and compare drop
performance of surface mount electronic components for handheld electronic product
applications in an accelerated test environment, where excessive flexure of a circuit board
causes product failure. The purpose is to standardize the test board and test methodology to
provide a reproducible assessment of the drop test performance of surface-mounted
components while producing the same failure modes normally observed during product level
test.
This document aims at prescribing a standardized test method and reporting procedure. This is
not a component qualification test and is not meant to replace any system level drop test that
is sometimes used to qualify a specific handheld electronic product. The standard is not meant
to cover the drop test required to simulate shipping and handling-related shock of electronic
components or PCB assemblies. These requirements are already addressed in test methods
such as IEC 60749-10. The method is applicable to both area array and perimeter-leaded
surface mounted packages.
This test method uses an accelerometer to measure the mechanical shock duration and
magnitude applied which is proportional to the stress on a given component mounted on a
standard board. The test method described in IEC 60749-40 uses strain gauge to measure the
strain and strain rate of a board in the vicinity of a component. The customer specification states
which test method is to be used.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60749-10:2022, Semiconductor devices – Mechanical and climatic test methods – Part 10:
Mechanical shock – Device and subassembly
IEC 60749-20, Semiconductor devices – Mechanical and climatic test methods – Part 20:
Resistance of plastic-encapsulated SMDs to the combined effect of moisture and soldering heat
IEC 60749-20-1, Semiconductor devices – Mechanical and climatic test methods – Part 20-1:
Handling, packing, labelling and shipping of surface-mount devices sensitive to the combined
effect of moisture and soldering heat
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
IEC Electropedia: available at https://www.electropedia.org/
ISO Online browsing platform: available at https://www.iso.org/obp
3.1
component
packaged semiconductor device
3.2
single-sided assembly
printed circuit board assembly with components mounted on only one side of the board
3.3
double-sided assembly
printed circuit board assembly with components mounted on top and bottom sides of the board
3.4
handheld electronic product
product that can conveniently be stored in a pocket (of sufficient size) and used when held in
user’s hand
Note 1 to entry: Handheld electronic products include cameras, calculators, cell phones, pagers, palm-size PCs
(formerly called ‘pocket organizers’), personal computer memory card international association (PCMCIA) cards,
smart cards, mobile phones, personal digital assistants (PDAs) and other communication devices.
3.5
peak acceleration
maximum acceleration during the dynamic motion of the test apparatus
3.6
pulse duration
acceleration interval
time interval between the instant when the acceleration first reaches 10 % of its specified peak
level and the instant when the acceleration first returns to 10 % of the specified peak level after
having reached that peak level
3.7
table drop height
free-fall drop height of the drop table needed to attain the prescribed peak acceleration and
pulse duration
3.8
event
electrical discontinuity of resistance greater than 1 000 Ω lasting for 1 μs or longer
3.9
event detector
continuity test instrument capable of detecting electrical discontinuity of resistance greater than
1 000 Ω lasting for 1 μs or longer
4 Test apparatus and components
4.1 Test apparatus
The shock-testing apparatus shall be capable of providing shock pulses up to a peak
−2
acceleration of 2 900 m·s with a pulse duration between 0,3 ms and 8,0 ms to the body of the
−1 −1
device and a velocity change of 1 250 mm·s to 5 430 mm·s . For free-state testing, a velocity
−1 −1
change of 1 250 mm·s to 5 430 mm·s and a pulse duration between 0,3 ms and 2,0 ms is
sufficient. Conversely, for mounted-state testing, apparatus capable of a velocity change of

– 8 – IEC 60749-37:2022 © IEC 2022
−1 −1
1 000 mm·s to 5 430 mm·s and a pulse duration between 5,0 ms and 8,0 ms to the body of
the component is sufficient.
The acceleration pulse shall be a half-sine waveform with an allowable deviation from specified
peak acceleration not greater than ±10 %. The test velocity change shall be ±10 %of the
specified level. The pulse duration shall be measured between the points at 10 % of the peak
acceleration during rise time and 10 % of the peak acceleration during decay time. Absolute
tolerances of the pulse duration shall be ±15 % of the specified duration. The test equipment
transducer shall have a natural frequency greater than 5 times the frequency of the shock pulse
being established, and measured through a low-pass filter having a bandwidth greater than 5
times the frequency of the shock pulse being established. Filtering shall not be used in lieu of
good measurement setup and procedure practices.
Appropriate equipment calibration shall be carried out prior to any testing.
4.2 Test components
This document covers all area arrays and perimeter-leaded surface-mountable packaged
semiconductor devices such as ball grid arrays (BGA), land grid arrays (LGA), chip scale
packages (CSP), thin small outline packages (TSOP) and quad flat no-lead packages (QFN)
typically used in handheld electronic product. The maximum size of the component body
covered in this document is 15 mm x 15 mm in general. A larger body size may be used for a
special board layout as described in detail in 4.3. All components used for this testing shall be
daisy-chained. The daisy chain is made at the die level or by providing daisy chain links at the
lead-frame or substrate level. In case of non-daisy chain die, a mechanical dummy die shall be
used inside the package to simulate the actual structure of the package. The die size and
thickness shall be similar to the functional die size to be used in application. The component
materials, dimensions and assembly processes shall be representative of typical production
device.
4.3 Test board
Since the drop test performance is a function of the test board used for evaluation, this
document describes a preferred test board construction, dimensions, and material that is
representative of those used in handheld electronic products. If another board
construction/material better represents a specific application, the test board construction,
dimensions and material shall be documented. The test data generated using such a board
shall be correlated at least once by generating the same data on the same component using
the preferred board defined in this document (see Annex A for recommendations).
4.4 Test board assembly
Prior to board assembly, all devices shall be inspected for missing balls or bent leads. Board
thickness, warpage and pad sizes shall also be measured using a sampling plan. A visual
inspection shall be performed on all boards for solder mask registration, contamination and
daisy chain connection. It is recommended that boards be inspected and accepted in
accordance with a relevant national or international standard. One board shall also be used to
measure the mechanical properties (modulus and glass transition temperature, T ) of the board
g
at the component location using dynamic mechanical analysis (DMA) and thermomechanical
analysis (TMA) methods. It is highly recommended that the coefficient of thermal expansion
(CTE) of the board be also measured in X, Y and Z direction. The mechanical property
measurements are not required for every board lot, unless the fabrication process, material or
vendor is changed from lot to lot.
The components shall be baked according to IEC 60749-20 and IEC 60749-20-1 prior to board
assembly. The test boards shall be assembled using best known methods of printed circuit
assembly process, representative of production methods. At least one board shall be used to
adjust the board mounting process such as paste printing, placement and reflow profile. All
assemblies shall be single-sided only, unless the component is anticipated for use in mirror-

sided board assemblies. In that case, the components shall be mounted on each side of the
board.
A 100 % X-ray inspection is recommended on assembled units to check for voids, short-circuits
and other abnormalities. Electrical continuity test shall also be performed on all mounted units
to detect any open-circuits or short-circuits.
4.5 Number of components and sample size
The board design recommended in Annex A allows 4 locations for component mounting and is
recommended that all 4 components are mounted. Since the board is designed with full
symmetry, all 4 components are expected to be subjected to the same drop performance and
hereby the test results are treated as one single group. Statistical analysis on the data
equivalence is suggested to ensure that variability in the component performance is insignificant
before comprehensive data or full qualification is pursued. In order to get good statistically
meaningful results, a total of 6 boards or 24 components are recommended as a minimum
quantity per each design.
Since the number and size of the components mounted on the board can influence the dynamic
response of the test board assembly during drop, it is required that additional data be provided
whenever the 1-component configuration is employed. The additional data shall directly
compare the effect of optional component mounting (1 component case) to the preferred 4-
component mounting configuration. This comparison shall be provided for a component similar
in size (within 20 % in both length and width) to the component, which has been tested using
1-component per board configuration only.
In the case of 1 component mount on the board, Table 1 shall be used to determine the minimum
quantity of assembled board required for testing and total number of components to be tested.
Sample sizes greater than specified below can also be used to generate statistically sufficient
data.
Table 1 – Quantity of test boards and components required for testing
Number of boards
Number of
Total number of
components Location
Side A assembly Side B assembly
components
per board
(via in pad) (not via in pad)
4 U1, U2, U3 and U4 6 6 48
1 Centre of the board 16 16 32

5 Test procedure
5.1 Test equipment and parameters
The shock testing apparatus shall be mounted on a sturdy laboratory table or equivalent base
and levelled before use. Means shall be provided in the apparatus (such as an automatic
braking mechanism) to eliminate bounce and to prevent multiple shocks to the board. Figure 1
shows the typical drop test apparatus where the drop table travels down on guide rods and
strikes the rigid fixture. The rigid fixture typically is covered with some form of material to
achieve the desirable pulse and acceleration levels. The bottom of the drop table is usually
rounded slightly to ensure a very small area of contact with the strike surface.

– 10 – IEC 60749-37:2022 © IEC 2022

d) Sample stand-off design
a) Typical drop test apparatus b) Pre-characterization set up c) Assembly set up with board
without test board
Figure 1 – Drop test apparatus detail
A base plate with suitable standoffs shall be rigidly mounted on the drop table. The thickness
and mounting locations of the base plate shall be selected such that there is no relative
movement between the drop table and any part of base plate during drop testing. This plate will
serve as the mounting structure for the PCB assemblies. This is pictorially shown in Figure 1.
The PCB assembly shall be mounted to the base plate standoffs using four screws, one at each
corner of the board. The board shall be mounted using four suitable precision shoulder screws
(e.g. M3 × 0,5). Test data suggests that the variations in response acceleration and strain are
reduced significantly depending upon the choice of screw. Since the length of shoulder is
nominal, a number of washers shall be placed between the screw head and the top surface of
the board (nominal 1,0 mm thick) to avoid any gap between the top of the standoffs and the
bottom surface of the board. Due to tolerance stack up, a small gap is still possible but this gap
shall not exceed 50 µm. The use of shoulder screw eliminates the need to re-tighten screws
between drops. The screws shall be tightened in a diagonal pattern in the order of SW, NE, SE,
and NW corners of the board. The screw shall be tightened until the shoulder of the screw
bottoms out against the standoff. The number of washers used shall be the same for all four
screws. A custom board jig may be used instead of mounting the board directly to the plate.
Experience with different board orientations has suggested that the horizontal board orientation
with components facing down results in maximum PCB flexure and, thus, the worst orientation
for failures. Therefore, this document requires that the board shall be horizontal in orientation
with components facing in downward direction during the test. Drop testing using other board
orientations is not required but may be performed if deemed necessary. However, this is an
additional test option and not a replacement for testing in the required orientation.
–2
This document requires test condition B (15 000 m·s , 0,5 ms duration, half-sine pulse), as
listed in Table 1 of IEC 60749-10:2022, as the input shock pulse to the printed circuit assembly.
This is the applied shock pulse to the base plate and shall be measured by accelerometer
mounted at the centre of base plate or close to the support posts for the board. The velocity
change of the drop pulse shall be also controlled and maintained at 4,67 m/s. The calculation
of the velocity change is defined by the effective pulse where the acceleration must be equal to
–2
or above 1 500 m·s as shown in Figure 2. No rebounces are allowed in this calculation.

Figure 2 – Calculation of velocity change
5.2 Pre-test characterization
A set-up board with components mounted on it shall be used to adjust and characterize the
drop test parameters and board response. A lightweight accelerometer is attached with (using
suitable adhesive) in the centre of the mounting plate. Since the board weight is negligible as
compared to mounting plate, setup characterization without a test board will not alter the results.
Both the accelerometer and the strain gauge shall be connected to a data acquisition system
capable of measuring at a scan frequency of 20 kHz and greater with a 16-bit signal width.
Additional strain gauges can also be mounted at different locations on the board to fully
characterize the strain response of the assembly.
The board assembly shall then be mounted on the drop test fixture using four screws. The
screws shall be tightened in diagonal pattern in the order of SW, NE, SE, and NW corners of
the board. An additional accelerometer may also be mounted on the board assembly at or close
to one of the support locations to ensure that the input pulse to the base plate is transmitted to
the PCB without any distortion. The drop table shall then be raised to the height required to
meet test condition B of Table 1 of IEC 60749-10:2022 and dropped on to the strike surface
while measuring the G level, pulse duration, and pulse shape.
–2
The acceleration pulse shall follow a half-sine curve with a peak acceleration of 1 500 m·s
during each drop as shown in Figure 2. Multiple drops can be required while adjusting the drop
height and impact surface to achieve the specified peak acceleration and change of velocity
–2
(1 500 m·s , 4,67 m/s respectively). The variations of the peak acceleration and change of
velocity needs to be controlled within 10 % on each individual measurement and 5% tolerance
on average when 20 repeating measurements. The change of velocity is the total area enclosed
by the acceleration pulse and the time axis. An effective change of velocity shall be counted in
–2
which only an acceleration equal to or higher than 1 500 m·s is considered and any rebounces
–2
after the acceleration dropping to below 1 500 m·s from the peak shall be ignored in the
calculation. The time duration for defining the area of effective change of velocity is called
effective pulse duration and shall also be maintained at 0,5 ms within 15 % tolerance which is
in accordance with IEC 60749-10. The test equipment and transducer shall have a natural
frequency greater than 5 times the frequency of the shock pulse being established, and
measured through a low-pass filter having a bandwidth greater than 5 times the frequency of
the shock pulse being established, see detail in IEC 60749-10. However, both unfiltered and

– 12 – IEC 60749-37:2022 © IEC 2022
filtered acceleration profiles shall be reported for the comparison purposes. It shall be noted
that these pulse parameters are function of not only the drop height but also the impact surface.
Depending on the strike surface, the same drop height could result in different acceleration
levels and pulse durations. Theoretically, the drop height needed to achieve the appropriate
acceleration levels can be determined from Equations (1) and (2) and the associated Figure 3,
where H is the drop height and C is the rebound co-efficient (1,0 for no rebound, 2,0 for full
rebound). However, this equation does not include the strike surface effect.
Experiments with different strike surfaces can be necessary to achieve the desired peak value
and duration.
 
πt
 
A(t)= A sin (1)
 
t
w
 
 2A t 
0 w
2gH = A sin 
(2)
 
Cπ
 
Figure 3 – Typical shock test half-sine pulse graphic and formulae
Once the specified drop parameters (acceleration level, duration and pulse shape) are
achieved, the PCB response acceleration and strain shall be measured. The strain rate shall
also be calculated by dividing the change in strain value by the time interval during which this
change occurred. The characterized board response (acceleration, strain and strain rate) and
its variation shall be documented and provided with the test data. Although it is recommended
that this characterization be performed for previously untested components, this may not be
required if such characterization data are available for a similar sized component.
5.3 Drop testing
With test parameters adjusted and PCB response characterized, the PCB assemblies shall be
prepared for drop testing. This involves soldering cables to the plated-through holes on one end
of the board, mounting the board on the drop fixture with components facing down, and
connecting cables to the event detector/data logger. Since the dynamic response of the board
can be affected by the mass and stiffening of the connector, it is recommended that no
connectors are used and wires are directly soldered to the board.
The event detector’s threshold resistance shall be set to no more than 1 000 Ω. The system
used for such event detections shall have a 55 MHz scan rate or 0,2 μs (or lower) event
detection window. Proper strain relief shall also be provided to cables/wires to avoid a failure
at wires to board interconnects. All cables shall be cleared from the drop path. The initial
resistance of all nets for each assembly shall be measured and logged before conducting the
first drop. The drop test shall be conducted by releasing the drop table from the pre-established

height. The electrical resistance of each net shall be measured in situ during each drop and all
failures shall be logged. The board shall be dropped a required maximum number of times or
until a percentage of all devices has failed, whichever is earlier. The maximum number of drops
or percentage of devices failing shall be consistent with the application. The maximum number
of drops shall be irrespective of single or double-sided assembly. In the event that a shock
condition in addition to the required condition B is used to conduct the test, the maximum
number of drops shall be determined using the acceleration factor between the two conditions
for similar sized components. This acceleration factor shall be reported with the test data.
During the test, the shock pulse shall be measured for each drop to ensure that the input pulse
remains within the specified tolerance. Adjustments in drop height or replacement of strike
surface shall be made if the pulse deviates from that specified.
Depending on the number of components per board, Table 1 shall be used to determine the
number of boards to be tested per component type.
6 Failure criteria and failure analysis
In-situ electrical monitoring of daisy chain nets for failure is required during each drop. The
electrical continuity of all nets shall either be detected by an event detector or by a high-speed
data acquisition system. The event detector shall be able to detect any intermittent discontinuity
of resistance greater than 1 000 Ω lasting for 1 μs or longer. The high-speed data acquisition
system shall be able to measure resistance with a sampling rate of 50,000 samples per second
or greater.
Depending on the monitoring system used, the failure is defined as follows:
– event detector: the first event of intermittent discontinuity as defined above followed by 3
additional such events during 5 subsequent drops.
– high speed data acquisition: the first indication of resistance value of 100 Ω or 20 %
increase in resistance from the initial resistance if initial resistance is greater than 85 Ω
followed by 3 additional such indications during 5 subsequent drops.
A visible partial separation of component from the test board, even without a significant increase
in resistance or intermittent discontinuity, shall also be considered as a failure. This can occur
if the PCB tracks come off the board with the component while maintaining electrical continuity.
As wires soldered to the board for electrical continuity test can also come off during the test, it
is highly recommended that all electrical connections be checked once a failure is indicated to
ensure that the failure is due to a component to board interconnection failure.
All failures after each drop shall be logged. A sufficient number of components from the test lot
shall be subjected to failure analysis to determine the root cause and to identify failure
mechanism. The selection of components shall cover different locations on the board. Different
methods and equipment, such as visual inspection, cross-section, dye and pry, chemical
etching, scanning electron microscopy, and scanning acoustic tomography can be employed to
determine the root cause of failure. The failure site shall be clearly identified as ‘component
failure’, ‘interconnect failure’ or ‘board failure’. For the purpose of this document, the
“interconnect failure” is defined as any failure
a) on the package pad – joint interface or intermetallics,
b) through the joint material,
c) on the PCB pad joint interface or intermetallics.
The above criteria may always be overridden by an applicable procurement document.

– 14 – IEC 60749-37:2022 © IEC 2022
Data analysis shall be conducted showing mean and standard deviation of failure data
according to component groupings. Weibull and/or log normal analysis result shall also be
included if sufficient quantities have failed for such analyses.
7 Summary
All test reports shall include the following information:
a) number of packages per board;
b) package and PCB assembly weight;
c) package geometrical details including body size, lead size, ball size, layer thickness and die
size;
d) package materials including mould compound, die attach, substrate;
e) PCB information, including materials, surface finishes, pad design type, board thickness,
layer count and etc.;
f) board geometry, material and material properties such as thickness, pad size, modulus and
T ;
g
g) board assembly details including stencil thickness, apertures, stencil material, solder alloy
and paste, reflow profile and other board assembly process details;
h) test details: drop height, strike surface, shock pulse profile;
i) board response (acceleration, strain and strain rate);
j) shock table response (shock parameter including peak acceleration, velocity change, time
duration, number of spots/locations on table tested and repetitions, tolerance report of those
measurements; filtering frequency for acceleration;
k) initial resistance of daisy chain nets;
l) failure detection equipment and failure criteria;
m) test results including the number of drops to failure for each location on each test board,
failure mechanisms and representative pictures;
n) data analysis showing mean and standar
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