IEC 62215-3:2013
(Main)Integrated circuits - Measurement of impulse immunity - Part 3: Non-synchronous transient injection method
Integrated circuits - Measurement of impulse immunity - Part 3: Non-synchronous transient injection method
IEC 62215-3:2013 specifies a method for measuring the immunity of an integrated circuit (IC) to standardized conducted electrical transient disturbances. The disturbances, not necessarily synchronized to the operation of the device under test (DUT), are applied to the IC pins via coupling networks. This method enables understanding and classification of interaction between conducted transient disturbances and performance degradation induced in ICs regardless of transients within or beyond the specified operating voltage range.
Circuits intégrés - Mesure de l'immunité aux impulsions - Partie 3: Méthode d'injection de transitoires non synchrones
La CEI 62215-3:2013 spécifie une méthode pour mesurer l'immunité d'un circuit intégré (CI) aux perturbations transitoires électriques conduites normalisées. Les perturbations, non nécessairement synchronisées sur le fonctionnement du dispositif en essai (DUT, device under test), sont appliquées aux broches du circuit intégré via des réseaux de couplage. Cette méthode permet de comprendre et de classer les interactions entre des perturbations transitoires conduites et la dégradation de fonctionnement induite dans les circuits intégrés indépendamment des transitoires à l'intérieur ou au-delà de la gamme de tensions de fonctionnement spécifiées.
General Information
Standards Content (Sample)
IEC 62215-3 ®
Edition 1.0 2013-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Integrated circuits – Measurement of impulse immunity –
Part 3: Non-synchronous transient injection method
Circuits intégrés – Mesure de l'immunité aux impulsions –
Partie 3: Méthode d'injection de transitoires non synchrones
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IEC 62215-3 ®
Edition 1.0 2013-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Integrated circuits – Measurement of impulse immunity –
Part 3: Non-synchronous transient injection method
Circuits intégrés – Mesure de l'immunité aux impulsions –
Partie 3: Méthode d'injection de transitoires non synchrones
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX V
ICS 31.200 ISBN 978-2-8322-0994-3
– 2 – 62215-3 © IEC:2013
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 General . 8
5 Coupling networks . 9
5.1 General on coupling networks . 9
5.2 Supply injection network . 9
5.2.1 Direct injection . 9
5.2.2 Capacitive coupling . 10
5.3 Input injection . 10
5.4 Output injection . 11
5.5 Simultaneous multiple pin injection . 12
6 IC configuration and evaluation . 12
6.1 IC configuration and operating modes . 12
6.2 IC monitoring . 13
6.3 IC performance classes . 13
7 Test conditions . 14
7.1 General . 14
7.2 Ambient electromagnetic environment . 14
7.3 Ambient temperature . 14
7.4 IC supply voltage . 14
8 Test equipment . 14
8.1 General requirements for test equipment . 14
8.2 Cables . 14
8.3 Shielding . 14
8.4 Transient generator . 14
8.5 Power supply . 14
8.6 Monitoring and stimulation equipment . 14
8.7 Control unit . 15
9 Test set up . 15
9.1 General . 15
9.2 EMC test board . 15
10 Test procedure . 17
10.1 Test plan . 17
10.2 Test preparation . 17
10.3 Characterization of coupled impulses . 17
10.4 Impulse immunity measurement . 17
10.5 Interpretation and comparison of results . 18
10.6 Transient immunity acceptance level . 18
11 Test report . 18
Annex A (informative) Test board recommendations . 19
Annex B (informative) Selection hints for coupling and decoupling network values . 24
Annex C (informative) Industrial and consumer applications . 26
Annex D (informative) Vehicle applications . 29
62215-3 © IEC:2013 – 3 –
Figure 1 – Typical pin injection test implementation . 9
Figure 2 – Supply pin direct injection test implementation . 10
Figure 3 – Supply pin capacitive injection test implementation . 10
Figure 4 – Input pin injection test implementation . 11
Figure 5 – Output pin injection test implementation . 12
Figure 6 – Multiple pin injection test implementation . 12
Figure 7 – Test set-up diagram . 15
Figure 8 – Example of the routing from the injection port to a pin of the DUT . 16
Figure A.1 – Typical EMC test board topology. 22
Figure A.2 – Example of implementation of multiple injection structures . 23
Table A.1 – Position of vias over the board . 19
Table C.1 – Definition of pin types . 26
Table C.2 – Test circuit values . 27
Table C.3 – Example of IC impulse test level (IEC 61000-4-4) . 28
Table D.1 – IC pin type definition . 29
Table D.2 – Transient test level 12 V (ISO 7637-2) . 30
Table D.3 – Transient test level 24 V (ISO 7637-2) . 31
Table D.4 – Example of transient test specification . 32
– 4 – 62215-3 © IEC:2013
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
INTEGRATED CIRCUITS –
MEASUREMENT OF IMPULSE IMMUNITY –
Part 3: Non-synchronous transient injection method
FOREWORD
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