kSIST FprEN IEC 63287-3:2026

SLOVENSKI STANDARD
oSIST prEN IEC 63287-3:2025
01-februar-2025
Polprevodniški elementi - Splošne smernice za kvalifikacijo polprevodnikov - 3.
del: Smernice za načrtovanje ocenjevanja zanesljivosti močnostnega
polprevodniškega modula
Semiconductor devices - Generic semiconductor qualification guidelines - Part 3:
Guidelines for reliability qualification plans for power semiconductor module
Dispositifs à semiconducteurs - Lignes directrices génériques concernant la qualification
des semiconducteurs - Partie 3: Lignes directrices pour les plans de qualification de la
fiabilité des modules à semiconducteurs de puissance
Ta slovenski standard je istoveten z: prEN IEC 63287-3:2024
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
oSIST prEN IEC 63287-3:2025 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

oSIST prEN IEC 63287-3:2025
oSIST prEN IEC 63287-3:2025
47/2873/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 63287-3 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2024-10-25 2025-01-17
SUPERSEDES DOCUMENTS:
47/2815/CD, 47/2832/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
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TITLE:
Semiconductor devices - Generic semiconductor qualification guidelines - Part 3: Guidelines
for reliability qualification plans for power semiconductor module

PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
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1 CONTENTS
3 FOREWORD . 4
4 INTRODUCTION . 6
5 1 Scope . 7
6 2 Normative reference . 7
7 3 Terms and definitions . 7
8 4 Product categories and applications . 8
9 4.1 Quality grade by application . 8
10 4.2 Definition of quality grade（Example） . 8
11 5 Failure . 9
12 5.1 Failure distribution . 9
13 5.2 Early failure period . 11
14 5.2.1 Description . 11
15 5.2.2 Early failure rate . 12
16 5.2.3 Screening (Reduction of early failure) . 13
17 5.3 Random failure period . 13
18 5.3.1 Description . 13
19 5.3.2 Failure rate in the random failure period . 13
20 5.4 Wear-out failure period . 13
21 5.4.1 Description . 13
22 6 Reliability test . 16
23 6.1 Reliability test methods . 16
24 6.2 Acceleration models for reliability tests . 18
25 7 Stress test methods . 18
26 8 Summary table of assumptions . 19
27 9 Summary . 21
28 Annex A . 22
29 Bibliography . 31
31 Figure 1 – Bath-tub curve . 11
32 Figure 2 – Failure process of power semiconductor module manufacturing lots during
33 the early failure period . 12
34 Figure 3– Conceptual diagram of the wear-out failure . 14
35 Figure 4 – Conceptual diagram of the accelerated reliability test . 14
36 Figure A.1 – The gate oxide breakdown mechanism . 22
37 Figure A.2 – Relationship between electric field strength and lifetime . 23
38 Figure A.3 – The relationship between the stress application time and the gate oxide
39 breakdown time . 24
40 Figure A.4 – TDDB Weibull plot . 24
41 Figure A.5 – Relationship between the electric field strength 1/E and the oxide
42 breakdown lifetime tBD . 25
43 Figure A.6 – Relationship between the gate oxide lifetime and the failure rate . 26

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44 Figure A.7 – Relationship between the gate oxide lifetime and the cumulative failure
45 probability . 26
46 Figure A.8 – The breakdown voltage distribution of gate oxide . 27
47 Figure A.9 – Voltage screening flow of gate oxide of power MOSFETs . 27
48 Figure A.10 – An example of the Weibull plot before and after screening . 28
49 Figure A.11 – The flow of the test using the voltage step stress method . 30
50 Figure A.12 – An example of the TDDB evaluation of semiconductor devices found
51 acceptable in the screening, using the voltage step stress method . 31
53 Table 1 – Definition of quality grade . 8
54 Table 2 – Accelerated lifetime test methods and purpose . 16
55 Table 3 – Stress test methods and purpose . 18
56 Table 4 – Accelerating factors, calculation formulae and numerical values . 20
57 Table A.1 – Comparison between the voltage screening and the burn-in test . 28
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60 INTERNATIONAL ELECTROTECHNICAL COMMISSION
61 ____________
63 SEMICONDUCTOR DEVICES –
64 GENERIC SEMICONDUCTOR QUALIFICATION GUIDELINES –
66 Part 3: Guidelines for reliability qualification plans for power
67 semiconductor module
70 FOREWORD
71 1) The International Electro technical Commission (IEC) is a worldwide organization for standardization comprising
72 all national electro technical committees (IEC National Committees). The object of IEC is to promote international
73 co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
74 in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
75 Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their
76 preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
77 may participate in this preparatory work. International, governmental and non-governmental organizations liaising
78 with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
79 Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
80 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
81 consensus of opinion on the relevant subjects since each technical committee has representation from all
82 interested IEC National Committees.
83 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
84 Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
85 Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
86 misinterpretation by any end user.
87 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
88 transparently to the maximum extent possible in their national and regional publications. Any divergence between
89 any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
90 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
91 assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
92 services carried out by independent certification bodies.
93 6) All users should ensure that they have the latest edition of this publication.
94 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
95 members of its technical committees and IEC National Committees for any personal injury, property damage or
96 other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
97 expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications.
98 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
99 indispensable for the correct application of this publication.
100 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
101 rights. IEC shall not be held responsible for identifying any or all such patent rights.
102 International Standard IEC 63287-3 has been prepared by IEC technical committee 47:
103 Semiconductor devices.
104 The text of this International Standard is based on the following documents:
FDIS Report on voting
47 /XX/FDIS 47 /XX/RVD
106 Full information on the voting for the approval of this International Standard can be found in the
107 report on voting indicated in the above table.
108 This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

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109 A list of all parts in the IEC 63287 series, published under the general title semiconductor
110 devices –generic semiconductor qualification guidelines, can be found on the IEC website.
111 The committee has decided that the contents of this document will remain unchanged until the
112 stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
113 the specific document. At this date, the document will be
114 • reconfirmed,
115 • withdrawn,
116 • replaced by a revised edition, or
117 • amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates that it
contains colours which are considered to be useful for the correct understanding of its
contents. Users should therefore print this document using a colour printer.
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120 INTRODUCTION
121 When performing qualification tests, semiconductor device vendors prepare a specific reliability test
122 plan upon consultation with semiconductor device users in order to efficiently carry out the reliability
123 test.
125 This guideline presents examples of methods for preparing test plans to determine appropriate reliability
126 test conditions, based on the level of quality required in the operating environments of various
127 applications of power semiconductor modules. As a target of reliability, grades have been specified for
128 each of the following applications: automotive, industrial and consumer electronics. Based on the
129 number of annual operating hours, use period and other parameters assumed for each grade, this
130 guideline defines verification methods for the wear-out failure, and proposes appropriate reliability tests.
131 This guideline defines the concept of quality assurance from early failure to wear-out failure. It also
132 presents approaches to appropriately ensure the reliability of power semiconductor modules.
134 The test conditions and the acceleration factor values presented in this guideline are only examples
135 used for setting reliability test conditions to verify a required level of quality.
137 NOTE Qualification tests are tests performed by power semiconductor device vendors,
138 taking into account the quality required by the users of their products.

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139 SEMICONDUCTOR DEVICES ––
140 GENERIC SEMICONDUCTOR QUALIFICATION GUIDELINES –
142 Part 3: Guidelines for reliability qualification plans for power
143 semiconductor module
145 1 Scope
146 This part of the IEC 63287 provides guidelines for a reliability qualification plan for power semiconductor
147 modules to assure reliability targets over the entire product life.
148 Here, the term power semiconductor module refers to multichip semiconductor power modules as
149 defined below in 3.3.
150 Power semiconductor modules with incorporated control circuits are excluded. Clamped packages that
151 need external pressure for being mounted in a system are excluded, e.g. disc-type pressure pack
152 devices.
153 This document is not intended for medical, military, aeronautics and astronautics-related applications.
154 2 Normative reference
155 The following documents are referred to in the text in such a way that some or all of their content
156 constitutes requirements of this document. For dated references, only the edition cited applies.
157 For undated references, the latest edition of the referenced document (including any
158 amendments) applies.
159 IEC 60191-4, Mechanical standardization of semiconductor devices - Part 4: Coding system
160 and classification into forms of package outlines for semiconductor device packages
161 IEC 63287-1, Semiconductor devices - Generic semiconductor qualification guidelines - Part 1:
162 Guidelines for IC reliability qualification
164 3 Terms and definitions
165 For the purpose of this document, the following terms and definitions apply.
166 ISO and IEC maintain terminological databases for use in standardization at the following
167 addresses:
168 • IEC Electropedia: available at http://www.electropedia.org/
169 • ISO Online browsing platform: available at http://www.iso.org/obp
171 3.1
172 failure mode
173 classification of a fault phenomenon which causes product failure
174 Note 1 to entry disconnection, a short circuit, occasional loss, abrasion, characteristic
175 deterioration, etc. are typical items considered as failure modes
176 3.2
177 failure mechanism
178 physical, chemical or other process that results in a failure mode, which leads to a product that
179 fails to meet functional requirements

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180 3.3
181 power module
182 isolated or non-isolated semiconductor module with two or more semiconductor chips
183 according to the package outline style code “MP” specified in IEC 60191-4
184 Note 1 to entry: The predominantly used package body material is plastic (including epoxy)
185 according to IEC 60191-4 and both the frame based and resin based embodiment are
186 possible.
188 3.4
189 mode A failures
190 early failures with a decreasing failure rate due to extrinsic defects
191 3.5
192 mode B failures
193 random failures with relatively constant failure rate. The end of mode B regime limits the use
194 period of a power semiconductor module
195 3.6
196 mode C failures
197 wear-out failures with increasing failure rate due to intrinsic limitation of lifetime
199 3.7
200 bathtub curve
201 a plot of failure rate versus time or cycles that exhibits three phases of life: infant mortality
202 (decreasing failure rate), random failure period (relatively constant failure rate), and intrinsic
203 wear-out (increasing failure rate)
205 4 Product categories and applications
206 4.1 Quality grade by application
207 Level of quality, operating hours and operating environment required for power semiconductor
208 modules in the market are varied, depending on the application of products for which power
209 semiconductor modules are used. As an example of a method for preparing test plans, this
210 guideline has grouped the applications into three major grades of requirements, namely the
211 automotive, the industrial and the consumer electronics application. And for each grade, the
212 required level of quality and its preconditions are defined, as shown in Table 1.
213 4.2 Definition of quality grade（Example）
214 Table 1 – Definition of quality grade
Grade I II III
Description of Automotive application Industrial application Consumer electronics
grade application
Example of Powertrains, DC/DC Motor controls, Power Air conditioners, Home
application Converter, OBC, Power converters, Robots, appliances, etc.
steering, etc.
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Machine tools, Railway,
etc.
Annual 500 hours (driving Up to 8760 hours; Up to 8760 hours;
operating hours) varies depending on varies depending on
hours The operation differs application. application.
between when it works
with KEY ON/OFF and
when it does not work
with KEY ON/OFF.
10~20 years (cumulative
Use period 15 years (cumulative 5~10 years
failure probability:1%);
failure probability: <1%) (cumulative failure
varies depending on
probability:1%);
application.
varies depending on
application.
Operating For engine T = -20°C (min)/100°C T = 0°C (min)/70 °C
a a
environment compartment: (max) (max)
assumed Ta= -40 °C (min)/125°C Tj = 70 °C (typ)/125°C Tj = 70°C (typ)/105 °C
(varies (max) (max) (max)
depending on Tj= 100°C (typ)/150°C RH=10 (min)/80 (max)% RH= 10 (min)/80
a
application) (max) RH typ. (20% when (max)%
RH=0 (min)/100 (max)% being energized) RH typ. (20% when
RH typ. (10% when (60% when being de- being energized)
driving) energized) (60% when being de-
(70% when stopping) energized)
Early failure 1 ppm/year or less 50 to 100 ppm/year or 100 ppm/year or less;
rate less; varies depending on
varies depending on application.
application.
Failure rate in 1 FIT or less 50 to 100 FIT or less; 100 FIT or less;
the random varies depending on varies depending on
failure period application. application.
NOTE The values shown in Table 1 are only examples. In real business life, these conditions are set
according to market and customer requirements.
a
as an alternative, the limiting values according to the climatic classes reported in IEC 60721 should
be used as boundary conditions for a mission profile of climatic conditions (Ta, RH)
216 5 Failure
217 5.1 Failure distribution
218 The failure distribution of power semiconductor modules has been divided into three major areas: early
219 failure, random failure and wear-out failure. Figure 1 shows the bathtub curve representing the
220 relationship between the field use time and the instantaneous failure rate. Each of the three areas is
221 described in detail in 5.2 to 5.4.
223 In the case of power semiconductor modules, most modules that may cause early failures are rejected

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224 in the power semiconductor modules vendors’ screening process, such as in the burn-in test. However,
225 some defective power semiconductor modules fail to be sorted out, and cause failures relatively soon
226 after they start operating in the market. It is generally known that with power semiconductor modules,
227 more Mode B failures take place than early failures. This is because the gate oxide of power
228 semiconductor modules is thicker than that of integrated circuits (IC) or large scale integration devices
229 (LSI). There are cases in which both the early failure rate and the mode-B failure rate keep declining.
230 When there are few early failures due to adequate pre-shipment screening, and there are only limited
231 Mode B failures, however, random failures will become dominant failures in the random failure period.
232 In this case, the Weibull shape parameter m often gets closer to 1.
234 In reality, the instantaneous failure rate in the random failure period should be considered as a
235 superposition of 1) early failures, whose instantaneous failure rate declines according to the theory, and
236 2) random failures, whose instantaneous failure rate is kept constant. Depending on the proportion
237 between the early failures and the random failures, it is often observed that the instantaneous failure
238 rate in the random failure period continues to decline. The random failures have been attributed not only
239 to internal factors, but also to external factors including ESD and EOS.
241 The wear-out failure period has been defined as the period in which failures are caused by the end-of-
242 life of wire bonding, solder bonding and the like of power semiconductor modules and other parts that
243 compose a power module. Other causes for wear-out failures include the end-of-life of cells,
244 interconnects, etc. that compose a semiconductor device such as a power MOSFET or IGBT. In other
245 words, the wear-out failure period is a period when the end-of-life of the power modules themselves has
246 been observed. The number of failures increases over the course of time, and eventually all power
247 semiconductor modules will fail. For wear-out failures, there has been no concept for setting upper limits
248 or criteria for the failure rate. It is important to design power semiconductor modules in such a way as
249 not to allow any wear-out failures to take place during their use period. In general, the criterion for
250 determining the life of a power semiconductor module is the period up until the start of wear failure until
251 the cumulative failure probability rises.
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Wear-out failure
period
Real life capacity
(Confirmed at element level)
Accelerated reliability test
(Checked with products)
Wear-out
failure
Use period
Pre-shipment
Early failure
Random failure
screening at
period
period
power
semiconductor
Early failure
module vendors
Random failure
Field use time
255 Figure 1 – Bath-tub curve
256 5.2 Early failure period
257 5.2.1 Description
258 Power semiconductor modules are susceptible to defects derived from their manufacturing process, as
259 they are highly integrated and complex. The ratio of these power semiconductor modules, which
260 conform to their specification, is referred to as “yield.” In the sorting, all possible parameters relating to
261 the characteristic and functional requirements have been measured to select conforming semiconductor
262 devices. Even if they function normally in the sorting process, however, some of the selected conforming
263 semiconductor devices may have minor hidden defects that do not have any electrical effects (latent
264 failures). When a high yield is achieved, it is less likely that power semiconductor modules with latent
265 failures have been mixed into conforming semiconductor devices.
266 When a small quantity of conforming power semiconductor modules with latent failures are included in
267 a production lot, the failure rate will decrease over the course of time. This is because defect-free
268 semiconductor devices with low-failure probability remain in the batch even after power semiconductor
269 modules with latent failures fail and are removed. In such a case, the Weibull shape parameter m, on
270 the assumption that the Weibull distribution applies, is less than 1 (m<1).
271 To be more specific, as shown in Figure 2, when a small quantity of conforming power semiconductor
272 modules with latent failures is contained in a production lot, electronic equipment using these modules
273 becomes defective in operation during the early failure period. Hence, the broken semiconductor devices
274 will be removed in the repair of the electronic equipment (part replacement). Eventually, highly reliable
275 power semiconductor modules will remain.
Instantaneous failure rate
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Population of
Failure
Failure
manufacturing lots of
power semiconductor
devices
Defect
Individual
Failure
power
semiconductor
devices
Immediately after manufacturing After a certain period of
After long-term use
of power semiconductor devices time has passed
(Semiconductor devices containing defects cause a (Semiconductor devices containing no
failure and are removed) defect remain after time has passed)
IEC
278 Figure 2 – Failure process of power semiconductor module manufacturing lots during
279 the early failure period
281 A primary countermeasure against such early failures is to reduce defects generated in the
282 manufacturing process. When practicable, design change may work as an effective
283 countermeasure to make power semiconductor modules unsusceptible to defects.
285 5.2.2 Early failure rate
286 5.2.2.1 Early failure rate definition
287 The early failure rate represents the rate of failures taking place in the defined early failure period in
288 terms of % or ppm (parts per million).
289 The early failure probability represents the probability of degradation failures derived from manufacturing
290 defects that take place after shipment from semiconductor device manufacturers, within one year from
291 the start of operation in the market (end users) or in the manufacturing process of system manufacturers
292 (the defined early failure period).
293 In some cases, the term “mean early failure rate” has been used. The mean failure rate is obtained by
294 dividing the number of failures taking place during the defined failure period by total operating time. The
295 mean early failure rate is obtained by converting the cumulative failure probability in the defined early
296 failure period to the probability per unit time, and it is mainly expressed in terms of FIT (Failures In Time:
－
297 10 /h).
299 5.2.2.2 Cumulative fail probability
300 There are 2 methods to calculate the mean early failure rate including the following 1)~2）
301 1) A method to use actual market data acquired during the early failure period (for one year after the start
302 of shipment of mass-produced power semiconductor modules),
303 2) A method to perform calculation in a short period of time by conducting reliability tests accelerated by
304 applying an acceleration factor to actual operating conditions.
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307 5.2.3 Screening (Reduction of early failure)
308 Power semiconductor modules are used in a variety of applications and it is important to ensure the
309 right quality level for each application. Under such circumstances, customers and the market demand
310 the reduction of early failures as an improvement in quality level.
311 In the case of IGBTs, failures in the low breakdown voltage region due to gate oxide film defects have
312 been reported as early failures of power semiconductor modules, and in the case of power MOSFETs,
313 avalanche failures due to device defects have been reported. As a method to reduce these early
314 failures, there are gate oxide screening for IGBTs and avalanche screening for power MOSFETs.
315 In this guideline, the IGBT gate screening method is described in "Annex A" as an example of the early
316 failure reduction method.
318 5.3 Random failure period
319 5.3.1  Description
320 In general, the random failure period has been defined as period from end of the early failure period to
321 start of the wear-out failure period. It is appropriate to consider that failures caused after the end of the
322 defined early failure period are attributed not only to those remaining defective power semiconductor
323 modules, which were not removed in the pre-shipment sorting, but also to disturbance or random factors,
324 which are not related to manufacturing defects. In the case of power semiconductor modules, however,
325 there are extremely few remaining defective semiconductor devices to cause early failures which were
326 not removed in the sorting. The shape parameter of the Weibull distribution is usually almost constant
327 (m≒1).
329 5.3.2  Failure rate in the random failure period
330 The mean failure rate in the random failure period can be calculated by using the same methods as the
331 mean early failure rate described below:
332 1) A method to use actual market data acquired during the random failure period (for the end of the early
333 failure period to the end of use period),
334 2) A method of calculation based on the data obtained from the evaluation of accelerated tests,
336 5.4 Wear-out failure period
337 5.4.1  Description
338 Wear-out failures represent the end of the lifetime of semiconductor devices themselves. All power
339 semiconductor modules fail sooner or later when they enter the wear-out period. In other words, the
340 wear-out failures must not be allowed to take place before the end of use period. Every power
341 semiconductor device vendor adopts “reliability design” so as to take actions at the design stage to
342 prevent occurrence of wear-out failures during the use period. In the wear-out failure period, the shape
343 parameter m of the Weibull distribution is above 1 (m＞1), which reflects the end of the lifetime of power
344 semiconductor modules.
345 The following contents of this clause explain a methodology to calculate the sample size and the test
346 duration, which are needed to verify that the wear out regime is not entered during the use period by
347 means of a product reliability qualification. The methodology can be applied, if the mission profile, the
348 acceleration model and the end-of-life failure distribution are known or if at least reasonable assumptions
349 can be made. If this information is missing, the application of a standardized test duration according to
350 clause 6 and sample sizes according to clause 9 is recommended.

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351 Based on the conceptual diagrams, the method to calculate the number of samples taken in an
352 accelerated reliability test and the duration of an accelerated reliability test is described below.
lnln(1/(1－F(t)))
Reliability level in
m＞1
the market to be
checked
Wear-out failure
T
l mode
Early failure
period
Wear-out failure period
Reliability
goals
ln(t)
F0
ts
t＝t＋T
l s l
Shipment
Random failure period
355 Figure 3– Conceptual diagram of the wear-out failure
lnln(1/(1－F(t)))
Failure distribution
assumed in
accelerated
reliability test
m＞1
m＞1
F
i
Reliability level in
the market to be
F0
checked
ln(t)
t t t t
s 0 i l
358 Figure 4 – Conceptual diagram of the accelerated reliability test
359 The time to reach a failure probability in the accelerated reliability test t , which is equivalent to the actual
360 operating time up to the end of the use period t , can be expressed as:
l
𝑡
l
361    𝑡 = ··································································································· (10)
𝐴𝑐𝑐
362 Where:
363 tl ＝ ts ＋ Tl
364 ts ：value of actual operating time converted from pre-shipment screening time
365 Tl ：use period
366 A ：acceleration factor
cc
367 By using the level of confidence of g % (CL = g %) and the number of samples ni，the maximum failure
368 rate F - the estimated cumulative failure probability – as calcualted from the binominal distribution (with
i
369 the number of failures equals 0) can be expressed as:
ｇ
𝑛𝑖
370   F ＝ 1 － (1－ ) ······················································································ (11)
i
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371 Equation (11) can also be expressed as:
ｇ
ln(1－ )
··············································································· (12)
n ＝
i
ln(1－Fi)
373 The cumulative failure probability for the failure distribution assumed in the accelerated reliability test
374 can be expressed as:
𝑚
ｔ
i
375   F ＝ 1 － exp(－ ) ················································································ (13)
i
𝑚
𝜂
𝑚
𝑡
376   F0 ＝ 1 － exp(－ ) ················································································ (14)
𝑚
𝜂
377 Where:
378 t = duration of pre-shipment tests including screening
i
379 F = cumulative failure probability to be checked during the use period
380 η = scale parameter of the Weibull distribution
382 The following equation is obtained from the above Weibull equations :
m
m
ln(1－F)
i t A
i cc
×
＝ ＝ ti  ······································· (15)
ln(1－F0) t0 tl
384 Once the level of confidence g % (CL = g %) and the number of samples n is determined, the
i
385 estimated cumulative failure rate F can be obtained. By using the cumulative failure probability
i
386 that has to be checked during the use period F and equation (15), the duration of pre-shipment
387 tests including screening t can be calculated as :
i
ln(1－Fi) tl ln(1－F )
i
m m
ti ＝ t0
······················ (16)
＝
ln(1－F ) A ln(1－F )
0 cc 0
389 When the binominal distribution has been applied with the number of failures of 0, the duration of pre-
390 shipment tests including screening ti can be expressed as :
ｇ ｇ
1 1
ln(1－ ) ln(1－ )
tl
100 100
m m
ti ＝ t0
＝
n ×ln(1－F ) A n ×ln(1－F )
i 0 cc i 0 ··········· (17)
392 When the test is performed using samples for which pre-shipment screening equivalent to actual
393 operating time of ts has been conducted, the duration of the test excluding the pre-shipment screening
394 Ti can be expressed as :
𝑡
s
395   Ti ＝ ti －
𝐴𝑐𝑐
396 By using the duration of the test excluding the pre-shipment screening Ti，the cumulative failure
397 probability that has to be checked during the useful time F0 and Equation (15), the estimated
398 cumulative failure rate Fi , can be obtained. The number of samples ni can be calculated based on the
399 level of confidence of g % (CL＝g %).
𝑡
s
400   t ＝ T ＋
i i
𝐴𝑐𝑐
oSIST prEN IEC 63287-3:2025
IEC CDV 63287-3 © IEC 2024 – 16 – 47/2873/CDV

m
A
cc
t
F ＝ 1 － exp i× ×ln(1－F )  ········································ (18)
i 0
t
l
402 When the binominal distribution is applied with the number of failures of 0, the number of samples ni can
403 be expressed as:
ｇ ｇ
m
m
ln(1－ ) ln(1－ )
t 100 t 100
0 l
n ＝ ×
i
× ＝
ln(1－F )
t ln(1－F ) A ×t  · (19)
i 0 cc i
405 6 Reliability test
406 6.1  Reliability test methods
407 Table 2 shows reliability test items for products (in the form of finished products). This guideline presents
408 a common scope of tests, taking account of the industrial standards and the JEDEC standards. However,
409 the test scope can be changed as long as it is large enough to verify that the cumulative wear out failure
410 probability in the use period is 1% or less. For an assessment of the random failure probability both
411 methods mentioned in 5.3.2 may be applied. In most tests, stress conditions can be accelerated by
412 changing parameters such as voltage, temperature and humidity. Through acceleration of stress
413 conditions, reliability in the use period can be verified in a short period of time.
414 Power semiconductor modules are operated at high voltage and high current. It is desirable to
415 perform the reliability test after the packaging process, partly because high voltage and high
416 current cannot be applied to the wafers, and partly because heat dissipation of the packages
417 has an impact on the reliability test results. For TDDB, however, the reliability test may be
418 performed on the wafers in order to make the total duration of the TDDB reliability test, including
419 the time to prepare test samples, reasonably short.
421 Table 2 – Accelerated lifetime test methods and purpose
Refer to test
Test item Objective Failure phenomena Remark
standard
IEC60749-23 TDDB due to
IEC60747-9 electrical field, time-
To evaluate durability dependent
by applying electrical breakdown due to
High-temperature
and thermal off-state variation of
reverse bias test
static load to characteristics, chip-
semiconductor devices package interaction
by movable charges
(ions)
IEC60749-23 To evaluate durability
High-temperature gate IEC60747-9 or lifetime by applying TDDB due to

bias test electrical and thermal electrical field
load to gate dielectric
High-temperature IEC60749-5 To evaluate durability Galvanic corrosion of Recommend
humidity bias test for the case where metal interconnects, 85°C/85% RH
(takes priority over semiconductor devices Ion migration See relevant

oSIST prEN IEC 63287-3:2025
IEC CDV 63287-3 © IEC 2024 – 17 – 47/2873/CDV

“temperature humidity are used in high- between metal standards for
storage test”) temperature and high- interconnects, test voltage
humidity ambience Increase of leakage
current due to
moisture
IEC60749-5 To evaluate durability
Corrosion of metal
for the case where
interconnects，
Temperature humidity semiconductor devices Recommend
increase of leakage
storage test are stored in high- 85°C/85% RH
current due to
temperature and high-
moisture
humidity ambience
IEC60749-25 To evaluate durability
by exposing
Cracks in solder，
semiconductor devices
cracks in chips,
Temperature cycling test to cyclic temperature
cracks in passivation
swing between high
film
temperature and low
temperature
IEC60749-6 Reference
test
high-
To evaluate durability of
temperature
semiconductor devices
High-temperature reverse bias
when they are stored at
storage test test or high-
a high temperature for
temperature
prolonged time
gate bias test
can be used
as substitute
IEC60068-2-1 This test
To evaluate durability of
should only
semiconductor devices
Low-temperature be required if
when they are stored at
storage test demanded by
a low temperature for
the
prolonged time
application
IEC60749-34 To evaluate durability
against change of
electrical or thermal
stress when electrical
Power cycling test stress is applied to
semiconductor devices
in a cyclic manner
between on-state and
off-state
JEDEC JEP151 To evaluate the EOS caused by
durability against SEB terrestrial neutrons. Optional test
SEB
(Single Event Burn-out)
failure
oSIST prEN IEC 63287-3:2025
IEC CDV 63287-3 © IEC 2024 – 18 – 47/2873/CDV

NOTE SEB occur accidentally on the market and their destruction voltage depends on the device structure and
applied voltage. Therefore, it is desirable to confirm the SEB tolerance test by neutron irradiation at
the product design stage, not the product certification test.
422 6.2  Acceleration models for reliability tests
423 Acceleration models for reliability tests have been referred to in the IEC63287-1 6.4
424 (Acceleration models for reliability tests).
426 7 Stress test methods
427 Stress test methods have been referred to in the IEC63287-1 clause 7 (Stress test methods).
428 Table 3 has been changed as follows:
430 Table 3 – Stress test methods and purpose
Refer to test
Test item Failure phenomena Remark
Objective
standard
IEC60749-15 Cracks in packages,
Not appli
...